2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola,Inc.
4 * Xianghua Xiao<X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
27 * The processor starts at 0xfffffffc and the code is first executed in the
28 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
52 * Set up GOT: Global Offset Table
54 * Use r14 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(_FIXUP_TABLE_)
61 GOT_ENTRY(_start_of_vectors)
62 GOT_ENTRY(_end_of_vectors)
63 GOT_ENTRY(transfer_to_handler)
67 GOT_ENTRY(__bss_start)
71 * e500 Startup -- after reset only the last 4KB of the effective
72 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
73 * section is located at THIS LAST page and basically does three
74 * things: clear some registers, set up exception tables and
75 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
76 * continue the boot procedure.
78 * Once the boot rom is mapped by TLB entries we can proceed
79 * with normal startup.
88 lis r1, PVR_85xx_REV1@h
89 ori r1, r1, PVR_85xx_REV1@l
93 /* Semi-bogus errata fixup for Rev 1 */
98 * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
99 * write it back immediately to fixup a Rev 1 bug (Errata CPU4)
100 * for this initial TLB1 entry 0, otherwise the TLB1 entry 0
101 * will be invalidated (incorrectly).
111 * Clear and set up some registers.
112 * Note: Some registers need strict synchronization by
113 * sync/mbar/msync/isync when being "mtspr".
114 * BookE: isync before PID,tlbivax,tlbwe
115 * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
116 * E500: msync,isync before L1CSR0
117 * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
118 * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
122 /* invalidate d-cache */
130 /* disable d-cache */
134 /* invalidate i-cache */
140 /* disable i-cache */
145 /* clear registers */
167 mtspr DBSR,r1 /* Clear all valid bits */
174 mtspr BUCSR,r0 /* disable branch prediction */
177 #if defined(CONFIG_ENABLE_36BIT_PHYS)
182 /* Setup interrupt vectors */
187 mtspr IVOR0,r1 /* 0: Critical input */
189 mtspr IVOR1,r1 /* 1: Machine check */
191 mtspr IVOR2,r1 /* 2: Data storage */
193 mtspr IVOR3,r1 /* 3: Instruction storage */
195 mtspr IVOR4,r1 /* 4: External interrupt */
197 mtspr IVOR5,r1 /* 5: Alignment */
199 mtspr IVOR6,r1 /* 6: Program check */
201 mtspr IVOR7,r1 /* 7: floating point unavailable */
203 mtspr IVOR8,r1 /* 8: System call */
204 /* 9: Auxiliary processor unavailable(unsupported) */
206 mtspr IVOR10,r1 /* 10: Decrementer */
208 mtspr IVOR11,r1 /* 11: Interval timer */
210 mtspr IVOR12,r1 /* 11: Watchdog timer */
212 mtspr IVOR13,r1 /* 13: Data TLB error */
214 mtspr IVOR14,r1 /* 14: Instruction TLB error */
216 mtspr IVOR15,r1 /* 15: Debug */
219 * Invalidate MMU L1/L2
221 * Note: There is a fixup earlier for Errata CPU4 on
222 * Rev 1 parts that must precede this MMU invalidation.
229 * Invalidate all TLB0 entries.
235 * To avoid REV1 Errata CPU6 issues, make sure
236 * the instruction following tlbivax is not a store.
240 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
241 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
242 * region before we can access any CCSR registers such as L2
243 * registers, Local Access Registers,etc. We will also re-allocate
244 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
246 * Please refer to board-specif directory for TLB1 entry configuration.
247 * (e.g. board/<yourboard>/init.S)
252 li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */
254 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
274 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
275 /* Special sequence needed to update CCSRBAR itself */
276 lis r4, CFG_CCSRBAR_DEFAULT@h
277 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
279 lis r5, CFG_CCSRBAR@h
280 ori r5, r5, CFG_CCSRBAR@l
290 lis r3, CFG_CCSRBAR@h
291 lwz r5, CFG_CCSRBAR@l(r3)
296 /* set up local access windows, defined at board/<boardname>/init.S */
298 ori r7,r7,CFG_CCSRBAR@l
302 li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
304 lwzu r5,0(r6) /* how many windows we actually use */
306 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
320 /* Jump out the last 4K page and continue to 'normal' start */
325 mtspr SRR1,r0 /* Keep things disabled for now */
331 * r3 - 1st arg to board_init(): IMMP pointer
332 * r4 - 2nd arg to board_init(): boot flag
335 .long 0x27051956 /* U-BOOT Magic Number */
336 .globl version_string
338 .ascii U_BOOT_VERSION
339 .ascii " (", __DATE__, " - ", __TIME__, ")"
340 .ascii CONFIG_IDENT_STRING, "\0"
342 . = EXC_OFF_SYS_RESET
345 /* Clear and set up some registers. */
348 mtspr DEC,r0 /* prevent dec exceptions */
349 mttbl r0 /* prevent fit & wdt exceptions */
351 mtspr TSR,r1 /* clear all timer exception status */
352 mtspr TCR,r0 /* disable all */
353 mtspr ESR,r0 /* clear exception syndrome register */
354 mtspr MCSR,r0 /* machine check syndrome register */
355 mtxer r0 /* clear integer exception register */
356 lis r1,0x0002 /* set CE bit (Critical Exceptions) */
357 ori r1,r1,0x1200 /* set ME/DE bit */
358 mtmsr r1 /* change MSR */
361 /* Enable Time Base and Select Time Base Clock */
362 lis r0,HID0_EMCP@h /* Enable machine check */
363 ori r0,r0,0x4000 /* time base is processor clock */
364 #if defined(CONFIG_ENABLE_36BIT_PHYS)
365 ori r0,r0,0x0080 /* enable MAS7 updates */
369 #if defined(CONFIG_ADDR_STREAMING)
376 /* Enable Branch Prediction */
377 #if defined(CONFIG_BTB)
378 li r0,0x201 /* BBFI = 1, BPEN = 1 */
382 #if defined(CFG_INIT_DBCR)
385 mtspr DBSR,r1 /* Clear all status bits */
386 lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
387 ori r0,r0,CFG_INIT_DBCR@l
391 /* L1 DCache is used for initial RAM */
395 mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
398 /* Allocate Initial RAM in data cache.
400 lis r3, CFG_INIT_RAM_ADDR@h
401 ori r3, r3, CFG_INIT_RAM_ADDR@l
402 li r2, 512 /* 512*32=16K */
412 /* Calculate absolute address in FLASH and jump there */
413 /*--------------------------------------------------------------*/
414 lis r3, CFG_MONITOR_BASE@h
415 ori r3, r3, CFG_MONITOR_BASE@l
416 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
421 #endif /* CFG_RAMBOOT */
423 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
424 lis r1,CFG_INIT_RAM_ADDR@h
425 ori r1,r1,CFG_INIT_SP_OFFSET@l
429 stwu r0,-4(r1) /* Terminate call chain */
431 stwu r1,-8(r1) /* Save back chain and move SP */
432 lis r0,RESET_VECTOR@h /* Address of reset vector */
433 ori r0,r0, RESET_VECTOR@l
434 stwu r1,-8(r1) /* Save back chain and move SP */
435 stw r0,+12(r1) /* Save return addr (underflow vect) */
443 /* --FIXME-- machine check with MCSRRn and rfmci */
445 .globl _start_of_vectors
448 /* Critical input. */
449 CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
451 /* Machine check --FIXME-- Should be MACH_EXCEPTION */
452 CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
454 /* Data Storage exception. */
455 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
457 /* Instruction Storage exception. */
458 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
460 /* External Interrupt exception. */
461 STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
463 /* Alignment exception. */
471 addi r3,r1,STACK_FRAME_OVERHEAD
473 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
474 lwz r6,GOT(transfer_to_handler)
478 .long AlignmentException - _start + EXC_OFF_SYS_RESET
479 .long int_return - _start + EXC_OFF_SYS_RESET
481 /* Program check exception */
485 addi r3,r1,STACK_FRAME_OVERHEAD
487 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
488 lwz r6,GOT(transfer_to_handler)
492 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
493 .long int_return - _start + EXC_OFF_SYS_RESET
495 /* No FPU on MPC85xx. This exception is not supposed to happen.
497 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
501 * r0 - SYSCALL number
505 addis r11,r0,0 /* get functions table addr */
506 ori r11,r11,0 /* Note: this code is patched in trap_init */
507 addis r12,r0,0 /* get number of functions */
513 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
517 li r20,0xd00-4 /* Get stack pointer */
519 subi r12,r12,12 /* Adjust stack pointer */
520 li r0,0xc00+_end_back-SystemCall
521 cmplw 0, r0, r12 /* Check stack overflow */
532 li r12,0xc00+_back-SystemCall
540 mfmsr r11 /* Disable interrupts */
544 SYNC /* Some chip revs need this... */
548 li r12,0xd00-4 /* restore regs */
558 addi r12,r12,12 /* Adjust stack pointer */
566 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
567 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
568 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
570 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
571 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
573 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
575 .globl _end_of_vectors
582 * This code finishes saving the registers to the exception frame
583 * and jumps to the appropriate handler for the exception.
584 * Register r21 is pointer into trap frame, r1 has new stack pointer.
586 .globl transfer_to_handler
598 andi. r24,r23,0x3f00 /* get vector offset */
602 mtspr SPRG2,r22 /* r1 is now kernel sp */
604 lwz r24,0(r23) /* virtual address of handler */
605 lwz r23,4(r23) /* where to go when done */
610 rfi /* jump to handler, enable MMU */
613 mfmsr r28 /* Disable interrupts */
617 SYNC /* Some chip revs need this... */
632 lwz r2,_NIP(r1) /* Restore environment */
643 mfmsr r28 /* Disable interrupts */
647 SYNC /* Some chip revs need this... */
662 lwz r2,_NIP(r1) /* Restore environment */
664 mtspr 990,r2 /* SRR2 */
665 mtspr 991,r0 /* SRR3 */
679 blr /* entire I cache */
703 .globl icache_disable
707 ori r1,r1,0xfffffffe@l
716 srwi r3, r3, 31 /* >>31 => select bit 0 */
734 .globl dcache_disable
738 ori r1,r1,0xfffffffe@l
749 srwi r3, r3, 31 /* >>31 => select bit 0 */
772 /*------------------------------------------------------------------------------- */
774 /* Description: Input 8 bits */
775 /*------------------------------------------------------------------------------- */
781 /*------------------------------------------------------------------------------- */
783 /* Description: Output 8 bits */
784 /*------------------------------------------------------------------------------- */
790 /*------------------------------------------------------------------------------- */
791 /* Function: out16 */
792 /* Description: Output 16 bits */
793 /*------------------------------------------------------------------------------- */
799 /*------------------------------------------------------------------------------- */
800 /* Function: out16r */
801 /* Description: Byte reverse and output 16 bits */
802 /*------------------------------------------------------------------------------- */
808 /*------------------------------------------------------------------------------- */
809 /* Function: out32 */
810 /* Description: Output 32 bits */
811 /*------------------------------------------------------------------------------- */
817 /*------------------------------------------------------------------------------- */
818 /* Function: out32r */
819 /* Description: Byte reverse and output 32 bits */
820 /*------------------------------------------------------------------------------- */
826 /*------------------------------------------------------------------------------- */
828 /* Description: Input 16 bits */
829 /*------------------------------------------------------------------------------- */
835 /*------------------------------------------------------------------------------- */
836 /* Function: in16r */
837 /* Description: Input 16 bits and byte reverse */
838 /*------------------------------------------------------------------------------- */
844 /*------------------------------------------------------------------------------- */
846 /* Description: Input 32 bits */
847 /*------------------------------------------------------------------------------- */
853 /*------------------------------------------------------------------------------- */
854 /* Function: in32r */
855 /* Description: Input 32 bits and byte reverse */
856 /*------------------------------------------------------------------------------- */
862 /*------------------------------------------------------------------------------- */
863 /* Function: ppcDcbf */
864 /* Description: Data Cache block flush */
865 /* Input: r3 = effective address */
867 /*------------------------------------------------------------------------------- */
873 /*------------------------------------------------------------------------------- */
874 /* Function: ppcDcbi */
875 /* Description: Data Cache block Invalidate */
876 /* Input: r3 = effective address */
878 /*------------------------------------------------------------------------------- */
884 /*--------------------------------------------------------------------------
886 * Description: Data Cache block zero.
887 * Input: r3 = effective address
889 *-------------------------------------------------------------------------- */
896 /*------------------------------------------------------------------------------- */
897 /* Function: ppcSync */
898 /* Description: Processor Synchronize */
901 /*------------------------------------------------------------------------------- */
907 /*------------------------------------------------------------------------------*/
910 * void relocate_code (addr_sp, gd, addr_moni)
912 * This "function" does not return, instead it continues in RAM
913 * after relocating the monitor code.
917 * r5 = length in bytes
922 mr r1, r3 /* Set new stack pointer */
923 mr r9, r4 /* Save copy of Init Data pointer */
924 mr r10, r5 /* Save copy of Destination Address */
926 mr r3, r5 /* Destination Address */
927 lis r4, CFG_MONITOR_BASE@h /* Source Address */
928 ori r4, r4, CFG_MONITOR_BASE@l
929 lwz r5,GOT(__init_end)
931 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
936 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
942 /* First our own GOT */
944 /* the the one used by the C code */
954 beq cr1,4f /* In place copy is not necessary */
955 beq 7f /* Protect against 0 count */
974 * Now flush the cache: note that we must start from a cache aligned
975 * address. Otherwise we might miss one cache line.
979 beq 7f /* Always flush prefetch queue in any case */
987 sync /* Wait for all dcbst to complete on bus */
993 7: sync /* Wait for all icbi to complete on bus */
997 * We are done. Do not return, instead branch to second part of board
998 * initialization, now running from RAM.
1001 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1003 blr /* NEVER RETURNS! */
1008 * Relocation Function, r14 point to got2+0x8000
1010 * Adjust got2 pointers, no need to check for 0, this code
1011 * already puts a few entries in the table.
1013 li r0,__got2_entries@sectoff@l
1014 la r3,GOT(_GOT2_TABLE_)
1015 lwz r11,GOT(_GOT2_TABLE_)
1025 * Now adjust the fixups and the pointers to the fixups
1026 * in case we need to move ourselves again.
1028 2: li r0,__fixup_entries@sectoff@l
1029 lwz r3,GOT(_FIXUP_TABLE_)
1043 * Now clear BSS segment
1045 lwz r3,GOT(__bss_start)
1059 mr r3, r9 /* Init Data pointer */
1060 mr r4, r10 /* Destination Address */
1064 * Copy exception vector code to low memory
1067 * r7: source address, r8: end address, r9: target address
1072 lwz r8, GOT(_end_of_vectors)
1074 li r9, 0x100 /* reset vector always at 0x100 */
1077 bgelr /* return if r7>=r8 - just in case */
1079 mflr r4 /* save link register */
1089 * relocate `hdlr' and `int_return' entries
1091 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1093 li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET
1095 li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET
1097 li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET
1099 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1101 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1103 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1105 li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET
1107 li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET
1108 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1111 addi r7, r7, 0x100 /* next exception vector */
1118 mtlr r4 /* restore link register */
1122 * Function: relocate entries for one exception vector
1125 lwz r0, 0(r7) /* hdlr ... */
1126 add r0, r0, r3 /* ... += dest_addr */
1129 lwz r0, 4(r7) /* int_return ... */
1130 add r0, r0, r3 /* ... += dest_addr */
1135 #ifdef CFG_INIT_RAM_LOCK
1136 .globl unlock_ram_in_cache
1137 unlock_ram_in_cache:
1138 /* invalidate the INIT_RAM section */
1139 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1140 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1147 sync /* Wait for all icbi to complete on bus */