2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
32 #include <asm/fsl_law.h>
42 uint lcrr; /* local bus clock ratio register */
43 uint clkdiv; /* clock divider portion of lcrr */
44 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
45 volatile ccsr_gur_t *gur = &immap->im_gur;
47 puts("Freescale PowerPC\n");
58 case PVR_VER(PVR_86xx):
60 uint msscr0 = mfspr(MSSCR0);
61 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
62 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
63 puts("\n Core1Translation Enabled");
64 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
71 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
74 ver = SVR_SOC_VER(svr);
81 if (SVR_SUBVER(svr) == 1) {
94 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
96 get_sys_info(&sysinfo);
99 printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
100 printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
101 printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
103 #if defined(CONFIG_SYS_LBC_LCRR)
104 lcrr = CONFIG_SYS_LBC_LCRR;
107 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
108 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
113 clkdiv = lcrr & LCRR_CLKDIV;
114 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
116 printf("LBC:%4lu MHz\n",
117 sysinfo.freqSystemBus / 1000000 / clkdiv);
119 printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
123 if (get_l2cr() & 0x80000000)
133 soft_restart(unsigned long addr)
135 #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
138 * SRR0 has system reset vector, SRR1 has default MSR value
139 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
142 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
143 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
144 __asm__ __volatile__ ("mtspr 27, 4");
145 __asm__ __volatile__ ("rfi");
147 #else /* CONFIG_MPC8641HPCN */
149 out8(PIXIS_BASE + PIXIS_RST, 0);
151 #endif /* !CONFIG_MPC8641HPCN */
153 while (1) ; /* not reached */
158 * No generic way to do board reset. Simply call soft_reset.
161 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
163 #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
165 #ifdef CONFIG_SYS_RESET_ADDRESS
166 ulong addr = CONFIG_SYS_RESET_ADDRESS;
169 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
170 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
171 * address. Better pick an address known to be invalid on your
172 * system and assign it to CONFIG_SYS_RESET_ADDRESS.
174 ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
177 /* flush and disable I/D cache */
178 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
179 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
180 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
181 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
182 __asm__ __volatile__ ("sync");
183 __asm__ __volatile__ ("mtspr 1008, 4");
184 __asm__ __volatile__ ("isync");
185 __asm__ __volatile__ ("sync");
186 __asm__ __volatile__ ("mtspr 1008, 5");
187 __asm__ __volatile__ ("isync");
188 __asm__ __volatile__ ("sync");
192 #else /* CONFIG_MPC8641HPCN */
194 out8(PIXIS_BASE + PIXIS_RST, 0);
196 #endif /* !CONFIG_MPC8641HPCN */
198 while (1) ; /* not reached */
203 * Get timebase clock frequency
210 get_sys_info(&sys_info);
211 return (sys_info.freqSystemBus + 3L) / 4L;
215 #if defined(CONFIG_WATCHDOG)
219 #if defined(CONFIG_MPC8610)
221 * This actually feed the hard enabled watchdog.
223 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
224 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
225 volatile ccsr_gur_t *gur = &immap->im_gur;
226 u32 tmp = gur->pordevsr;
234 #endif /* CONFIG_WATCHDOG */
237 #if defined(CONFIG_DDR_ECC)
241 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
242 volatile ccsr_dma_t *dma = &immap->im_dma;
244 dma->satr0 = 0x00040000;
245 dma->datr0 = 0x00040000;
252 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
253 volatile ccsr_dma_t *dma = &immap->im_dma;
254 volatile uint status = dma->sr0;
256 /* While the channel is busy, spin */
257 while ((status & 4) == 4) {
262 printf("DMA Error: status = %x\n", status);
268 dma_xfer(void *dest, uint count, void *src)
270 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
271 volatile ccsr_dma_t *dma = &immap->im_dma;
273 dma->dar0 = (uint) dest;
274 dma->sar0 = (uint) src;
276 dma->mr0 = 0xf000004;
278 dma->mr0 = 0xf000005;
283 #endif /* CONFIG_DDR_ECC */
287 * Print out the state of various machine registers.
288 * Currently prints out LAWs, BR0/OR0, and BATs
290 void mpc86xx_reginfo(void)
292 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
293 ccsr_lbc_t *lbc = &immap->im_lbc;
298 printf ("Local Bus Controller Registers\n"
299 "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
300 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
301 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
302 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
303 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
304 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
305 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
306 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
311 * Initializes on-chip ethernet controllers.
312 * to override, implement board_eth_init()
314 int cpu_eth_init(bd_t *bis)
316 #if defined(CONFIG_TSEC_ENET)
317 tsec_standard_init(bis);