2 #include <asm/processor.h>
9 DECLARE_GLOBAL_DATA_PTR;
13 /* dummy function so common/cmd_mp.c will build
14 * should be implemented in the future, when cpu_release()
15 * is supported. Be aware there may be a similiar bug
16 * as exists on MPC85xx w/its PIC having a timing window
17 * associated to resetting the core */
21 int cpu_status(int nr)
23 /* dummy function so common/cmd_mp.c will build */
27 int cpu_release(int nr, int argc, char *argv[])
29 /* dummy function so common/cmd_mp.c will build
30 * should be implemented in the future */
34 u32 determine_mp_bootpg(void)
36 /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
37 if ((u64)gd->ram_size > 0xfffff000)
40 return (gd->ram_size - (1024 * 1024));
43 void cpu_mp_lmb_reserve(struct lmb *lmb)
45 u32 bootpg = determine_mp_bootpg();
47 /* tell u-boot we stole a page */
48 lmb_reserve(lmb, bootpg, 4096);
52 * Copy the code for other cpus to execute into an
53 * aligned location accessible via BPTR
57 extern ulong __secondary_start_page;
58 ulong fixup = (ulong)&__secondary_start_page;
59 u32 bootpg = determine_mp_bootpg();
62 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
63 /* We're not covered by the DDR mapping, set up BAT */
64 write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
66 bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
67 bootpg_va = CONFIG_SYS_SCRATCH_VA;
72 memcpy((void *)bootpg_va, (void *)fixup, 4096);
73 flush_cache(bootpg_va, 4096);
75 /* remove the temporary BAT mapping */
76 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
77 write_bat(DBAT7, 0, 0);
79 /* If the physical location of bootpg is not at fff00000, set BPTR */
80 if (bootpg != 0xfff00000)
81 out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |