2 * Support for indirect PCI bridges.
4 * Copyright (c) Freescale Semiconductor, Inc.
5 * 2006. All rights reserved.
7 * Jason Jin <Jason.jin@freescale.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 * arch/powerpc/platforms/86xx/mpc86xx_pcie.c
22 #include <asm/processor.h>
26 #define PCI_CFG_OUT out_be32
27 #define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
30 indirect_read_config_pcie(struct pci_controller *hose,
31 pci_dev_t dev, int offset,
34 int bus = PCI_BUS(dev);
35 char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ;
37 unsigned char *cfg_data;
42 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
44 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
47 * Note: the caller has already checked that offset is
48 * suitably aligned and that len is 1, 2 or 4.
50 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
51 cfg_data = hose->cfg_data;
53 temp = in_le32(cfg_data);
56 *val = (temp >> (((offset & 3))*8)) & 0xff;
59 *val = (temp >> (((offset & 3))*8)) & 0xffff;
70 indirect_write_config_pcie(struct pci_controller *hose,
76 int bus = PCI_BUS(dev);
77 char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ;
79 unsigned char *cfg_data;
84 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
86 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
90 * Note: the caller has already checked that offset is
91 * suitably aligned and that len is 1, 2 or 4.
93 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
94 cfg_data = hose->cfg_data;
98 temp = in_le32(cfg_data);
99 temp = (temp & ~(0xff << ((offset & 3) * 8))) |
100 (val << ((offset & 3) * 8));
102 out_le32(cfg_data, temp);
106 temp = in_le32(cfg_data);
107 temp = (temp & ~(0xffff << ((offset & 3) * 8)));
108 temp |= (val << ((offset & 3) * 8)) ;
110 out_le32(cfg_data, temp);
114 out_le32(cfg_data, val);
122 indirect_read_config_byte_pcie(struct pci_controller *hose,
128 indirect_read_config_pcie(hose,dev,offset,1,&val32);
134 indirect_read_config_word_pcie(struct pci_controller *hose,
140 indirect_read_config_pcie(hose,dev,offset,2,&val32);
146 indirect_read_config_dword_pcie(struct pci_controller *hose,
151 return indirect_read_config_pcie(hose,dev, offset,4,val);
155 indirect_write_config_byte_pcie(struct pci_controller *hose,
160 return indirect_write_config_pcie(hose,dev, offset,1,(u32)val);
164 indirect_write_config_word_pcie(struct pci_controller *hose,
169 return indirect_write_config_pcie(hose,dev, offset,2,(u32)val);
173 indirect_write_config_dword_pcie(struct pci_controller *hose,
178 return indirect_write_config_pcie(hose,dev, offset,4,val);
182 pcie_setup_indirect(struct pci_controller* hose,
187 indirect_read_config_byte_pcie,
188 indirect_read_config_word_pcie,
189 indirect_read_config_dword_pcie,
190 indirect_write_config_byte_pcie,
191 indirect_write_config_word_pcie,
192 indirect_write_config_dword_pcie);
194 hose->cfg_addr = (unsigned int *) cfg_addr;
195 hose->cfg_data = (unsigned char *) cfg_data;
198 #endif /* CONFIG_PCI */