2 * Copyright 2004 Freescale Semiconductor.
3 * Jeff Brown (jeffrey@freescale.com)
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * (C) Copyright 2000-2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 unsigned long get_board_sys_clk(ulong dummy);
33 unsigned long get_sysclk_from_px_regs(void);
36 void get_sys_info (sys_info_t *sysInfo)
38 volatile immap_t *immap = (immap_t *)CFG_IMMR;
39 volatile ccsr_gur_t *gur = &immap->im_gur;
40 uint plat_ratio, e600_ratio;
42 plat_ratio = (gur->porpllsr) & 0x0000003e;
47 sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
59 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
62 sysInfo->freqSystemBus = 0;
67 printf("assigned system bus freq = %d for plat ratio 0x%08lx\n",
68 sysInfo->freqSystemBus, plat_ratio);
71 e600_ratio = (gur->porpllsr) & 0x003f0000;
76 sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
79 sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2;
82 sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
85 sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2;
88 sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
91 sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2;
94 /* JB - Emulator workaround until real cop is plugged in */
95 /* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */
96 sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
100 printf("assigned processor freq = %d for e600 ratio 0x%08lx\n",
101 sysInfo->freqProcessor, e600_ratio);
107 * Measure CPU clock speed (core clock GCLK1, GCLK2)
108 * (Approx. GCLK frequency in Hz)
113 DECLARE_GLOBAL_DATA_PTR;
116 get_sys_info(&sys_info);
117 gd->cpu_clk = sys_info.freqProcessor;
118 gd->bus_clk = sys_info.freqSystemBus;
120 if (gd->cpu_clk != 0)
129 * Return system bus freq in Hz
131 ulong get_bus_freq(ulong dummy)
136 get_sys_info(&sys_info);
137 val = sys_info.freqSystemBus;
142 unsigned long get_sysclk_from_px_regs()
147 vclkh = in8(PIXIS_BASE + PIXIS_VCLKH);
148 vclkl = in8(PIXIS_BASE + PIXIS_VCLKL);
150 if ((vclkh == 0x84) && (vclkl == 0x07)) {
153 if ((vclkh == 0x3F) && (vclkl == 0x20)) {
156 if ((vclkh == 0x3F) && (vclkl == 0x2A)) {
159 if ((vclkh == 0x24) && (vclkl == 0x04)) {
162 if ((vclkh == 0x3F) && (vclkl == 0x4B)) {
165 if ((vclkh == 0x3F) && (vclkl == 0x5C)) {
168 if ((vclkh == 0xDF) && (vclkl == 0x3B)) {
171 if ((vclkh == 0xDF) && (vclkl == 0x4B)) {
181 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
184 unsigned long get_board_sys_clk(ulong dummy)
186 u8 i, go_bit, rd_clks;
189 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
192 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
196 * Only if both go bit and the SCLK bit in VCFGEN0 are set
197 * should we be using the AUX register. Remember, we also set the
198 * GO bit to boot from the alternate bank on the on-board flash
203 i = in8(PIXIS_BASE + PIXIS_AUX);
205 i = in8(PIXIS_BASE + PIXIS_SPD);
207 i = in8(PIXIS_BASE + PIXIS_SPD);