2 * Copyright 2004 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * (C) Copyright 2000-2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
36 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
39 unsigned long get_board_sys_clk(ulong dummy)
41 u8 i, go_bit, rd_clks;
44 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
47 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
51 * Only if both go bit and the SCLK bit in VCFGEN0 are set
52 * should we be using the AUX register. Remember, we also set the
53 * GO bit to boot from the alternate bank on the on-board flash
58 i = in8(PIXIS_BASE + PIXIS_AUX);
60 i = in8(PIXIS_BASE + PIXIS_SPD);
62 i = in8(PIXIS_BASE + PIXIS_SPD);
99 void get_sys_info (sys_info_t *sysInfo)
101 volatile immap_t *immap = (immap_t *)CFG_IMMR;
102 volatile ccsr_gur_t *gur = &immap->im_gur;
103 uint plat_ratio, e600_ratio;
105 plat_ratio = (gur->porpllsr) & 0x0000003e;
110 sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
122 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
125 sysInfo->freqSystemBus = 0;
129 e600_ratio = (gur->porpllsr) & 0x003f0000;
132 switch (e600_ratio) {
134 sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
137 sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2;
140 sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
143 sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2;
146 sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
149 sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2;
152 sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
159 * Measure CPU clock speed (core clock GCLK1, GCLK2)
160 * (Approx. GCLK frequency in Hz)
165 DECLARE_GLOBAL_DATA_PTR;
168 get_sys_info(&sys_info);
169 gd->cpu_clk = sys_info.freqProcessor;
170 gd->bus_clk = sys_info.freqSystemBus;
172 if (gd->cpu_clk != 0)
181 * Return system bus freq in Hz
184 ulong get_bus_freq(ulong dummy)
189 get_sys_info(&sys_info);
190 val = sys_info.freqSystemBus;