2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
35 #include <timestamp.h>
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
53 * Set up GOT: Global Offset Table
55 * Use r14 to access the GOT
58 GOT_ENTRY(_GOT2_TABLE_)
59 GOT_ENTRY(_FIXUP_TABLE_)
62 GOT_ENTRY(_start_of_vectors)
63 GOT_ENTRY(_end_of_vectors)
64 GOT_ENTRY(transfer_to_handler)
68 GOT_ENTRY(__bss_start)
72 * r3 - 1st arg to board_init(): IMMP pointer
73 * r4 - 2nd arg to board_init(): boot flag
76 .long 0x27051956 /* U-Boot Magic Number */
80 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
81 .ascii CONFIG_IDENT_STRING, "\0"
86 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
90 . = EXC_OFF_SYS_RESET + 0x10
94 li r21, BOOTFLAG_WARM /* Software reboot */
98 /* the boot code is located below the exception table */
100 .globl _start_of_vectors
104 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
106 /* Data Storage exception. */
107 STD_EXCEPTION(0x300, DataStorage, UnknownException)
109 /* Instruction Storage exception. */
110 STD_EXCEPTION(0x400, InstStorage, UnknownException)
112 /* External Interrupt exception. */
113 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
115 /* Alignment exception. */
118 EXCEPTION_PROLOG(SRR0, SRR1)
123 addi r3,r1,STACK_FRAME_OVERHEAD
125 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
126 lwz r6,GOT(transfer_to_handler)
130 .long AlignmentException - _start + EXC_OFF_SYS_RESET
131 .long int_return - _start + EXC_OFF_SYS_RESET
133 /* Program check exception */
136 EXCEPTION_PROLOG(SRR0, SRR1)
137 addi r3,r1,STACK_FRAME_OVERHEAD
139 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
140 lwz r6,GOT(transfer_to_handler)
144 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
145 .long int_return - _start + EXC_OFF_SYS_RESET
147 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
149 /* I guess we could implement decrementer, and may have
150 * to someday for timekeeping.
152 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
153 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
154 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
155 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
156 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
157 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
158 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
159 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
160 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
161 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
162 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
163 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
164 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
165 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
166 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
167 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
168 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
169 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
170 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
171 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
172 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
174 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
176 .globl _end_of_vectors
184 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
185 * address specified by the BPTR
188 #ifdef CONFIG_SYS_RAMBOOT
189 /* disable everything */
196 /* Invalidate BATs */
199 /* Invalidate all of TLB before MMU turn on */
204 /* init the L2 cache */
206 ori r3, r3, L2_INIT@l
208 /* invalidate the L2 cache */
209 bl l2cache_invalidate
214 * Calculate absolute address in FLASH and jump there
215 *------------------------------------------------------*/
216 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
217 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
218 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
223 /* let the C-code set up the rest */
225 /* Be careful to keep code relocatable ! */
226 /*------------------------------------------------------*/
227 /* perform low-level init */
229 /* enable extended addressing */
236 * Cache must be enabled here for stack-in-cache trick.
237 * This means we need to enable the BATS.
238 * Cache should be turned on after BATs, since by default
239 * everything is write-through.
242 /* enable address translation */
244 ori r5, r5, (MSR_IR | MSR_DR)
245 lis r3,addr_trans_enabled@h
246 ori r3, r3, addr_trans_enabled@l
252 /* enable and invalidate the data cache */
253 /* bl l1dcache_enable */
261 #ifdef CONFIG_SYS_INIT_RAM_LOCK
266 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
270 /* set up the stack pointer in our newly created
272 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
273 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
275 li r0, 0 /* Make room for stack frame header and */
276 stwu r0, -4(r1) /* clear final stack frame so that */
277 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
279 GET_GOT /* initialize GOT access */
281 /* run low-level CPU init code (from Flash) */
287 /* Load PX_AUX register address in r4 */
290 /* Load contents of PX_AUX in r3 bits 24 to 31*/
293 /* Mask and obtain the bit in r3 */
294 rlwinm. r3, r3, 0, 24, 24
295 /* If not zero, jump and continue with u-boot */
298 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
300 /* Set the MSB of the register value */
302 /* Write value in r3 back to PX_AUX */
305 /* Get the address to jump to in r3*/
306 lis r3, CONFIG_SYS_DIAG_ADDR@h
307 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
309 /* Load the LR with the branch address */
312 /* Branch to diagnostic */
318 /* bl l2cache_enable */
322 /* run 1st part of board init code (from Flash) */
328 .globl invalidate_bats
332 /* invalidate BATs */
359 * Set up bats needed early on - this is usually the BAT for the
360 * stack-in-cache, the Flash, and CCSR space
365 lis r4, CONFIG_SYS_IBAT3L@h
366 ori r4, r4, CONFIG_SYS_IBAT3L@l
367 lis r3, CONFIG_SYS_IBAT3U@h
368 ori r3, r3, CONFIG_SYS_IBAT3U@l
374 lis r4, CONFIG_SYS_DBAT3L@h
375 ori r4, r4, CONFIG_SYS_DBAT3L@l
376 lis r3, CONFIG_SYS_DBAT3U@h
377 ori r3, r3, CONFIG_SYS_DBAT3U@l
383 lis r4, CONFIG_SYS_IBAT5L@h
384 ori r4, r4, CONFIG_SYS_IBAT5L@l
385 lis r3, CONFIG_SYS_IBAT5U@h
386 ori r3, r3, CONFIG_SYS_IBAT5U@l
392 lis r4, CONFIG_SYS_DBAT5L@h
393 ori r4, r4, CONFIG_SYS_DBAT5L@l
394 lis r3, CONFIG_SYS_DBAT5U@h
395 ori r3, r3, CONFIG_SYS_DBAT5U@l
401 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
402 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
403 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
404 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
410 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
411 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
412 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
413 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
418 #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
420 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
421 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
422 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
423 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
429 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
430 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
431 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
432 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
452 .globl disable_addr_trans
454 /* disable address translation */
457 andi. r0, r3, (MSR_IR | MSR_DR)
465 * This code finishes saving the registers to the exception frame
466 * and jumps to the appropriate handler for the exception.
467 * Register r21 is pointer into trap frame, r1 has new stack pointer.
469 .globl transfer_to_handler
480 andi. r24,r23,0x3f00 /* get vector offset */
484 mtspr SPRG2,r22 /* r1 is now kernel sp */
485 lwz r24,0(r23) /* virtual address of handler */
486 lwz r23,4(r23) /* where to go when done */
491 rfi /* jump to handler, enable MMU */
494 mfmsr r28 /* Disable interrupts */
498 SYNC /* Some chip revs need this... */
513 lwz r2,_NIP(r1) /* Restore environment */
540 * Description: Input 8 bits
549 * Description: Output 8 bits
558 * Description: Output 16 bits
567 * Description: Byte reverse and output 16 bits
576 * Description: Output 32 bits
585 * Description: Byte reverse and output 32 bits
594 * Description: Input 16 bits
603 * Description: Input 16 bits and byte reverse
612 * Description: Input 32 bits
621 * Description: Input 32 bits and byte reverse
629 * void relocate_code (addr_sp, gd, addr_moni)
631 * This "function" does not return, instead it continues in RAM
632 * after relocating the monitor code.
636 * r5 = length in bytes
642 mr r1, r3 /* Set new stack pointer */
643 mr r9, r4 /* Save copy of Global Data pointer */
644 mr r10, r5 /* Save copy of Destination Address */
646 mr r3, r5 /* Destination Address */
647 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
648 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
649 lwz r5, GOT(__init_end)
651 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
656 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
662 /* First our own GOT */
664 /* then the one used by the C code */
673 beq cr1,4f /* In place copy is not necessary */
674 beq 7f /* Protect against 0 count */
692 * Now flush the cache: note that we must start from a cache aligned
693 * address. Otherwise we might miss one cache line.
697 beq 7f /* Always flush prefetch queue in any case */
705 sync /* Wait for all dcbst to complete on bus */
711 7: sync /* Wait for all icbi to complete on bus */
715 * We are done. Do not return, instead branch to second part of board
716 * initialization, now running from RAM.
718 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
724 * Relocation Function, r14 point to got2+0x8000
726 * Adjust got2 pointers, no need to check for 0, this code
727 * already puts a few entries in the table.
729 li r0,__got2_entries@sectoff@l
730 la r3,GOT(_GOT2_TABLE_)
731 lwz r11,GOT(_GOT2_TABLE_)
743 * Now adjust the fixups and the pointers to the fixups
744 * in case we need to move ourselves again.
746 li r0,__fixup_entries@sectoff@l
747 lwz r3,GOT(_FIXUP_TABLE_)
761 * Now clear BSS segment
763 lwz r3,GOT(__bss_start)
776 mr r3, r9 /* Init Date pointer */
777 mr r4, r10 /* Destination Address */
780 /* not reached - end relocate_code */
781 /*-----------------------------------------------------------------------*/
784 * Copy exception vector code to low memory
787 * r7: source address, r8: end address, r9: target address
792 lwz r8, GOT(_end_of_vectors)
794 li r9, 0x100 /* reset vector always at 0x100 */
797 bgelr /* return if r7>=r8 - just in case */
799 mflr r4 /* save link register */
809 * relocate `hdlr' and `int_return' entries
811 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
812 li r8, Alignment - _start + EXC_OFF_SYS_RESET
815 addi r7, r7, 0x100 /* next exception vector */
819 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
822 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
825 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
826 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
829 addi r7, r7, 0x100 /* next exception vector */
833 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
834 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
837 addi r7, r7, 0x100 /* next exception vector */
841 /* enable execptions from RAM vectors */
845 ori r7,r7,MSR_ME /* Enable Machine Check */
848 mtlr r4 /* restore link register */
852 * Function: relocate entries for one exception vector
855 lwz r0, 0(r7) /* hdlr ... */
856 add r0, r0, r3 /* ... += dest_addr */
859 lwz r0, 4(r7) /* int_return ... */
860 add r0, r0, r3 /* ... += dest_addr */
868 .globl enable_ext_addr
871 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
872 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
878 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
881 /* Special sequence needed to update CCSRBAR itself */
882 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
883 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
885 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
886 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
888 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
890 stw r5, 0(r4) /* Store physical value of CCSR */
894 ori r5,r5,TEXT_BASE@l
898 /* Use VA of CCSR to do read */
899 lis r3, CONFIG_SYS_CCSRBAR@h
900 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
906 #ifdef CONFIG_SYS_INIT_RAM_LOCK
908 /* Allocate Initial RAM in data cache.
910 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
911 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
912 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
913 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
920 /* Lock the data cache */
929 /* Lock the first way of the data cache */
932 #if defined(CONFIG_ALTIVEC)
942 .globl unlock_ram_in_cache
944 /* invalidate the INIT_RAM section */
945 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
946 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
947 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
948 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
953 sync /* Wait for all icbi to complete on bus */
956 /* Unlock the data cache and invalidate it */
968 /* Unlock the first way of the data cache */
972 #ifdef CONFIG_ALTIVEC