3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
34 #ifdef CFG_DISCOVER_PHY
36 static void mii_discover_phy(void);
39 /* Ethernet Transmit and Receive Buffers */
40 #define DBUF_LENGTH 1520
46 #define PKT_MAXBUF_SIZE 1518
47 #define PKT_MINBUF_SIZE 64
48 #define PKT_MAXBLR_SIZE 1520
51 static char txbuf[DBUF_LENGTH];
53 static uint rxIdx; /* index of the current RX buffer */
54 static uint txIdx; /* index of the current TX buffer */
57 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
58 * immr->udata_bd address on Dual-Port RAM
59 * Provide for Double Buffering
62 typedef volatile struct CommonBufferDescriptor {
63 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
64 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
67 static RTXBD *rtx = NULL;
69 static int fec_send(struct eth_device* dev, volatile void *packet, int length);
70 static int fec_recv(struct eth_device* dev);
71 static int fec_init(struct eth_device* dev, bd_t * bd);
72 static void fec_halt(struct eth_device* dev);
74 int fec_initialize(bd_t *bis)
76 struct eth_device* dev;
78 dev = (struct eth_device*) malloc(sizeof *dev);
79 memset(dev, 0, sizeof *dev);
81 sprintf(dev->name, "FEC ETHERNET");
94 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
97 volatile immap_t *immr = (immap_t *) CFG_IMMR;
98 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
104 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
109 printf("TX not ready\n");
112 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
113 rtx->txbd[txIdx].cbd_datlen = length;
114 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
117 /* Activate transmit Buffer Descriptor polling */
118 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
121 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
122 #if defined(CONFIG_ICU862)
130 printf("TX timeout\n");
133 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
134 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
135 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
137 /* return only status bits */;
138 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
140 txIdx = (txIdx + 1) % TX_BUF_CNT;
145 static int fec_recv(struct eth_device* dev)
148 volatile immap_t *immr = (immap_t *) CFG_IMMR;
149 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
152 /* section 16.9.23.2 */
153 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
155 break; /* nothing received - leave for() loop */
158 length = rtx->rxbd[rxIdx].cbd_datlen;
160 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
162 printf("%s[%d] err: %x\n",
163 __FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
166 /* Pass the packet up to the protocol layers. */
167 NetReceive(NetRxPackets[rxIdx], length - 4);
170 /* Give the buffer back to the FEC. */
171 rtx->rxbd[rxIdx].cbd_datlen = 0;
173 /* wrap around buffer index when necessary */
174 if ((rxIdx + 1) >= PKTBUFSRX) {
175 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
178 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
184 /* Try to fill Buffer Descriptors */
185 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
191 /**************************************************************
193 * FEC Ethernet Initialization Routine
195 *************************************************************/
197 #define FEC_ECNTRL_PINMUX 0x00000004
198 #define FEC_ECNTRL_ETHER_EN 0x00000002
199 #define FEC_ECNTRL_RESET 0x00000001
201 #define FEC_RCNTRL_BC_REJ 0x00000010
202 #define FEC_RCNTRL_PROM 0x00000008
203 #define FEC_RCNTRL_MII_MODE 0x00000004
204 #define FEC_RCNTRL_DRT 0x00000002
205 #define FEC_RCNTRL_LOOP 0x00000001
207 #define FEC_TCNTRL_FDEN 0x00000004
208 #define FEC_TCNTRL_HBC 0x00000002
209 #define FEC_TCNTRL_GTS 0x00000001
211 #define FEC_RESET_DELAY 50
213 static int fec_init(struct eth_device* dev, bd_t * bd)
217 volatile immap_t *immr = (immap_t *) CFG_IMMR;
218 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
220 #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
221 #if defined(CONFIG_DUET_ADS)
222 *(vu_char *)BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
224 /* configure FADS for fast (FEC) ethernet, half-duplex */
225 /* The LXT970 needs about 50ms to recover from reset, so
226 * wait for it by discovering the PHY before leaving eth_init().
229 volatile uint *bcsr4 = (volatile uint *) BCSR4;
230 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
231 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST);
233 /* reset the LXT970 PHY */
234 *bcsr4 &= ~BCSR4_FETHRST;
236 *bcsr4 |= BCSR4_FETHRST;
239 #endif /* CONFIG_DUET_ADS */
240 #endif /* CONFIG_FADS */
242 * A delay is required between a reset of the FEC block and
243 * initialization of other FEC registers because the reset takes
244 * some time to complete. If you don't delay, subsequent writes
245 * to FEC registers might get killed by the reset routine which is
248 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
250 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
254 if (i == FEC_RESET_DELAY) {
255 printf ("FEC_RESET_DELAY timeout\n");
259 /* We use strictly polling mode only
263 /* Clear any pending interrupt
265 fecp->fec_ievent = 0xffc0;
267 /* No need to set the IVEC register */
269 /* Set station address
271 #define ea eth_get_dev()->enetaddr
272 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
273 (ea[2] << 8) | (ea[3] ) ;
274 fecp->fec_addr_high = (ea[4] << 8) | (ea[5] ) ;
277 /* Clear multicast address hash table
279 fecp->fec_hash_table_high = 0;
280 fecp->fec_hash_table_low = 0;
282 /* Set maximum receive buffer size.
284 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
286 /* Set maximum frame length
288 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
291 * Setup Buffers and Buffer Desriptors
297 #ifdef CFG_ALLOC_DPRAM
298 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + dpram_alloc_align(sizeof(RTXBD),8));
300 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
304 * Setup Receiver Buffer Descriptors (13.14.24.18)
308 for (i = 0; i < PKTBUFSRX; i++) {
309 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
310 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
311 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
313 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
316 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
320 for (i = 0; i < TX_BUF_CNT; i++) {
321 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
322 rtx->txbd[i].cbd_datlen = 0; /* Reset */
323 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
325 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
327 /* Set receive and transmit descriptor base
329 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
330 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
334 #if 0 /* Full duplex mode */
335 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
336 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
337 #else /* Half duplex mode */
338 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
339 fecp->fec_x_cntrl = 0;
342 /* Enable big endian and don't care about SDMA FC.
344 fecp->fec_fun_code = 0x78000000;
346 /* Set MII speed to 2.5 MHz or slightly below.
347 * According to the MPC860T (Rev. D) Fast ethernet controller user
349 * the MII management interface clock must be less than or equal
351 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
352 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
354 fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
356 #if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
357 immr->im_ioport.iop_papar |= 0xf830;
358 immr->im_ioport.iop_padir |= 0x0830;
359 immr->im_ioport.iop_padir &= ~0xf000;
360 immr->im_cpm.cp_pbpar |= 0x00001001;
361 immr->im_cpm.cp_pbdir &= ~0x00001001;
362 immr->im_ioport.iop_pcpar |= 0x000c;
363 immr->im_ioport.iop_pcdir &= ~0x000c;
364 immr->im_ioport.iop_pdpar |= 0x0080;
365 immr->im_ioport.iop_pddir &= ~0x0080;
366 immr->im_cpm.cp_pepar |= 0x00000003;
367 immr->im_cpm.cp_pedir |= 0x00000003;
368 immr->im_cpm.cp_peso &= ~0x00000003;
369 #elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
370 /* Configure all of port D for MII.
372 immr->im_ioport.iop_pdpar = 0x1fff;
374 /* Bits moved from Rev. D onward */
375 if ((get_immr (0) & 0xffff) < 0x0501) {
376 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
378 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
381 /* Configure port A for MII.
384 #if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
386 /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
387 * of CPU, so for this board we need to configure Utopia and
388 * enable PD8 to MII-MDC function */
389 immr->im_ioport.iop_pdpar |= 0x4080;
392 /* Has Utopia been configured? */
393 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
395 * YES - Use MUXED mode for UTOPIA bus.
396 * This frees Port A for use by MII (see 862UM table 41-6).
398 immr->im_ioport.utmode &= ~0x80;
401 * NO - set SPLIT mode for UTOPIA bus.
403 * This doesn't really effect UTOPIA (which isn't
404 * enabled anyway) but just tells the 862
405 * to use port A for MII (see 862UM table 41-6).
407 immr->im_ioport.utmode |= 0x80;
409 #endif /* !defined(CONFIG_ICU862) */
414 /* Now enable the transmit and receive processing
416 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
418 #ifdef CFG_DISCOVER_PHY
419 /* wait for the PHY to wake up after reset
424 /* And last, try to fill Rx Buffer Descriptors */
425 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
431 static void fec_halt(struct eth_device* dev)
434 volatile immap_t *immr = (immap_t *)CFG_IMMR;
435 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
442 volatile immap_t *immr = (immap_t *)CFG_IMMR;
443 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
447 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
449 static int phyaddr = -1; /* didn't find a PHY yet */
452 /* Make MII read/write commands for the FEC.
455 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
458 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
459 (REG & 0x1f) << 18) | \
462 /* Interrupt events/masks.
464 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
465 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
466 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
467 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
468 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
469 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
470 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
471 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
472 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
473 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
475 /* PHY identification
477 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
478 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
479 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
480 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
481 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
482 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
483 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
484 #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
486 /* send command to phy using mii, wait for result */
488 mii_send(uint mii_cmd)
493 ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
495 ep->fec_mii_data = mii_cmd; /* command to phy */
497 /* wait for mii complete */
498 while (!(ep->fec_ievent & FEC_ENET_MII))
499 ; /* spin until done */
500 mii_reply = ep->fec_mii_data; /* result from phy */
501 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
503 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
504 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
506 return (mii_reply & 0xffff); /* data read from phy */
508 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
510 #if defined(CFG_DISCOVER_PHY)
512 mii_discover_phy(void)
514 #define MAX_PHY_PASSES 11
518 phyaddr = -1; /* didn't find a PHY yet */
519 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
521 /* PHY may need more time to recover from reset.
522 * The LXT970 needs 50ms typical, no maximum is
523 * specified, so wait 10ms before try again.
524 * With 11 passes this gives it 100ms to wake up.
526 udelay(10000); /* wait 10ms */
528 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
529 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
531 printf("PHY type 0x%x pass %d type ", phytype, pass);
533 if (phytype != 0xffff) {
536 phytype |= mii_send(mk_mii_read(phyno,
540 printf("PHY @ 0x%x pass %d type ",phyno,pass);
541 switch (phytype & 0xfffffff0) {
554 case PHY_ID_AMD79C784:
555 printf("AMD79C784\n");
557 case PHY_ID_LSI80225B:
558 printf("LSI L80225/B\n");
561 printf("Davicom DM9161\n");
564 printf("0x%08x\n", phytype);
572 printf("No PHY device found.\n");
575 #endif /* CFG_DISCOVER_PHY */
577 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
579 static int mii_init_done = 0;
581 /****************************************************************************
582 * mii_init -- Initialize the MII for MII command without ethernet
583 * This function is a subset of eth_init
584 ****************************************************************************
588 DECLARE_GLOBAL_DATA_PTR;
591 volatile immap_t *immr = (immap_t *) CFG_IMMR;
592 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
595 if (mii_init_done != 0) {
600 * A delay is required between a reset of the FEC block and
601 * initialization of other FEC registers because the reset takes
602 * some time to complete. If you don't delay, subsequent writes
603 * to FEC registers might get killed by the reset routine which is
607 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
609 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
613 if (i == FEC_RESET_DELAY) {
614 printf ("FEC_RESET_DELAY timeout\n");
618 /* We use strictly polling mode only
622 /* Clear any pending interrupt
624 fecp->fec_ievent = 0xffc0;
626 /* Set MII speed to 2.5 MHz or slightly below.
627 * According to the MPC860T (Rev. D) Fast ethernet controller user
629 * the MII management interface clock must be less than or equal
631 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
632 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
634 fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
636 #if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
637 immr->im_ioport.iop_papar |= 0xf830;
638 immr->im_ioport.iop_padir |= 0x0830;
639 immr->im_ioport.iop_padir &= ~0xf000;
640 immr->im_cpm.cp_pbpar |= 0x00001001;
641 immr->im_cpm.cp_pbdir &= ~0x00001001;
642 immr->im_ioport.iop_pcpar |= 0x000c;
643 immr->im_ioport.iop_pcdir &= ~0x000c;
644 immr->im_ioport.iop_pdpar |= 0x0080;
645 immr->im_ioport.iop_pddir &= ~0x0080;
646 immr->im_cpm.cp_pepar |= 0x00000003;
647 immr->im_cpm.cp_pedir |= 0x00000003;
648 immr->im_cpm.cp_peso &= ~0x00000003;
649 #elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
650 /* Configure all of port D for MII.
652 immr->im_ioport.iop_pdpar = 0x1fff;
654 /* Bits moved from Rev. D onward */
655 if ((get_immr (0) & 0xffff) < 0x0501) {
656 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
658 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
661 /* Configure port A for MII.
664 #if defined(CONFIG_ICU862)
666 /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
667 * of CPU, so for this board we need to configure Utopia and
668 * enable PD8 to MII-MDC function */
669 immr->im_ioport.iop_pdpar |= 0x4080;
672 /* Has Utopia been configured? */
673 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
675 * YES - Use MUXED mode for UTOPIA bus.
676 * This frees Port A for use by MII (see 862UM table 41-6).
678 immr->im_ioport.utmode &= ~0x80;
681 * NO - set SPLIT mode for UTOPIA bus.
683 * This doesn't really effect UTOPIA (which isn't
684 * enabled anyway) but just tells the 862
685 * to use port A for MII (see 862UM table 41-6).
687 immr->im_ioport.utmode |= 0x80;
689 #endif /* !defined(CONFIG_ICU862) */
690 /* Now enable the transmit and receive processing
692 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
696 /*****************************************************************************
697 * Read and write a MII PHY register, routines used by MII Utilities
699 * FIXME: These routines are expected to return 0 on success, but mii_send
700 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
701 * no PHY connected...
702 * For now always return 0.
703 * FIXME: These routines only work after calling eth_init() at least once!
704 * Otherwise they hang in mii_send() !!! Sorry!
705 *****************************************************************************/
707 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
709 short rdreg; /* register working value */
712 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
714 rdreg = mii_send(mk_mii_read(addr, reg));
719 printf ("0x%04x\n", *value);
725 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
727 short rdreg; /* register working value */
730 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
733 rdreg = mii_send(mk_mii_write(addr, reg, value));
736 printf ("0x%04x\n", value);
741 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
743 #endif /* CFG_CMD_NET, FEC_ENET */