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1 /*
2  * (C) Copyright 2000
3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4  *
5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6  * Marius Groeger <mgroeger@sysgo.de>
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  *
26  * Back ported to the 8xx platform (from the 8260 platform) by
27  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
28  */
29
30 #include <common.h>
31
32 #ifdef CONFIG_HARD_I2C
33
34 #include <commproc.h>
35 #include <i2c.h>
36 #ifdef CONFIG_LWMON
37 #include <watchdog.h>
38 #endif
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 /* define to enable debug messages */
43 #undef  DEBUG_I2C
44
45 /*-----------------------------------------------------------------------
46  * Set default values
47  */
48 #ifndef CFG_I2C_SPEED
49 #define CFG_I2C_SPEED   50000
50 #endif
51
52 #ifndef CFG_I2C_SLAVE
53 #define CFG_I2C_SLAVE   0xFE
54 #endif
55 /*-----------------------------------------------------------------------
56  */
57
58 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
59 #define TOUT_LOOP 1000000
60
61 #define NUM_RX_BDS 4
62 #define NUM_TX_BDS 4
63 #define MAX_TX_SPACE 256
64 #define I2C_RXTX_LEN 128        /* maximum tx/rx buffer length */
65
66 typedef struct I2C_BD
67 {
68   unsigned short status;
69   unsigned short length;
70   unsigned char *addr;
71 } I2C_BD;
72 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
73
74 #define BD_I2C_TX_CL    0x0001  /* collision error */
75 #define BD_I2C_TX_UN    0x0002  /* underflow error */
76 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
77 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
78
79 #define BD_I2C_RX_ERR   BD_SC_OV
80
81 typedef void (*i2c_ecb_t)(int, int);    /* error callback function */
82
83 /* This structure keeps track of the bd and buffer space usage. */
84 typedef struct i2c_state {
85         int             rx_idx;         /* index   to next free Rx BD */
86         int             tx_idx;         /* index   to next free Tx BD */
87         void            *rxbd;          /* pointer to next free Rx BD */
88         void            *txbd;          /* pointer to next free Tx BD */
89         int             tx_space;       /* number  of Tx bytes left   */
90         unsigned char   *tx_buf;        /* pointer to free Tx area    */
91         i2c_ecb_t       err_cb;         /* error callback function    */
92 } i2c_state_t;
93
94
95 /* flags for i2c_send() and i2c_receive() */
96 #define I2CF_ENABLE_SECONDARY   0x01    /* secondary_address is valid           */
97 #define I2CF_START_COND         0x02    /* tx: generate start condition         */
98 #define I2CF_STOP_COND          0x04    /* tx: generate stop  condition         */
99
100 /* return codes */
101 #define I2CERR_NO_BUFFERS       0x01    /* no more BDs or buffer space          */
102 #define I2CERR_MSG_TOO_LONG     0x02    /* tried to send/receive to much data   */
103 #define I2CERR_TIMEOUT          0x03    /* timeout in i2c_doio()                */
104 #define I2CERR_QUEUE_EMPTY      0x04    /* i2c_doio called without send/receive */
105
106 /* error callback flags */
107 #define I2CECB_RX_ERR           0x10    /* this is a receive error              */
108 #define     I2CECB_RX_ERR_OV    0x02    /* receive overrun error                */
109 #define     I2CECB_RX_MASK      0x0f    /* mask for error bits                  */
110 #define I2CECB_TX_ERR           0x20    /* this is a transmit error             */
111 #define     I2CECB_TX_CL        0x01    /* transmit collision error             */
112 #define     I2CECB_TX_UN        0x02    /* transmit underflow error             */
113 #define     I2CECB_TX_NAK       0x04    /* transmit no ack error                */
114 #define     I2CECB_TX_MASK      0x0f    /* mask for error bits                  */
115 #define I2CECB_TIMEOUT          0x40    /* this is a timeout error              */
116
117 #ifdef DEBUG_I2C
118 #define PRINTD(x) printf x
119 #else
120 #define PRINTD(x)
121 #endif
122
123 /*
124  * Returns the best value of I2BRG to meet desired clock speed of I2C with
125  * input parameters (clock speed, filter, and predivider value).
126  * It returns computer speed value and the difference between it and desired
127  * speed.
128  */
129 static inline int
130 i2c_roundrate(int hz, int speed, int filter, int modval,
131                 int *brgval, int *totspeed)
132 {
133     int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
134
135     PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
136         hz, speed, filter, modval));
137
138     div = moddiv * speed;
139     brgdiv = (hz + div - 1) / div;
140
141     PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
142
143     *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
144
145     if ((*brgval < 0) || (*brgval > 255)) {
146           PRINTD(("\t\trejected brgval=%d\n", *brgval));
147           return -1;
148     }
149
150     brgdiv = 2 * (*brgval + 3 + (2 * filter));
151     div = moddiv * brgdiv ;
152     *totspeed = hz / div;
153
154     PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
155
156     return  0;
157 }
158
159 /*
160  * Sets the I2C clock predivider and divider to meet required clock speed.
161  */
162 static int
163 i2c_setrate (int hz, int speed)
164 {
165         immap_t         *immap = (immap_t *) CFG_IMMR;
166         volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
167         int             brgval,
168                         modval,         /* 0-3 */
169                         bestspeed_diff = speed,
170                         bestspeed_brgval = 0,
171                         bestspeed_modval = 0,
172                         bestspeed_filter = 0,
173                         totspeed,
174                         filter = 0;     /* Use this fixed value */
175
176         for (modval = 0; modval < 4; modval++) {
177                 if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) {
178                         int diff = speed - totspeed;
179
180                         if ((diff >= 0) && (diff < bestspeed_diff)) {
181                                 bestspeed_diff = diff;
182                                 bestspeed_modval = modval;
183                                 bestspeed_brgval = brgval;
184                                 bestspeed_filter = filter;
185                         }
186                 }
187         }
188
189         PRINTD (("[I2C] Best is:\n"));
190         PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
191                 hz,
192                 speed,
193                 bestspeed_filter,
194                 bestspeed_modval,
195                 bestspeed_brgval,
196                 bestspeed_diff));
197
198         i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
199         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
200
201         PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
202                          i2c->i2c_i2brg));
203
204         return 1;
205 }
206
207 void
208 i2c_init(int speed, int slaveaddr)
209 {
210         volatile immap_t *immap = (immap_t *)CFG_IMMR ;
211         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
212         volatile i2c8xx_t *i2c  = (i2c8xx_t *)&immap->im_i2c;
213         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
214         ulong rbase, tbase;
215         volatile I2C_BD *rxbd, *txbd;
216         uint dpaddr;
217
218 #ifdef CFG_I2C_INIT_BOARD
219         /* call board specific i2c bus reset routine before accessing the   */
220         /* environment, which might be in a chip on that bus. For details   */
221         /* about this problem see doc/I2C_Edge_Conditions.                  */
222         i2c_init_board();
223 #endif
224
225 #ifdef CFG_I2C_UCODE_PATCH
226         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
227 #else
228         /* Disable relocation */
229         iip->iic_rpbase = 0;
230 #endif
231
232 #ifdef CFG_ALLOC_DPRAM
233         dpaddr = iip->iic_rbase;
234         if (dpaddr == 0) {
235             /* need to allocate dual port ram */
236             dpaddr = dpram_alloc_align(
237                 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
238                 MAX_TX_SPACE, 8);
239         }
240 #else
241         dpaddr = CPM_I2C_BASE;
242 #endif
243
244         /*
245          * initialise data in dual port ram:
246          *
247          * dpaddr->rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
248          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
249          *                  tx buffer     (MAX_TX_SPACE bytes)
250          */
251
252         rbase = dpaddr;
253         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
254
255         /* Initialize Port B I2C pins. */
256         cp->cp_pbpar |= 0x00000030;
257         cp->cp_pbdir |= 0x00000030;
258         cp->cp_pbodr |= 0x00000030;
259
260         /* Disable interrupts */
261         i2c->i2c_i2mod = 0x00;
262         i2c->i2c_i2cmr = 0x00;
263         i2c->i2c_i2cer = 0xff;
264         i2c->i2c_i2add = slaveaddr;
265
266         /*
267          * Set the I2C BRG Clock division factor from desired i2c rate
268          * and current CPU rate (we assume sccr dfbgr field is 0;
269          * divide BRGCLK by 1)
270          */
271         PRINTD(("[I2C] Setting rate...\n"));
272         i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ;
273
274         /* Set I2C controller in master mode */
275         i2c->i2c_i2com = 0x01;
276
277         /* Set SDMA bus arbitration level to 5 (SDCR) */
278         immap->im_siu_conf.sc_sdcr = 0x0001 ;
279
280         /* Initialize Tx/Rx parameters */
281         iip->iic_rbase = rbase;
282         iip->iic_tbase = tbase;
283         rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
284         txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
285
286         PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
287         PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
288         PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
289         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
290
291         /* Set big endian byte order */
292         iip->iic_tfcr = 0x10;
293         iip->iic_rfcr = 0x10;
294
295         /* Set maximum receive size. */
296         iip->iic_mrblr = I2C_RXTX_LEN;
297
298 #ifdef CFG_I2C_UCODE_PATCH
299         /*
300          *  Initialize required parameters if using microcode patch.
301          */
302         iip->iic_rbptr  = iip->iic_rbase;
303         iip->iic_tbptr  = iip->iic_tbase;
304         iip->iic_rstate = 0;
305         iip->iic_tstate = 0;
306 #else
307         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
308         do {
309                 __asm__ __volatile__ ("eieio");
310         } while (cp->cp_cpcr & CPM_CR_FLG);
311 #endif
312
313         /* Clear events and interrupts */
314         i2c->i2c_i2cer = 0xff;
315         i2c->i2c_i2cmr = 0x00;
316 }
317
318 static void
319 i2c_newio(i2c_state_t *state)
320 {
321         volatile immap_t *immap = (immap_t *)CFG_IMMR ;
322         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
323         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
324
325         PRINTD(("[I2C] i2c_newio\n"));
326
327 #ifdef CFG_I2C_UCODE_PATCH
328         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
329 #endif
330         state->rx_idx = 0;
331         state->tx_idx = 0;
332         state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase];
333         state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase];
334         state->tx_space = MAX_TX_SPACE;
335         state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
336         state->err_cb = NULL;
337
338         PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
339         PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
340         PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
341
342         /* clear the buffer memory */
343         memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
344 }
345
346 static int
347 i2c_send(i2c_state_t *state,
348          unsigned char address,
349          unsigned char secondary_address,
350          unsigned int flags,
351          unsigned short size,
352          unsigned char *dataout)
353 {
354         volatile I2C_BD *txbd;
355         int i,j;
356
357         PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
358                         address, secondary_address, flags, size));
359
360         /* trying to send message larger than BD */
361         if (size > I2C_RXTX_LEN)
362           return I2CERR_MSG_TOO_LONG;
363
364         /* no more free bds */
365         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
366           return I2CERR_NO_BUFFERS;
367
368         txbd = (I2C_BD *)state->txbd;
369         txbd->addr = state->tx_buf;
370
371         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
372
373         if (flags & I2CF_START_COND) {
374                 PRINTD(("[I2C] Formatting addresses...\n"));
375                 if (flags & I2CF_ENABLE_SECONDARY) {
376                         txbd->length = size + 2;  /* Length of msg + dest addr */
377                         txbd->addr[0] = address << 1;
378                         txbd->addr[1] = secondary_address;
379                         i = 2;
380                 } else {
381                         txbd->length = size + 1;  /* Length of msg + dest addr */
382                         txbd->addr[0] = address << 1;  /* Write dest addr to BD */
383                         i = 1;
384                 }
385         } else {
386                 txbd->length = size;  /* Length of message */
387                 i = 0;
388         }
389
390         /* set up txbd */
391         txbd->status = BD_SC_READY;
392         if (flags & I2CF_START_COND)
393           txbd->status |= BD_I2C_TX_START;
394         if (flags & I2CF_STOP_COND)
395           txbd->status |= BD_SC_LAST | BD_SC_WRAP;
396
397         /* Copy data to send into buffer */
398         PRINTD(("[I2C] copy data...\n"));
399         for(j = 0; j < size; i++, j++)
400           txbd->addr[i] = dataout[j];
401
402         PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
403                    txbd->length,
404                    txbd->status,
405                    txbd->addr[0],
406                    txbd->addr[1]));
407
408         /* advance state */
409         state->tx_buf += txbd->length;
410         state->tx_space -= txbd->length;
411         state->tx_idx++;
412         state->txbd = (void*)(txbd + 1);
413
414         return 0;
415 }
416
417 static int
418 i2c_receive(i2c_state_t *state,
419             unsigned char address,
420             unsigned char secondary_address,
421             unsigned int flags,
422             unsigned short size_to_expect,
423             unsigned char *datain)
424 {
425         volatile I2C_BD *rxbd, *txbd;
426
427         PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
428
429         /* Expected to receive too much */
430         if (size_to_expect > I2C_RXTX_LEN)
431           return I2CERR_MSG_TOO_LONG;
432
433         /* no more free bds */
434         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
435                  || state->tx_space < 2)
436           return I2CERR_NO_BUFFERS;
437
438         rxbd = (I2C_BD *)state->rxbd;
439         txbd = (I2C_BD *)state->txbd;
440
441         PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
442         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
443
444         txbd->addr = state->tx_buf;
445
446         /* set up TXBD for destination address */
447         if (flags & I2CF_ENABLE_SECONDARY) {
448                 txbd->length = 2;
449                 txbd->addr[0] = address << 1;   /* Write data */
450                 txbd->addr[1] = secondary_address;  /* Internal address */
451                 txbd->status = BD_SC_READY;
452         } else {
453                 txbd->length = 1 + size_to_expect;
454                 txbd->addr[0] = (address << 1) | 0x01;
455                 txbd->status = BD_SC_READY;
456                 memset(&txbd->addr[1], 0, txbd->length);
457         }
458
459         /* set up rxbd for reception */
460         rxbd->status = BD_SC_EMPTY;
461         rxbd->length = size_to_expect;
462         rxbd->addr = datain;
463
464         txbd->status |= BD_I2C_TX_START;
465         if (flags & I2CF_STOP_COND) {
466                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
467                 rxbd->status |= BD_SC_WRAP;
468         }
469
470         PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
471                    txbd->length,
472                    txbd->status,
473                    txbd->addr[0],
474                    txbd->addr[1]));
475         PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
476                    rxbd->length,
477                    rxbd->status,
478                    rxbd->addr[0],
479                    rxbd->addr[1]));
480
481         /* advance state */
482         state->tx_buf += txbd->length;
483         state->tx_space -= txbd->length;
484         state->tx_idx++;
485         state->txbd = (void*)(txbd + 1);
486         state->rx_idx++;
487         state->rxbd = (void*)(rxbd + 1);
488
489         return 0;
490 }
491
492
493 static int i2c_doio(i2c_state_t *state)
494 {
495         volatile immap_t *immap = (immap_t *)CFG_IMMR ;
496         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
497         volatile i2c8xx_t *i2c  = (i2c8xx_t *)&immap->im_i2c;
498         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
499         volatile I2C_BD *txbd, *rxbd;
500         volatile int j = 0;
501
502         PRINTD(("[I2C] i2c_doio\n"));
503
504 #ifdef CFG_I2C_UCODE_PATCH
505         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
506 #endif
507
508         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
509                 PRINTD(("[I2C] No I/O is queued\n"));
510                 return I2CERR_QUEUE_EMPTY;
511         }
512
513         iip->iic_rbptr = iip->iic_rbase;
514         iip->iic_tbptr = iip->iic_tbase;
515
516         /* Enable I2C */
517         PRINTD(("[I2C] Enabling I2C...\n"));
518         i2c->i2c_i2mod |= 0x01;
519
520         /* Begin transmission */
521         i2c->i2c_i2com |= 0x80;
522
523         /* Loop until transmit & receive completed */
524
525         if (state->tx_idx > 0) {
526                 txbd = ((I2C_BD*)state->txbd) - 1;
527                 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
528                 while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
529                         if (ctrlc()) {
530                                 return (-1);
531                         }
532                         __asm__ __volatile__ ("eieio");
533                 }
534         }
535
536         if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
537                 rxbd = ((I2C_BD*)state->rxbd) - 1;
538                 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
539                 while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
540                         if (ctrlc()) {
541                                 return (-1);
542                         }
543                         __asm__ __volatile__ ("eieio");
544                 }
545         }
546
547         /* Turn off I2C */
548         i2c->i2c_i2mod &= ~0x01;
549
550         if (state->err_cb != NULL) {
551                 int n, i, b;
552
553                 /*
554                  * if we have an error callback function, look at the
555                  * error bits in the bd status and pass them back
556                  */
557
558                 if ((n = state->tx_idx) > 0) {
559                         for (i = 0; i < n; i++) {
560                                 txbd = ((I2C_BD*)state->txbd) - (n - i);
561                                 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
562                                         (*state->err_cb)(I2CECB_TX_ERR|b, i);
563                         }
564                 }
565
566                 if ((n = state->rx_idx) > 0) {
567                         for (i = 0; i < n; i++) {
568                                 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
569                                 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
570                                         (*state->err_cb)(I2CECB_RX_ERR|b, i);
571                         }
572                 }
573
574                 if (j >= TOUT_LOOP)
575                         (*state->err_cb)(I2CECB_TIMEOUT, 0);
576         }
577
578         return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
579 }
580
581 static int had_tx_nak;
582
583 static void
584 i2c_test_callback(int flags, int xnum)
585 {
586         if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
587                 had_tx_nak = 1;
588 }
589
590 int i2c_probe(uchar chip)
591 {
592         i2c_state_t state;
593         int rc;
594         uchar buf[1];
595
596         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
597
598         i2c_newio(&state);
599
600         state.err_cb = i2c_test_callback;
601         had_tx_nak = 0;
602
603         rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
604
605         if (rc != 0)
606                 return (rc);
607
608         rc = i2c_doio(&state);
609
610         if ((rc != 0) && (rc != I2CERR_TIMEOUT))
611                 return (rc);
612
613         return (had_tx_nak);
614 }
615
616 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
617 {
618         i2c_state_t state;
619         uchar xaddr[4];
620         int rc;
621
622 #ifdef CONFIG_LWMON
623         WATCHDOG_RESET();
624 #endif
625
626         xaddr[0] = (addr >> 24) & 0xFF;
627         xaddr[1] = (addr >> 16) & 0xFF;
628         xaddr[2] = (addr >>  8) & 0xFF;
629         xaddr[3] =  addr        & 0xFF;
630
631 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
632         /*
633          * EEPROM chips that implement "address overflow" are ones like
634          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
635          * extra bits end up in the "chip address" bit slots.  This makes
636          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
637          *
638          * Note that we consider the length of the address field to still
639          * be one byte because the extra address bits are hidden in the
640          * chip address.
641          */
642          chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
643 #endif
644
645         i2c_newio(&state);
646
647         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
648         if (rc != 0) {
649                 if (gd->have_console)
650                         printf("i2c_read: i2c_send failed (%d)\n", rc);
651                 return 1;
652         }
653
654         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
655         if (rc != 0) {
656                 if (gd->have_console)
657                         printf("i2c_read: i2c_receive failed (%d)\n", rc);
658                 return 1;
659         }
660
661         rc = i2c_doio(&state);
662         if (rc != 0) {
663                 if (gd->have_console)
664                         printf("i2c_read: i2c_doio failed (%d)\n", rc);
665                 return 1;
666         }
667         return 0;
668 }
669
670 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
671 {
672         i2c_state_t state;
673         uchar xaddr[4];
674         int rc;
675
676         xaddr[0] = (addr >> 24) & 0xFF;
677         xaddr[1] = (addr >> 16) & 0xFF;
678         xaddr[2] = (addr >>  8) & 0xFF;
679         xaddr[3] =  addr        & 0xFF;
680
681 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
682         /*
683          * EEPROM chips that implement "address overflow" are ones like
684          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
685          * extra bits end up in the "chip address" bit slots.  This makes
686          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
687          *
688          * Note that we consider the length of the address field to still
689          * be one byte because the extra address bits are hidden in the
690          * chip address.
691          */
692          chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
693 #endif
694
695         i2c_newio(&state);
696
697         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
698         if (rc != 0) {
699                 if (gd->have_console)
700                         printf("i2c_write: first i2c_send failed (%d)\n", rc);
701                 return 1;
702         }
703
704         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
705         if (rc != 0) {
706                 if (gd->have_console)
707                         printf("i2c_write: second i2c_send failed (%d)\n", rc);
708                 return 1;
709         }
710
711         rc = i2c_doio(&state);
712         if (rc != 0) {
713                 if (gd->have_console)
714                         printf("i2c_write: i2c_doio failed (%d)\n", rc);
715                 return 1;
716         }
717         return 0;
718 }
719
720 uchar
721 i2c_reg_read(uchar i2c_addr, uchar reg)
722 {
723         uchar buf;
724
725         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
726
727         i2c_read(i2c_addr, reg, 1, &buf, 1);
728
729         return (buf);
730 }
731
732 void
733 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
734 {
735         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
736
737         i2c_write(i2c_addr, reg, 1, &val, 1);
738 }
739
740 #endif  /* CONFIG_HARD_I2C */