2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <mpc8xx_irq.h>
28 #include <asm/processor.h>
31 /****************************************************************************/
33 unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
35 /****************************************************************************/
38 * CPM interrupt vector functions.
41 interrupt_handler_t *handler;
45 static struct cpm_action cpm_vecs[CPMVEC_NR];
47 static void cpm_interrupt_init (void);
48 static void cpm_interrupt(int irq, struct pt_regs * regs);
50 /****************************************************************************/
52 static __inline__ unsigned long get_msr(void)
56 asm volatile("mfmsr %0" : "=r" (msr) :);
60 static __inline__ void set_msr(unsigned long msr)
62 asm volatile("mtmsr %0" : : "r" (msr));
65 static __inline__ unsigned long get_dec(void)
69 asm volatile("mfdec %0" : "=r" (val) :);
74 static __inline__ void set_dec(unsigned long val)
76 asm volatile("mtdec %0" : : "r" (val));
80 void enable_interrupts (void)
82 set_msr (get_msr() | MSR_EE);
85 /* returns flag if MSR_EE was set before */
86 int disable_interrupts (void)
88 ulong msr = get_msr();
89 set_msr (msr & ~MSR_EE);
90 return ((msr & MSR_EE) != 0);
93 /****************************************************************************/
95 int interrupt_init(void)
97 volatile immap_t *immr = (immap_t *)CFG_IMMR;
99 decrementer_count = get_tbclk() / CFG_HZ;
101 cpm_interrupt_init();
103 /* disable all interrupts except for the CPM interrupt */
104 immr->im_siu_conf.sc_simask = 1 << (31-CPM_INTERRUPT);
106 set_dec (decrementer_count);
108 set_msr (get_msr() | MSR_EE);
113 /****************************************************************************/
116 * Handle external interrupts
118 void external_interrupt(struct pt_regs *regs)
120 volatile immap_t *immr = (immap_t *)CFG_IMMR;
122 ulong simask, newmask;
126 * read the SIVEC register and shift the bits down
127 * to get the irq number
129 vec = immr->im_siu_conf.sc_sivec;
131 v_bit = 0x80000000UL >> irq;
134 * Read Interrupt Mask Register and Mask Interrupts
136 simask = immr->im_siu_conf.sc_simask;
137 newmask = simask & (~(0xFFFF0000 >> irq));
138 immr->im_siu_conf.sc_simask = newmask;
140 if (!(irq & 0x1)) { /* External Interrupt ? */
143 * Read Interrupt Edge/Level Register
145 siel = immr->im_siu_conf.sc_siel;
147 if (siel & v_bit) { /* edge triggered interrupt ? */
149 * Rewrite SIPEND Register to clear interrupt
151 immr->im_siu_conf.sc_sipend = v_bit;
157 cpm_interrupt (irq, regs);
160 printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
162 /* turn off the bogus interrupt to avoid it from now */
168 * Re-Enable old Interrupt Mask
170 immr->im_siu_conf.sc_simask = simask;
173 /****************************************************************************/
176 * CPM interrupt handler
179 cpm_interrupt(int irq, struct pt_regs * regs)
181 volatile immap_t *immr = (immap_t *)CFG_IMMR;
185 * Get the vector by setting the ACK bit
186 * and then reading the register.
188 immr->im_cpic.cpic_civr = 1;
189 vec = immr->im_cpic.cpic_civr;
192 if (cpm_vecs[vec].handler != NULL) {
193 (*cpm_vecs[vec].handler)(cpm_vecs[vec].arg);
195 immr->im_cpic.cpic_cimr &= ~(1 << vec);
196 printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
199 * After servicing the interrupt, we have to remove the status indicator.
201 immr->im_cpic.cpic_cisr |= (1 << vec);
205 * The CPM can generate the error interrupt when there is a race
206 * condition between generating and masking interrupts. All we have
207 * to do is ACK it and return. This is a no-op function so we don't
208 * need any special tests in the interrupt handler.
211 cpm_error_interrupt (void *dummy)
215 /****************************************************************************/
218 * Install and free a CPM interrupt handler.
222 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
224 volatile immap_t *immr = (immap_t *)CFG_IMMR;
226 if (cpm_vecs[vec].handler != NULL) {
227 printf ("CPM interrupt 0x%x replacing 0x%x\n",
228 (uint)handler, (uint)cpm_vecs[vec].handler);
230 cpm_vecs[vec].handler = handler;
231 cpm_vecs[vec].arg = arg;
232 immr->im_cpic.cpic_cimr |= (1 << vec);
234 printf ("Install CPM interrupt for vector %d ==> %p\n", vec, handler);
239 irq_free_handler(int vec)
241 volatile immap_t *immr = (immap_t *)CFG_IMMR;
243 printf ("Free CPM interrupt for vector %d ==> %p\n",
244 vec, cpm_vecs[vec].handler);
246 immr->im_cpic.cpic_cimr &= ~(1 << vec);
247 cpm_vecs[vec].handler = NULL;
248 cpm_vecs[vec].arg = NULL;
251 /****************************************************************************/
254 cpm_interrupt_init (void)
256 volatile immap_t *immr = (immap_t *)CFG_IMMR;
259 * Initialize the CPM interrupt controller.
262 immr->im_cpic.cpic_cicr =
266 CICR_SCA_SCC1 ) | ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
268 immr->im_cpic.cpic_cimr = 0;
271 * Install the error handler.
273 irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
275 immr->im_cpic.cpic_cicr |= CICR_IEN;
278 /****************************************************************************/
280 volatile ulong timestamp = 0;
283 * timer_interrupt - gets called when the decrementer overflows,
284 * with interrupts disabled.
285 * Trivial implementation - no need to be really accurate.
287 void timer_interrupt(struct pt_regs *regs)
289 volatile immap_t *immr = (immap_t *)CFG_IMMR;
290 #ifdef CONFIG_STATUS_LED
291 extern void status_led_tick (ulong);
294 printf ("*** Timer Interrupt *** ");
296 /* Reset Timer Expired and Timers Interrupt Status */
297 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
299 immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
300 /* Restore Decrementer Count */
301 set_dec (decrementer_count);
305 #ifdef CONFIG_STATUS_LED
306 status_led_tick (timestamp);
307 #endif /* CONFIG_STATUS_LED */
309 #if defined(CONFIG_WATCHDOG) || defined(CFG_CMA_LCD_HEARTBEAT)
313 * The shortest watchdog period of all boards (except LWMON)
314 * is approx. 1 sec, thus re-trigger watchdog at least
315 * every 500 ms = CFG_HZ / 2
318 if ((timestamp % (CFG_HZ / 2)) == 0) {
320 if ((timestamp % (CFG_HZ / 20)) == 0) {
323 #if defined(CFG_CMA_LCD_HEARTBEAT)
324 extern void lcd_heartbeat(void);
326 #endif /* CFG_CMA_LCD_HEARTBEAT */
328 #if defined(CONFIG_WATCHDOG)
329 reset_8xx_watchdog(immr);
330 #endif /* CONFIG_WATCHDOG */
334 #endif /* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
337 /****************************************************************************/
339 void reset_timer (void)
344 ulong get_timer (ulong base)
346 return (timestamp - base);
349 void set_timer (ulong t)
354 /****************************************************************************/