4 * Basic ET HW initialization and packet RX/TX routines
6 * NOTE <<<IMPORTANT: PLEASE READ>>>:
7 * Do not cache Rx/Tx buffers!
11 * MPC823 <-> MC68160 Connections:
13 * Setup MPC823 to work with MC68160 Enhanced Ethernet
14 * Serial Tranceiver as follows:
16 * MPC823 Signal MC68160 Comments
17 * ------ ------ ------- --------
18 * PA-12 ETHTX --------> TX Eth. Port Transmit Data
19 * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
20 * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
21 * PA-13 ETHRX <-------- RX Eth. Port Receive Data
22 * PC-8 E_RENA <-------- RENA Eth. Receive Enable
23 * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
24 * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
26 * FADS Board Signal MC68160 Comments
27 * ----------------- ------- --------
28 * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
29 * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
30 * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
31 * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
41 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)
43 /* Ethernet Transmit and Receive Buffers */
44 #define DBUF_LENGTH 1520
48 #define TOUT_LOOP 10000 /* 10 ms to have a packet sent */
50 static char txbuf[DBUF_LENGTH];
52 static uint rxIdx; /* index of the current RX buffer */
53 static uint txIdx; /* index of the current TX buffer */
56 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
57 * immr->udata_bd address on Dual-Port RAM
58 * Provide for Double Buffering
61 typedef volatile struct CommonBufferDescriptor {
62 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
63 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
68 static int scc_send(struct eth_device* dev, volatile void *packet, int length);
69 static int scc_recv(struct eth_device* dev);
70 static int scc_init (struct eth_device* dev, bd_t * bd);
71 static void scc_halt(struct eth_device* dev);
73 int scc_initialize(bd_t *bis)
75 struct eth_device* dev;
77 dev = (struct eth_device*) malloc(sizeof *dev);
78 memset(dev, 0, sizeof *dev);
80 sprintf(dev->name, "SCC ETHERNET");
93 static int scc_send(struct eth_device* dev, volatile void *packet, int length)
97 volatile char *in, *out;
104 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
105 out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
107 for(i = 0; i < length; i++) {
110 rtx->txbd[txIdx].cbd_datlen = length;
111 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
112 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
115 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
117 i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
119 /* wrap around buffer index when necessary */
120 if (txIdx >= TX_BUF_CNT) txIdx = 0;
123 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
124 udelay (1); /* will also trigger Wd if needed */
127 if (j>=TOUT_LOOP) printf("TX not ready\n");
128 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
129 rtx->txbd[txIdx].cbd_datlen = length;
130 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
131 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
132 udelay (1); /* will also trigger Wd if needed */
135 if (j>=TOUT_LOOP) printf("TX timeout\n");
137 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
139 i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
143 static int scc_recv (struct eth_device *dev)
148 /* section 16.9.23.2 */
149 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
151 break; /* nothing received - leave for() loop */
154 length = rtx->rxbd[rxIdx].cbd_datlen;
156 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
158 printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
161 /* Pass the packet up to the protocol layers. */
162 NetReceive (NetRxPackets[rxIdx], length - 4);
166 /* Give the buffer back to the SCC. */
167 rtx->rxbd[rxIdx].cbd_datlen = 0;
169 /* wrap around buffer index when necessary */
170 if ((rxIdx + 1) >= PKTBUFSRX) {
171 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
172 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
175 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
182 /**************************************************************
184 * SCC Ethernet Initialization Routine
186 *************************************************************/
188 static int scc_init (struct eth_device *dev, bd_t * bis)
192 scc_enet_t *pram_ptr;
194 volatile immap_t *immr = (immap_t *) CFG_IMMR;
196 #if defined(CONFIG_LWMON)
201 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
202 /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
203 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
204 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
205 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
207 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
208 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
209 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
213 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
218 #ifdef CFG_ALLOC_DPRAM
219 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
220 dpram_alloc_align (sizeof (RTXBD), 8));
222 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
225 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
226 /* Configure port A pins for Txd and Rxd.
228 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
229 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
230 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
231 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
232 /* Configure port B pins for Txd and Rxd.
234 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
235 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
236 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
238 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
241 #if defined(PC_ENET_LBK)
242 /* Configure port C pins to disable External Loopback
244 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
245 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
246 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
247 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
248 #endif /* PC_ENET_LBK */
250 /* Configure port C pins to enable CLSN and RENA.
252 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
253 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
254 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
256 /* Configure port A for TCLK and RCLK.
258 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
259 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
262 * Configure Serial Interface clock routing -- see section 16.7.5.3
263 * First, clear all SCC bits to zero, then set the ones we want.
266 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
267 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
271 * Initialize SDCR -- see section 16.9.23.7
272 * SDMA configuration register
274 immr->im_siu_conf.sc_sdcr = 0x01;
278 * Setup SCC Ethernet Parameter RAM
281 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
282 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
284 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
286 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
287 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
290 * Setup Receiver Buffer Descriptors (13.14.24.18)
295 for (i = 0; i < PKTBUFSRX; i++) {
296 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
297 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
298 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
301 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
304 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
306 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
309 for (i = 0; i < TX_BUF_CNT; i++) {
310 rtx->txbd[i].cbd_sc =
311 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
312 rtx->txbd[i].cbd_datlen = 0; /* Reset */
313 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
316 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
319 * Enter Command: Initialize Rx Params for SCC
322 do { /* Spin until ready to issue command */
324 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
326 immr->im_cpm.cp_cpcr =
327 ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
328 do { /* Spin until command processed */
330 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
333 * Ethernet Specific Parameter RAM
334 * see table 13-16, pg. 660,
335 * pg. 681 (example with suggested settings)
338 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
339 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
340 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
341 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
342 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
343 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
345 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
346 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
347 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
349 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
350 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
352 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
353 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
354 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
355 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
357 #define ea eth_get_dev()->enetaddr
358 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
359 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
360 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
363 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
364 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
365 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
366 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
367 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
368 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
369 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
370 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
373 * Enter Command: Initialize Tx Params for SCC
376 do { /* Spin until ready to issue command */
378 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
380 immr->im_cpm.cp_cpcr =
381 ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
382 do { /* Spin until command processed */
384 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
387 * Mask all Events in SCCM - we use polling mode
389 immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
392 * Clear Events in SCCE -- Clear bits by writing 1's
395 immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
399 * Initialize GSMR High 32-Bits
400 * Settings: Normal Mode
403 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
406 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
410 * TPP = Repeating 10's
414 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
417 SCC_GSMRL_MODE_ENET);
420 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
423 immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
426 * Initialize the PSMR
429 * NIB = Begin searching for SFD 22 bits after RENA
430 * FDE = Full Duplex Enable
431 * LPB = Loopback Enable (Needed when FDE is set)
432 * BRO = Reject broadcast packets
433 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
435 immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
437 #if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
438 SCC_PSMR_FDE | SCC_PSMR_LPB |
440 #if defined(CONFIG_SCC_ENET_NO_BROADCAST)
443 #if defined(CONFIG_SCC_ENET_PROMISCOUS)
449 * Configure Ethernet TENA Signal
452 #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
453 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
454 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
455 #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
456 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
457 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
459 #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
462 #if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
464 * Port C is used to control the PHY,MC68160.
466 immr->im_ioport.iop_pcdir |=
467 (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
469 immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
470 immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
471 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
472 #endif /* MPC860ADS */
474 #if defined(CONFIG_AMX860)
476 * Port B is used to control the PHY,MC68160.
478 immr->im_cpm.cp_pbdir |=
479 (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
481 immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
482 immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
484 immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
485 immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
488 #ifdef CONFIG_RPXCLASSIC
489 *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
490 *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
493 #ifdef CONFIG_RPXLITE
494 *((uchar *) BCSR0) |= BCSR0_ETHEN;
497 #if defined(CONFIG_QS860T)
499 * PB27=FDE-, set output low for full duplex
500 * PB26=Link Test Enable, normally high output
502 immr->im_cpm.cp_pbdir |= 0x00000030;
503 immr->im_cpm.cp_pbdat |= 0x00000020;
504 immr->im_cpm.cp_pbdat &= ~0x00000010;
511 #if defined(CONFIG_NETVIA)
512 #if defined(PA_ENET_PDN)
513 immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
514 immr->im_ioport.iop_padir |= PA_ENET_PDN;
515 immr->im_ioport.iop_padat |= PA_ENET_PDN;
516 #elif defined(PB_ENET_PDN)
517 immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
518 immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
519 immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
520 #elif defined(PC_ENET_PDN)
521 immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
522 immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
523 immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
524 #elif defined(PD_ENET_PDN)
525 immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
526 immr->im_ioport.iop_pddir |= PD_ENET_PDN;
527 immr->im_ioport.iop_pddat |= PD_ENET_PDN;
532 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
535 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
536 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
539 * Work around transmit problem with first eth packet
541 #if defined (CONFIG_FADS)
542 udelay (10000); /* wait 10 ms */
543 #elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
544 udelay (100000); /* wait 100 ms */
551 static void scc_halt (struct eth_device *dev)
553 volatile immap_t *immr = (immap_t *) CFG_IMMR;
555 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
556 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
558 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
564 volatile immap_t *immr = (immap_t *) CFG_IMMR;
566 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
567 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
570 #endif /* CFG_CMD_NET, SCC_ENET */