3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
31 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
34 #define PROFF_SMC PROFF_SMC1
35 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
37 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
40 #define PROFF_SMC PROFF_SMC2
41 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
43 #elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
46 #define PROFF_SCC PROFF_SCC1
47 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
49 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
52 #define PROFF_SCC PROFF_SCC2
53 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
55 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
64 #define PROFF_SCC PROFF_SCC4
65 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
67 #else /* CONFIG_8xx_CONS_? */
68 #error "console not correctly defined"
71 static void serial_setdivisor(volatile cpm8xx_t *cp)
73 DECLARE_GLOBAL_DATA_PTR;
74 int divisor=gd->cpu_clk/16/gd->baudrate;
76 if(divisor/16>0x1000) {
77 /* bad divisor, assume 50Mhz clock and 9600 baud */
78 divisor=(50*1000*1000)/16/9600;
82 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
84 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
91 * Minimal serial functions needed to use one of the SMC ports
92 * as serial console interface.
95 int serial_init (void)
97 volatile immap_t *im = (immap_t *)CFG_IMMR;
99 volatile smc_uart_t *up;
100 volatile cbd_t *tbdf, *rbdf;
101 volatile cpm8xx_t *cp = &(im->im_cpm);
102 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
103 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
107 /* initialize pointers to SMC */
109 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
110 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
112 /* Disable transmitter/receiver.
114 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
118 im->im_siu_conf.sc_sdcr = 1;
120 /* clear error conditions */
122 im->im_sdma.sdma_sdsr = CFG_SDSR;
124 im->im_sdma.sdma_sdsr = 0x83;
127 /* clear SDMA interrupt mask */
129 im->im_sdma.sdma_sdmr = CFG_SDMR;
131 im->im_sdma.sdma_sdmr = 0x00;
134 #if defined(CONFIG_8xx_CONS_SMC1)
135 /* Use Port B for SMC1 instead of other functions.
137 cp->cp_pbpar |= 0x000000c0;
138 cp->cp_pbdir &= ~0x000000c0;
139 cp->cp_pbodr &= ~0x000000c0;
140 #else /* CONFIG_8xx_CONS_SMC2 */
141 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
142 /* Use Port A for SMC2 instead of other functions.
144 ip->iop_papar |= 0x00c0;
145 ip->iop_padir &= ~0x00c0;
146 ip->iop_paodr &= ~0x00c0;
147 # else /* must be a 860 then */
148 /* Use Port B for SMC2 instead of other functions.
150 cp->cp_pbpar |= 0x00000c00;
151 cp->cp_pbdir &= ~0x00000c00;
152 cp->cp_pbodr &= ~0x00000c00;
156 #if defined(CONFIG_FADS)
158 #if defined(CONFIG_8xx_CONS_SMC1)
159 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
161 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
163 #endif /* CONFIG_FADS */
165 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
166 /* Enable Monitor Port Transceiver */
167 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
168 #endif /* CONFIG_RPXLITE */
170 /* Set the physical address of the host memory buffers in
171 * the buffer descriptors.
174 #ifdef CFG_ALLOC_DPRAM
175 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
177 dpaddr = CPM_SERIAL_BASE ;
180 /* Allocate space for two buffer descriptors in the DP ram.
181 * For now, this address seems OK, but it may have to
182 * change with newer versions of the firmware.
183 * damm: allocating space after the two buffers for rx/tx data
186 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
187 rbdf->cbd_bufaddr = (uint) (rbdf+2);
190 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
193 /* Set up the uart parameters in the parameter ram.
195 up->smc_rbase = dpaddr;
196 up->smc_tbase = dpaddr+sizeof(cbd_t);
197 up->smc_rfcr = SMC_EB;
198 up->smc_tfcr = SMC_EB;
200 #if defined(CONFIG_MBX)
202 #endif /* CONFIG_MBX */
204 /* Set UART mode, 8 bit, no parity, one stop.
205 * Enable receive and transmit.
207 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
209 /* Mask all interrupts and remove anything pending.
214 /* Set up the baud rate generator.
218 /* Make the first buffer the only buffer.
220 tbdf->cbd_sc |= BD_SC_WRAP;
221 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
223 /* Single character receive.
228 /* Initialize Tx/Rx parameters.
231 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
234 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
236 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
239 /* Enable transmitter/receiver.
241 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
249 volatile immap_t *im = (immap_t *)CFG_IMMR;
250 volatile cpm8xx_t *cp = &(im->im_cpm);
252 /* Set up the baud rate generator.
253 * See 8xx_io/commproc.c for details.
258 cp->cp_simode = 0x00000000;
260 serial_setdivisor(cp);
263 #ifdef CONFIG_MODEM_SUPPORT
264 void disable_putc(void)
266 DECLARE_GLOBAL_DATA_PTR;
270 void enable_putc(void)
272 DECLARE_GLOBAL_DATA_PTR;
278 serial_putc(const char c)
280 volatile cbd_t *tbdf;
282 volatile smc_uart_t *up;
283 volatile immap_t *im = (immap_t *)CFG_IMMR;
284 volatile cpm8xx_t *cpmp = &(im->im_cpm);
286 #ifdef CONFIG_MODEM_SUPPORT
287 DECLARE_GLOBAL_DATA_PTR;
296 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
298 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
300 /* Wait for last character to go.
303 buf = (char *)tbdf->cbd_bufaddr;
306 tbdf->cbd_datlen = 1;
307 tbdf->cbd_sc |= BD_SC_READY;
310 while (tbdf->cbd_sc & BD_SC_READY) {
319 volatile cbd_t *rbdf;
320 volatile unsigned char *buf;
321 volatile smc_uart_t *up;
322 volatile immap_t *im = (immap_t *)CFG_IMMR;
323 volatile cpm8xx_t *cpmp = &(im->im_cpm);
326 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
328 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
330 /* Wait for character to show up.
332 buf = (unsigned char *)rbdf->cbd_bufaddr;
334 while (rbdf->cbd_sc & BD_SC_EMPTY)
338 rbdf->cbd_sc |= BD_SC_EMPTY;
346 volatile cbd_t *rbdf;
347 volatile smc_uart_t *up;
348 volatile immap_t *im = (immap_t *)CFG_IMMR;
349 volatile cpm8xx_t *cpmp = &(im->im_cpm);
351 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
353 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
355 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
358 #else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
360 int serial_init (void)
362 volatile immap_t *im = (immap_t *)CFG_IMMR;
364 volatile scc_uart_t *up;
365 volatile cbd_t *tbdf, *rbdf;
366 volatile cpm8xx_t *cp = &(im->im_cpm);
368 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
369 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
372 /* initialize pointers to SCC */
374 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
375 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
377 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
378 { /* Disable Ethernet, enable Serial */
382 c &= ~0x40; /* enable COM3 */
383 c |= 0x80; /* disable Ethernet */
387 cp->cp_pbpar |= 0x2000;
388 cp->cp_pbdat |= 0x2000;
389 cp->cp_pbdir |= 0x2000;
391 #endif /* CONFIG_LWMON */
393 /* Disable transmitter/receiver.
395 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
397 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
399 * The MPC850 has SCC3 on Port B
401 cp->cp_pbpar |= 0x06;
402 cp->cp_pbdir &= ~0x06;
403 cp->cp_pbodr &= ~0x06;
405 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
407 * Standard configuration for SCC's is on Part A
409 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
410 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
411 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
414 * The IP860 has SCC3 and SCC4 on Port D
416 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
419 /* Allocate space for two buffer descriptors in the DP ram.
422 #ifdef CFG_ALLOC_DPRAM
423 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
425 dpaddr = CPM_SERIAL_BASE ;
430 im->im_siu_conf.sc_sdcr = 0x0001;
432 /* Set the physical address of the host memory buffers in
433 * the buffer descriptors.
436 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
437 rbdf->cbd_bufaddr = (uint) (rbdf+2);
440 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
443 /* Set up the baud rate generator.
447 /* Set up the uart parameters in the parameter ram.
449 up->scc_genscc.scc_rbase = dpaddr;
450 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
452 /* Initialize Tx/Rx parameters.
454 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
456 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
458 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
461 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
462 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
464 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
465 up->scc_maxidl = 0; /* disable max idle */
466 up->scc_brkcr = 1; /* send one break character on stop TX */
474 up->scc_char1 = 0x8000;
475 up->scc_char2 = 0x8000;
476 up->scc_char3 = 0x8000;
477 up->scc_char4 = 0x8000;
478 up->scc_char5 = 0x8000;
479 up->scc_char6 = 0x8000;
480 up->scc_char7 = 0x8000;
481 up->scc_char8 = 0x8000;
482 up->scc_rccm = 0xc0ff;
484 /* Set low latency / small fifo.
486 sp->scc_gsmrh = SCC_GSMRH_RFW;
488 /* Set SCC(x) clock mode to 16x
489 * See 8xx_io/commproc.c for details.
494 /* Set UART mode, clock divider 16 on Tx and Rx
497 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
499 sp->scc_psmr |= SCU_PSMR_CL;
501 /* Mask all interrupts and remove anything pending.
504 sp->scc_scce = 0xffff;
505 sp->scc_dsr = 0x7e7e;
506 sp->scc_psmr = 0x3000;
508 /* Make the first buffer the only buffer.
510 tbdf->cbd_sc |= BD_SC_WRAP;
511 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
513 /* Enable transmitter/receiver.
515 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
523 volatile immap_t *im = (immap_t *)CFG_IMMR;
524 volatile cpm8xx_t *cp = &(im->im_cpm);
526 /* Set up the baud rate generator.
527 * See 8xx_io/commproc.c for details.
532 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
534 serial_setdivisor(cp);
538 serial_putc(const char c)
540 volatile cbd_t *tbdf;
542 volatile scc_uart_t *up;
543 volatile immap_t *im = (immap_t *)CFG_IMMR;
544 volatile cpm8xx_t *cpmp = &(im->im_cpm);
549 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
551 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
553 /* Wait for last character to go.
556 buf = (char *)tbdf->cbd_bufaddr;
559 tbdf->cbd_datlen = 1;
560 tbdf->cbd_sc |= BD_SC_READY;
563 while (tbdf->cbd_sc & BD_SC_READY) {
572 volatile cbd_t *rbdf;
573 volatile unsigned char *buf;
574 volatile scc_uart_t *up;
575 volatile immap_t *im = (immap_t *)CFG_IMMR;
576 volatile cpm8xx_t *cpmp = &(im->im_cpm);
579 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
581 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
583 /* Wait for character to show up.
585 buf = (unsigned char *)rbdf->cbd_bufaddr;
587 while (rbdf->cbd_sc & BD_SC_EMPTY)
591 rbdf->cbd_sc |= BD_SC_EMPTY;
599 volatile cbd_t *rbdf;
600 volatile scc_uart_t *up;
601 volatile immap_t *im = (immap_t *)CFG_IMMR;
602 volatile cpm8xx_t *cpmp = &(im->im_cpm);
604 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
606 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
608 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
611 #endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
615 serial_puts (const char *s)
623 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
626 kgdb_serial_init(void)
628 #if defined(CONFIG_8xx_CONS_SMC1)
629 serial_printf("[on SMC1] ");
630 #elif defined(CONFIG_8xx_CONS_SMC2)
631 serial_printf("[on SMC2] ");
632 #elif defined(CONFIG_8xx_CONS_SCC1)
633 serial_printf("[on SCC1] ");
634 #elif defined(CONFIG_8xx_CONS_SCC2)
635 serial_printf("[on SCC2] ");
636 #elif defined(CONFIG_8xx_CONS_SCC3)
637 serial_printf("[on SCC3] ");
638 #elif defined(CONFIG_8xx_CONS_SCC4)
639 serial_printf("[on SCC4] ");
650 putDebugStr (const char *str)
658 return serial_getc();
662 kgdb_interruptible (int yes)
666 #endif /* CFG_CMD_KGDB */
668 #endif /* CONFIG_8xx_CONS_NONE */