2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
16 #include <asm/fsl_ddr_sdram.h>
20 extern unsigned int picos_to_mclk(unsigned int picos);
22 * Determine Rtt value.
24 * This should likely be either board or controller specific.
32 * FIXME: Apparently 8641 needs a value of 2
33 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
35 * FIXME: There was some effort down this line earlier:
38 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
39 * if (popts->dimmslot[i].num_valid_cs
40 * && (popts->cs_local_opts[2*i].odt_rd_cfg
41 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
47 static inline int fsl_ddr_get_rtt(void)
51 #if defined(CONFIG_FSL_DDR1)
53 #elif defined(CONFIG_FSL_DDR2)
56 #error "Need Rtt value for DDR3"
62 /* Chip Select Configuration (CSn_CONFIG) */
63 static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
64 const memctl_options_t *popts,
65 const dimm_params_t *dimm_params)
67 unsigned int cs_n_en = 0; /* Chip Select enable */
68 unsigned int intlv_en = 0; /* Memory controller interleave enable */
69 unsigned int intlv_ctl = 0; /* Interleaving control */
70 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
71 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
72 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
73 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
74 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
75 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
77 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
79 && (dimm_params[i/2].n_ranks == 1))
80 || (dimm_params[i/2].n_ranks == 2)) {
81 unsigned int n_banks_per_sdram_device;
84 /* These fields only available in CS0_CONFIG */
85 intlv_en = popts->memctl_interleaving;
86 intlv_ctl = popts->memctl_interleaving_mode;
88 ap_n_en = popts->cs_local_opts[i].auto_precharge;
89 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
90 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
91 n_banks_per_sdram_device
92 = dimm_params[i/2].n_banks_per_sdram_device;
93 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
94 row_bits_cs_n = dimm_params[i/2].n_row_addr - 12;
95 col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
98 ddr->cs[i].config = (0
99 | ((cs_n_en & 0x1) << 31)
100 | ((intlv_en & 0x3) << 29)
101 | ((intlv_ctl & 0xf) << 24)
102 | ((ap_n_en & 0x1) << 23)
104 /* XXX: some implementation only have 1 bit starting at left */
105 | ((odt_rd_cfg & 0x7) << 20)
107 /* XXX: Some implementation only have 1 bit starting at left */
108 | ((odt_wr_cfg & 0x7) << 16)
110 | ((ba_bits_cs_n & 0x3) << 14)
111 | ((row_bits_cs_n & 0x7) << 8)
112 | ((col_bits_cs_n & 0x7) << 0)
114 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
117 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
119 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
121 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
123 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
124 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
127 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
129 #if defined(CONFIG_FSL_DDR2)
131 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
133 * Avoid writing for DDR I. The new PQ38 DDR controller
134 * dreams up non-zero default values to be backwards compatible.
136 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
138 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
139 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
140 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
141 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
142 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
144 /* Active powerdown exit timing (tXARD and tXARDS). */
145 unsigned char act_pd_exit_mclk;
146 /* Precharge powerdown exit timing (tXP). */
147 unsigned char pre_pd_exit_mclk;
148 /* Precharge powerdown exit timing (tAXPD). */
149 unsigned char taxpd_mclk;
150 /* Mode register set cycle time (tMRD). */
151 unsigned char tmrd_mclk;
153 /* (tXARD and tXARDS). Empirical? */
154 act_pd_exit_mclk = 2;
156 /* XXX: tXARD = 2, tXARDS = 7 - AL. * Empirical? */
157 pre_pd_exit_mclk = 6;
159 /* FIXME: tXP = 2 on Micron 667 MHz DIMM */
164 ddr->timing_cfg_0 = (0
165 | ((trwt_mclk & 0x3) << 30) /* RWT */
166 | ((twrt_mclk & 0x3) << 28) /* WRT */
167 | ((trrt_mclk & 0x3) << 26) /* RRT */
168 | ((twwt_mclk & 0x3) << 24) /* WWT */
169 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
170 | ((pre_pd_exit_mclk & 0x7) << 16) /* PRE_PD_EXIT */
171 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
172 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
174 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
176 #endif /* defined(CONFIG_FSL_DDR2) */
178 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
179 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
180 const common_timing_params_t *common_dimm)
182 /* Extended Activate to precharge interval (tRAS) */
183 unsigned int ext_acttopre = 0;
184 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
185 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
186 unsigned int cntl_adj = 0; /* Control Adjust */
188 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
189 ddr->timing_cfg_3 = (0
190 | ((ext_acttopre & 0x1) << 24)
191 | ((ext_refrec & 0x7) << 16)
192 | ((ext_caslat & 0x1) << 12)
193 | ((cntl_adj & 0x7) << 0)
195 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
198 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
199 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
200 const common_timing_params_t *common_dimm,
201 unsigned int cas_latency)
203 /* Precharge-to-activate interval (tRP) */
204 unsigned char pretoact_mclk;
205 /* Activate to precharge interval (tRAS) */
206 unsigned char acttopre_mclk;
207 /* Activate to read/write interval (tRCD) */
208 unsigned char acttorw_mclk;
210 unsigned char caslat_ctrl;
211 /* Refresh recovery time (tRFC) ; trfc_low */
212 unsigned char refrec_ctrl;
213 /* Last data to precharge minimum interval (tWR) */
214 unsigned char wrrec_mclk;
215 /* Activate-to-activate interval (tRRD) */
216 unsigned char acttoact_mclk;
217 /* Last write data pair to read command issue interval (tWTR) */
218 unsigned char wrtord_mclk;
220 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
221 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
222 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
225 * Translate CAS Latency to a DDR controller field value:
227 * CAS Lat DDR I DDR II Ctrl
228 * Clocks SPD Bit SPD Bit Value
229 * ------- ------- ------- -----
240 #if defined(CONFIG_FSL_DDR1)
241 caslat_ctrl = (cas_latency + 1) & 0x07;
242 #elif defined(CONFIG_FSL_DDR2)
243 caslat_ctrl = 2 * cas_latency - 1;
245 #error "Need CAS Latency help for DDR3 in fsl_ddr_sdram.c"
248 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
249 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
250 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
251 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
253 ddr->timing_cfg_1 = (0
254 | ((pretoact_mclk & 0x07) << 28)
255 | ((acttopre_mclk & 0x0F) << 24)
256 | ((acttorw_mclk & 0x7) << 20)
257 | ((caslat_ctrl & 0xF) << 16)
258 | ((refrec_ctrl & 0xF) << 12)
259 | ((wrrec_mclk & 0x07) << 8)
260 | ((acttoact_mclk & 0x07) << 4)
261 | ((wrtord_mclk & 0x07) << 0)
263 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
266 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
267 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
268 const memctl_options_t *popts,
269 const common_timing_params_t *common_dimm,
270 unsigned int cas_latency,
271 unsigned int additive_latency)
273 /* Additive latency */
274 unsigned char add_lat_mclk;
275 /* CAS-to-preamble override */
278 unsigned char wr_lat;
279 /* Read to precharge (tRTP) */
280 unsigned char rd_to_pre;
281 /* Write command to write data strobe timing adjustment */
282 unsigned char wr_data_delay;
283 /* Minimum CKE pulse width (tCKE) */
284 unsigned char cke_pls;
285 /* Window for four activates (tFAW) */
286 unsigned short four_act;
288 /* FIXME add check that this must be less than acttorw_mclk */
289 add_lat_mclk = additive_latency;
290 cpo = popts->cpo_override;
292 #if defined(CONFIG_FSL_DDR1)
294 * This is a lie. It should really be 1, but if it is
295 * set to 1, bits overlap into the old controller's
296 * otherwise unused ACSM field. If we leave it 0, then
297 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
300 #elif defined(CONFIG_FSL_DDR2)
301 wr_lat = cas_latency + additive_latency - 1;
303 #error "Fix WR_LAT for DDR3"
306 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
307 wr_data_delay = popts->write_data_delay;
308 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
309 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
311 ddr->timing_cfg_2 = (0
312 | ((add_lat_mclk & 0x7) << 28)
313 | ((cpo & 0x1f) << 23)
314 | ((wr_lat & 0x7) << 19)
315 | ((rd_to_pre & 0x7) << 13)
316 | ((wr_data_delay & 0x7) << 10)
317 | ((cke_pls & 0x7) << 6)
318 | ((four_act & 0x1f) << 0)
320 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
323 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
324 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
325 const memctl_options_t *popts,
326 const common_timing_params_t *common_dimm)
328 unsigned int mem_en; /* DDR SDRAM interface logic enable */
329 unsigned int sren; /* Self refresh enable (during sleep) */
330 unsigned int ecc_en; /* ECC enable. */
331 unsigned int rd_en; /* Registered DIMM enable */
332 unsigned int sdram_type; /* Type of SDRAM */
333 unsigned int dyn_pwr; /* Dynamic power management mode */
334 unsigned int dbw; /* DRAM dta bus width */
335 unsigned int eight_be; /* 8-beat burst enable */
336 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
337 unsigned int threeT_en; /* Enable 3T timing */
338 unsigned int twoT_en; /* Enable 2T timing */
339 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
340 unsigned int x32_en = 0; /* x32 enable */
341 unsigned int pchb8 = 0; /* precharge bit 8 enable */
342 unsigned int hse; /* Global half strength override */
343 unsigned int mem_halt = 0; /* memory controller halt */
344 unsigned int bi = 0; /* Bypass initialization */
347 sren = popts->self_refresh_in_sleep;
348 if (common_dimm->all_DIMMs_ECC_capable) {
349 /* Allow setting of ECC only if all DIMMs are ECC. */
350 ecc_en = popts->ECC_mode;
355 rd_en = (common_dimm->all_DIMMs_registered
356 && !common_dimm->all_DIMMs_unbuffered);
358 sdram_type = CONFIG_FSL_SDRAM_TYPE;
360 dyn_pwr = popts->dynamic_power;
361 dbw = popts->data_bus_width;
362 eight_be = 0; /* always 0 for DDR2 */
363 threeT_en = popts->threeT_en;
364 twoT_en = popts->twoT_en;
365 ba_intlv_ctl = popts->ba_intlv_ctl;
366 hse = popts->half_strength_driver_enable;
368 ddr->ddr_sdram_cfg = (0
369 | ((mem_en & 0x1) << 31)
370 | ((sren & 0x1) << 30)
371 | ((ecc_en & 0x1) << 29)
372 | ((rd_en & 0x1) << 28)
373 | ((sdram_type & 0x7) << 24)
374 | ((dyn_pwr & 0x1) << 21)
375 | ((dbw & 0x3) << 19)
376 | ((eight_be & 0x1) << 18)
377 | ((ncap & 0x1) << 17)
378 | ((threeT_en & 0x1) << 16)
379 | ((twoT_en & 0x1) << 15)
380 | ((ba_intlv_ctl & 0x7F) << 8)
381 | ((x32_en & 0x1) << 5)
382 | ((pchb8 & 0x1) << 4)
384 | ((mem_halt & 0x1) << 1)
387 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
390 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
391 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
392 const memctl_options_t *popts)
394 unsigned int frc_sr = 0; /* Force self refresh */
395 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
396 unsigned int dll_rst_dis; /* DLL reset disable */
397 unsigned int dqs_cfg; /* DQS configuration */
398 unsigned int odt_cfg; /* ODT configuration */
399 unsigned int num_pr; /* Number of posted refreshes */
400 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
401 unsigned int ap_en; /* Address Parity Enable */
402 unsigned int d_init; /* DRAM data initialization */
403 unsigned int rcw_en = 0; /* Register Control Word Enable */
404 unsigned int md_en = 0; /* Mirrored DIMM Enable */
406 dll_rst_dis = 1; /* Make this configurable */
407 dqs_cfg = popts->DQS_config;
408 if (popts->cs_local_opts[0].odt_rd_cfg
409 || popts->cs_local_opts[0].odt_wr_cfg) {
416 num_pr = 1; /* Make this configurable */
420 * {TIMING_CFG_1[PRETOACT]
421 * + [DDR_SDRAM_CFG_2[NUM_PR]
422 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
423 * << DDR_SDRAM_INTERVAL[REFINT]
426 obc_cfg = 0; /* Make this configurable? */
427 ap_en = 0; /* Make this configurable? */
429 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
430 /* Use the DDR controller to auto initialize memory. */
432 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
433 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
435 /* Memory will be initialized via DMA, or not at all. */
439 ddr->ddr_sdram_cfg_2 = (0
440 | ((frc_sr & 0x1) << 31)
441 | ((sr_ie & 0x1) << 30)
442 | ((dll_rst_dis & 0x1) << 29)
443 | ((dqs_cfg & 0x3) << 26)
444 | ((odt_cfg & 0x3) << 21)
445 | ((num_pr & 0xf) << 12)
446 | ((obc_cfg & 0x1) << 6)
447 | ((ap_en & 0x1) << 5)
448 | ((d_init & 0x1) << 4)
449 | ((rcw_en & 0x1) << 2)
450 | ((md_en & 0x1) << 0)
452 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
455 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
456 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
458 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
459 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
461 ddr->ddr_sdram_mode_2 = (0
462 | ((esdmode2 & 0xFFFF) << 16)
463 | ((esdmode3 & 0xFFFF) << 0)
465 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
468 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
469 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
470 const memctl_options_t *popts,
471 const common_timing_params_t *common_dimm)
473 unsigned int refint; /* Refresh interval */
474 unsigned int bstopre; /* Precharge interval */
476 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
478 bstopre = popts->bstopre;
480 /* refint field used 0x3FFF in earlier controllers */
481 ddr->ddr_sdram_interval = (0
482 | ((refint & 0xFFFF) << 16)
483 | ((bstopre & 0x3FFF) << 0)
485 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
488 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
489 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
490 const memctl_options_t *popts,
491 const common_timing_params_t *common_dimm,
492 unsigned int cas_latency,
493 unsigned int additive_latency)
495 unsigned short esdmode; /* Extended SDRAM mode */
496 unsigned short sdmode; /* SDRAM mode */
499 * FIXME: This ought to be pre-calculated in a
500 * technology-specific routine,
501 * e.g. compute_DDR2_mode_register(), and then the
502 * sdmode and esdmode passed in as part of common_dimm.
505 /* Extended Mode Register */
506 unsigned int mrs = 0; /* Mode Register Set */
507 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
508 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
509 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
510 unsigned int ocd = 0; /* 0x0=OCD not supported,
511 0x7=OCD default state */
513 unsigned int al; /* Posted CAS# additive latency (AL) */
514 unsigned int ods = 0; /* Output Drive Strength:
515 0 = Full strength (18ohm)
516 1 = Reduced strength (4ohm) */
517 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
518 1=Disable (Test/Debug) */
520 /* Mode Register (MR) */
521 unsigned int mr; /* Mode Register Definition */
522 unsigned int pd; /* Power-Down Mode */
523 unsigned int wr; /* Write Recovery */
524 unsigned int dll_res; /* DLL Reset */
525 unsigned int mode; /* Normal=0 or Test=1 */
526 unsigned int caslat = 0;/* CAS# latency */
527 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
529 unsigned int bl; /* BL: Burst Length */
531 #if defined(CONFIG_FSL_DDR2)
532 const unsigned int mclk_ps = get_memory_clk_period_ps();
535 rtt = fsl_ddr_get_rtt();
537 al = additive_latency;
540 | ((mrs & 0x3) << 14)
541 | ((outputs & 0x1) << 12)
542 | ((rdqs_en & 0x1) << 11)
543 | ((dqs_en & 0x1) << 10)
545 | ((rtt & 0x2) << 5) /* rtt field is split */
547 | ((rtt & 0x1) << 2) /* rtt field is split */
549 | ((dll_en & 0x1) << 0)
552 mr = 0; /* FIXME: CHECKME */
555 * 0 = Fast Exit (Normal)
556 * 1 = Slow Exit (Low Power)
560 #if defined(CONFIG_FSL_DDR1)
561 wr = 0; /* Historical */
562 #elif defined(CONFIG_FSL_DDR2)
563 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
565 #error "Write tWR_auto for DDR3"
570 #if defined(CONFIG_FSL_DDR1)
571 if (1 <= cas_latency && cas_latency <= 4) {
572 unsigned char mode_caslat_table[4] = {
573 0x5, /* 1.5 clocks */
574 0x2, /* 2.0 clocks */
575 0x6, /* 2.5 clocks */
578 caslat = mode_caslat_table[cas_latency - 1];
580 printf("Warning: unknown cas_latency %d\n", cas_latency);
582 #elif defined(CONFIG_FSL_DDR2)
583 caslat = cas_latency;
585 #error "Fix the mode CAS Latency for DDR3"
589 switch (popts->burst_length) {
597 printf("Error: invalid burst length of %u specified. "
598 " Defaulting to 4 beats.\n",
599 popts->burst_length);
608 | ((dll_res & 0x1) << 8)
609 | ((mode & 0x1) << 7)
610 | ((caslat & 0x7) << 4)
615 ddr->ddr_sdram_mode = (0
616 | ((esdmode & 0xFFFF) << 16)
617 | ((sdmode & 0xFFFF) << 0)
619 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
623 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
624 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
626 unsigned int init_value; /* Initialization value */
628 init_value = 0xDEADBEEF;
629 ddr->ddr_data_init = init_value;
633 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
634 * The old controller on the 8540/60 doesn't have this register.
635 * Hope it's OK to set it (to 0) anyway.
637 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
638 const memctl_options_t *popts)
640 unsigned int clk_adjust; /* Clock adjust */
642 clk_adjust = popts->clk_adjust;
643 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
646 /* DDR Initialization Address (DDR_INIT_ADDR) */
647 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
649 unsigned int init_addr = 0; /* Initialization address */
651 ddr->ddr_init_addr = init_addr;
654 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
655 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
657 unsigned int uia = 0; /* Use initialization address */
658 unsigned int init_ext_addr = 0; /* Initialization address */
660 ddr->ddr_init_ext_addr = (0
661 | ((uia & 0x1) << 31)
662 | (init_ext_addr & 0xF)
666 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
667 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
669 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
670 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
671 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
672 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
673 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
675 ddr->timing_cfg_4 = (0
676 | ((rwt & 0xf) << 28)
677 | ((wrt & 0xf) << 24)
678 | ((rrt & 0xf) << 20)
679 | ((wwt & 0xf) << 16)
682 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
685 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
686 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
688 unsigned int rodt_on = 0; /* Read to ODT on */
689 unsigned int rodt_off = 0; /* Read to ODT off */
690 unsigned int wodt_on = 0; /* Write to ODT on */
691 unsigned int wodt_off = 0; /* Write to ODT off */
693 ddr->timing_cfg_5 = (0
694 | ((rodt_on & 0xf) << 24)
695 | ((rodt_off & 0xf) << 20)
696 | ((wodt_on & 0xf) << 12)
697 | ((wodt_off & 0xf) << 8)
699 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
702 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
703 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr)
705 unsigned int zq_en = 0; /* ZQ Calibration Enable */
706 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
707 /* Normal Operation Full Calibration Time (tZQoper) */
708 unsigned int zqoper = 0;
709 /* Normal Operation Short Calibration Time (tZQCS) */
710 unsigned int zqcs = 0;
712 ddr->ddr_zq_cntl = (0
713 | ((zq_en & 0x1) << 31)
714 | ((zqinit & 0xF) << 24)
715 | ((zqoper & 0xF) << 16)
716 | ((zqcs & 0xF) << 8)
720 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
721 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
723 unsigned int wrlvl_en = 0; /* Write Leveling Enable */
725 * First DQS pulse rising edge after margining mode
726 * is programmed (tWL_MRD)
728 unsigned int wrlvl_mrd = 0;
729 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
730 unsigned int wrlvl_odten = 0;
731 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
732 unsigned int wrlvl_dqsen = 0;
733 /* WRLVL_SMPL: Write leveling sample time */
734 unsigned int wrlvl_smpl = 0;
735 /* WRLVL_WLR: Write leveling repeition time */
736 unsigned int wrlvl_wlr = 0;
737 /* WRLVL_START: Write leveling start time */
738 unsigned int wrlvl_start = 0;
740 ddr->ddr_wrlvl_cntl = (0
741 | ((wrlvl_en & 0x1) << 31)
742 | ((wrlvl_mrd & 0x7) << 24)
743 | ((wrlvl_odten & 0x7) << 20)
744 | ((wrlvl_dqsen & 0x7) << 16)
745 | ((wrlvl_smpl & 0xf) << 12)
746 | ((wrlvl_wlr & 0x7) << 8)
747 | ((wrlvl_start & 0xF) << 0)
751 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
752 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr)
754 unsigned int sr_it = 0; /* Self Refresh Idle Threshold */
756 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
759 /* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */
760 static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr)
762 /* Termination value during pre-drive conditioning */
763 unsigned int tvpd = 0;
764 unsigned int pd_en = 0; /* Pre-Drive Conditioning Enable */
765 unsigned int pdar = 0; /* Pre-Drive After Read */
766 unsigned int pdaw = 0; /* Pre-Drive After Write */
767 unsigned int pd_on = 0; /* Pre-Drive Conditioning On */
768 unsigned int pd_off = 0; /* Pre-Drive Conditioning Off */
770 ddr->ddr_pd_cntl = (0
771 | ((pd_en & 0x1) << 31)
772 | ((tvpd & 0x7) << 28)
773 | ((pdar & 0x7F) << 20)
774 | ((pdaw & 0x7F) << 12)
775 | ((pd_on & 0x1F) << 6)
776 | ((pd_off & 0x1F) << 0)
781 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
782 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
784 unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */
785 unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */
786 unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */
787 unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */
788 unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */
789 unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */
790 unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */
791 unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */
793 ddr->ddr_sdram_rcw_1 = (0
794 | ((rcw0 & 0xF) << 28)
795 | ((rcw1 & 0xF) << 24)
796 | ((rcw2 & 0xF) << 20)
797 | ((rcw3 & 0xF) << 16)
798 | ((rcw4 & 0xF) << 12)
799 | ((rcw5 & 0xF) << 8)
800 | ((rcw6 & 0xF) << 4)
801 | ((rcw7 & 0xF) << 0)
805 /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
806 static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
808 unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */
809 unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */
810 unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */
811 unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */
812 unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */
813 unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */
814 unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */
815 unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */
817 ddr->ddr_sdram_rcw_2 = (0
818 | ((rcw8 & 0xF) << 28)
819 | ((rcw9 & 0xF) << 24)
820 | ((rcw10 & 0xF) << 20)
821 | ((rcw11 & 0xF) << 16)
822 | ((rcw12 & 0xF) << 12)
823 | ((rcw13 & 0xF) << 8)
824 | ((rcw14 & 0xF) << 4)
825 | ((rcw15 & 0xF) << 0)
830 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
832 unsigned int res = 0;
835 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
836 * not set at the same time.
838 if (ddr->ddr_sdram_cfg & 0x10000000
839 && ddr->ddr_sdram_cfg & 0x00008000) {
840 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
841 " should not be set at the same time.\n");
849 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
850 fsl_ddr_cfg_regs_t *ddr,
851 const common_timing_params_t *common_dimm,
852 const dimm_params_t *dimm_params,
853 unsigned int dbw_cap_adj)
856 unsigned int cas_latency;
857 unsigned int additive_latency;
859 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
861 if (common_dimm == NULL) {
862 printf("Error: subset DIMM params struct null pointer\n");
867 * Process overrides first.
869 * FIXME: somehow add dereated caslat to this
871 cas_latency = (popts->cas_latency_override)
872 ? popts->cas_latency_override_value
873 : common_dimm->lowest_common_SPD_caslat;
875 additive_latency = (popts->additive_latency_override)
876 ? popts->additive_latency_override_value
877 : common_dimm->additive_latency;
879 /* Chip Select Memory Bounds (CSn_BNDS) */
880 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
884 if (popts->ba_intlv_ctl && (i > 0) &&
885 ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
886 /* Don't set up boundaries for other CS
887 * other than CS0, if bank interleaving
888 * is enabled and not CS2+CS3 interleaved.
893 if (dimm_params[i/2].n_ranks == 0) {
894 debug("Skipping setup of CS%u "
895 "because n_ranks on DIMM %u is 0\n", i, i/2);
898 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
900 * This works superbank 2CS
901 * There are 2 memory controllers configured
902 * identically, memory is interleaved between them,
903 * and each controller uses rank interleaving within
904 * itself. Therefore the starting and ending address
905 * on each controller is twice the amount present on
908 unsigned long long rank_density
909 = dimm_params[0].capacity;
910 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
912 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
914 * If memory interleaving between controllers is NOT
915 * enabled, the starting address for each memory
916 * controller is distinct. However, because rank
917 * interleaving is enabled, the starting and ending
918 * addresses of the total memory on that memory
919 * controller needs to be programmed into its
920 * respective CS0_BNDS.
922 unsigned long long rank_density
923 = dimm_params[i/2].rank_density;
924 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
925 case FSL_DDR_CS0_CS1_CS2_CS3:
926 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
929 sa = common_dimm->base_address;
930 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
932 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
933 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
934 * and CS2_CNDS need to be set.
937 sa = dimm_params[i/2].base_address;
938 ea = sa + (i * (rank_density >>
942 case FSL_DDR_CS0_CS1:
943 /* CS0+CS1 interleaving, CS0_CNDS needs
946 sa = common_dimm->base_address;
947 ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
949 case FSL_DDR_CS2_CS3:
950 /* CS2+CS3 interleaving*/
952 sa = dimm_params[i/2].base_address;
953 ea = sa + (2 * (rank_density >>
957 default: /* No bank(chip-select) interleaving */
961 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
963 * Only the rank on CS0 of each memory controller may
964 * be used if memory controller interleaving is used
965 * without rank interleaving within each memory
966 * controller. However, the ending address programmed
967 * into each CS0 must be the sum of the amount of
968 * memory in the two CS0 ranks.
971 unsigned long long rank_density
972 = dimm_params[0].rank_density;
973 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
977 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
979 * No rank interleaving and no memory controller
982 unsigned long long rank_density
983 = dimm_params[i/2].rank_density;
984 sa = dimm_params[i/2].base_address;
985 ea = sa + (rank_density >> dbw_cap_adj) - 1;
987 if ((dimm_params[i/2].n_ranks == 1)) {
988 /* Odd chip select, single-rank dimm */
992 /* Odd chip select, dual-rank DIMM */
993 sa += rank_density >> dbw_cap_adj;
994 ea += rank_density >> dbw_cap_adj;
1002 ddr->cs[i].bnds = (0
1003 | ((sa & 0xFFF) << 16) /* starting address MSB */
1004 | ((ea & 0xFFF) << 0) /* ending address MSB */
1007 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1008 set_csn_config(i, ddr, popts, dimm_params);
1009 set_csn_config_2(i, ddr);
1012 #if defined(CONFIG_FSL_DDR2)
1013 set_timing_cfg_0(ddr);
1016 set_timing_cfg_3(ddr, common_dimm);
1017 set_timing_cfg_1(ddr, common_dimm, cas_latency);
1018 set_timing_cfg_2(ddr, popts, common_dimm,
1019 cas_latency, additive_latency);
1021 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1023 set_ddr_sdram_cfg_2(ddr, popts);
1024 set_ddr_sdram_mode(ddr, popts, common_dimm,
1025 cas_latency, additive_latency);
1026 set_ddr_sdram_mode_2(ddr);
1027 set_ddr_sdram_interval(ddr, popts, common_dimm);
1028 set_ddr_data_init(ddr);
1029 set_ddr_sdram_clk_cntl(ddr, popts);
1030 set_ddr_init_addr(ddr);
1031 set_ddr_init_ext_addr(ddr);
1032 set_timing_cfg_4(ddr);
1033 set_timing_cfg_5(ddr);
1035 set_ddr_zq_cntl(ddr);
1036 set_ddr_wrlvl_cntl(ddr);
1038 set_ddr_pd_cntl(ddr);
1039 set_ddr_sr_cntr(ddr);
1041 set_ddr_sdram_rcw_1(ddr);
1042 set_ddr_sdram_rcw_2(ddr);
1044 return check_fsl_memctl_config_regs(ddr);