2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
16 #include <asm/fsl_ddr_sdram.h>
20 extern void fsl_ddr_set_lawbar(
21 const common_timing_params_t *memctl_common_params,
22 unsigned int memctl_interleaved,
23 unsigned int ctrl_num);
25 /* processor specific function */
26 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
27 unsigned int ctrl_num);
29 /* Board-specific functions defined in each board's ddr.c */
30 extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
31 unsigned int ctrl_num);
35 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
36 * - Same memory data bus width on all controllers
40 * The memory controller and associated documentation use confusing
41 * terminology when referring to the orgranization of DRAM.
43 * Here is a terminology translation table:
45 * memory controller/documention |industry |this code |signals
46 * -------------------------------|-----------|-----------|-----------------
47 * physical bank/bank |rank |rank |chip select (CS)
48 * logical bank/sub-bank |bank |bank |bank address (BA)
49 * page/row |row |page |row address
50 * ??? |column |column |column address
52 * The naming confusion is further exacerbated by the descriptions of the
53 * memory controller interleaving feature, where accesses are interleaved
54 * _BETWEEN_ two seperate memory controllers. This is configured only in
55 * CS0_CONFIG[INTLV_CTL] of each memory controller.
57 * memory controller documentation | number of chip selects
58 * | per memory controller supported
59 * --------------------------------|-----------------------------------------
60 * cache line interleaving | 1 (CS0 only)
61 * page interleaving | 1 (CS0 only)
62 * bank interleaving | 1 (CS0 only)
63 * superbank interleraving | depends on bank (chip select)
64 * | interleraving [rank interleaving]
65 * | mode used on every memory controller
67 * Even further confusing is the existence of the interleaving feature
68 * _WITHIN_ each memory controller. The feature is referred to in
69 * documentation as chip select interleaving or bank interleaving,
70 * although it is configured in the DDR_SDRAM_CFG field.
72 * Name of field | documentation name | this code
73 * -----------------------------|-----------------------|------------------
74 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
79 const char *step_string_tbl[] = {
81 "STEP_COMPUTE_DIMM_PARMS",
82 "STEP_COMPUTE_COMMON_PARMS",
84 "STEP_ASSIGN_ADDRESSES",
90 const char * step_to_string(unsigned int step) {
92 unsigned int s = __ilog2(step);
95 return step_string_tbl[7];
97 return step_string_tbl[s];
101 int step_assign_addresses(fsl_ddr_info_t *pinfo,
102 unsigned int dbw_cap_adj[],
103 unsigned int *memctl_interleaving,
104 unsigned int *rank_interleaving)
109 * If a reduced data width is requested, but the SPD
110 * specifies a physically wider device, adjust the
111 * computed dimm capacities accordingly before
112 * assigning addresses.
114 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
115 unsigned int found = 0;
117 switch (pinfo->memctl_opts[i].data_bus_width) {
120 printf("can't handle 16-bit mode yet\n");
125 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
127 dw = pinfo->dimm_params[i][j].data_width;
128 if (pinfo->dimm_params[i][j].n_ranks
129 && (dw == 72 || dw == 64)) {
131 * FIXME: can't really do it
132 * like this because this just
133 * further reduces the memory
149 printf("unexpected data bus width "
150 "specified controller %u\n", i);
156 * Check if all controllers are configured for memory
157 * controller interleaving.
160 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
161 if (pinfo->memctl_opts[i].memctl_interleaving) {
166 *memctl_interleaving = 1;
169 /* Check that all controllers are rank interleaving. */
171 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
172 if (pinfo->memctl_opts[i].ba_intlv_ctl) {
177 *rank_interleaving = 1;
180 if (*memctl_interleaving) {
182 phys_size_t total_mem_per_ctlr = 0;
185 * If interleaving between memory controllers,
186 * make each controller start at a base address
189 * Also, if bank interleaving (chip select
190 * interleaving) is enabled on each memory
191 * controller, CS0 needs to be programmed to
192 * cover the entire memory range on that memory
195 * Bank interleaving also implies that each
196 * addressed chip select is identical in size.
199 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
201 pinfo->common_timing_params[i].base_address =
203 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
204 unsigned long long cap
205 = pinfo->dimm_params[i][j].capacity;
207 pinfo->dimm_params[i][j].base_address = addr;
208 addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
209 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
212 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
215 * Simple linear assignment if memory
216 * controllers are not interleaved.
218 phys_size_t cur_memsize = 0;
219 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
220 phys_size_t total_mem_per_ctlr = 0;
221 pinfo->common_timing_params[i].base_address =
222 (phys_addr_t)cur_memsize;
223 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
224 /* Compute DIMM base addresses. */
225 unsigned long long cap =
226 pinfo->dimm_params[i][j].capacity;
228 pinfo->dimm_params[i][j].base_address =
229 (phys_addr_t)cur_memsize;
230 cur_memsize += cap >> dbw_cap_adj[i];
231 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
233 pinfo->common_timing_params[i].total_mem =
242 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
245 unsigned int all_controllers_memctl_interleaving = 0;
246 unsigned int all_controllers_rank_interleaving = 0;
247 phys_size_t total_mem = 0;
249 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
250 common_timing_params_t *timing_params = pinfo->common_timing_params;
252 /* data bus width capacity adjust shift amount */
253 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
255 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
256 dbw_capacity_adjust[i] = 0;
259 debug("starting at step %u (%s)\n",
260 start_step, step_to_string(start_step));
262 switch (start_step) {
264 /* STEP 1: Gather all DIMM SPD data */
265 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
266 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
269 case STEP_COMPUTE_DIMM_PARMS:
270 /* STEP 2: Compute DIMM parameters from SPD data */
272 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
273 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
275 generic_spd_eeprom_t *spd =
276 &(pinfo->spd_installed_dimms[i][j]);
277 dimm_params_t *pdimm =
278 &(pinfo->dimm_params[i][j]);
280 retval = compute_dimm_parameters(spd, pdimm, i);
282 printf("Error: compute_dimm_parameters"
283 " non-zero returned FATAL value "
284 "for memctl=%u dimm=%u\n", i, j);
288 debug("Warning: compute_dimm_parameters"
289 " non-zero return value for memctl=%u "
295 case STEP_COMPUTE_COMMON_PARMS:
297 * STEP 3: Compute a common set of timing parameters
298 * suitable for all of the DIMMs on each memory controller
300 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
301 debug("Computing lowest common DIMM"
302 " parameters for memctl=%u\n", i);
303 compute_lowest_common_dimm_parameters(
304 pinfo->dimm_params[i],
306 CONFIG_DIMM_SLOTS_PER_CTLR);
309 case STEP_GATHER_OPTS:
310 /* STEP 4: Gather configuration requirements from user */
311 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
312 debug("Reloading memory controller "
313 "configuration options for memctl=%u\n", i);
315 * This "reloads" the memory controller options
316 * to defaults. If the user "edits" an option,
317 * next_step points to the step after this,
318 * which is currently STEP_ASSIGN_ADDRESSES.
320 populate_memctl_options(
321 timing_params[i].all_DIMMs_registered,
322 &pinfo->memctl_opts[i], i);
325 case STEP_ASSIGN_ADDRESSES:
326 /* STEP 5: Assign addresses to chip selects */
327 step_assign_addresses(pinfo,
329 &all_controllers_memctl_interleaving,
330 &all_controllers_rank_interleaving);
332 case STEP_COMPUTE_REGS:
333 /* STEP 6: compute controller register values */
334 debug("FSL Memory ctrl cg register computation\n");
335 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
336 if (timing_params[i].ndimms_present == 0) {
337 memset(&ddr_reg[i], 0,
338 sizeof(fsl_ddr_cfg_regs_t));
342 compute_fsl_memctl_config_regs(
343 &pinfo->memctl_opts[i],
344 &ddr_reg[i], &timing_params[i],
345 pinfo->dimm_params[i],
346 dbw_capacity_adjust[i]);
353 /* Compute the total amount of memory. */
356 * If bank interleaving but NOT memory controller interleaving
357 * CS_BNDS describe the quantity of memory on each memory
358 * controller, so the total is the sum across.
360 if (!all_controllers_memctl_interleaving
361 && all_controllers_rank_interleaving) {
363 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
364 total_mem += timing_params[i].total_mem;
369 * Compute the amount of memory available just by
370 * looking for the highest valid CSn_BNDS value.
371 * This allows us to also experiment with using
372 * only CS0 when using dual-rank DIMMs.
374 unsigned int max_end = 0;
376 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
377 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
378 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
379 if (reg->cs[j].config & 0x80000000) {
381 end = reg->cs[j].bnds & 0xFFF;
389 #if !defined(CONFIG_PHYS_64BIT)
390 /* Check for 4G or more with a 32-bit phys_addr_t. Bad. */
391 if (max_end >= 0xff) {
392 printf("This U-Boot only supports < 4G of DDR\n");
393 printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
394 return 0; /* Ensure DDR setup failure. */
398 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
406 * fsl_ddr_sdram() -- this is the main function to be called by
407 * initdram() in the board file.
409 * It returns amount of memory configured in bytes.
411 phys_size_t fsl_ddr_sdram(void)
414 unsigned int memctl_interleaved;
415 phys_size_t total_memory;
418 /* Reset info structure. */
419 memset(&info, 0, sizeof(fsl_ddr_info_t));
421 /* Compute it once normally. */
422 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD);
424 /* Check for memory controller interleaving. */
425 memctl_interleaved = 0;
426 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
427 memctl_interleaved +=
428 info.memctl_opts[i].memctl_interleaving;
431 if (memctl_interleaved) {
432 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
433 debug("memctl interleaving\n");
435 * Change the meaning of memctl_interleaved
438 memctl_interleaved = 1;
440 printf("Error: memctl interleaving not "
441 "properly configured on all controllers\n");
446 /* Program configuration registers. */
447 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
448 debug("Programming controller %u\n", i);
449 if (info.common_timing_params[i].ndimms_present == 0) {
450 debug("No dimms present on controller %u; "
451 "skipping programming\n", i);
455 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
458 if (memctl_interleaved) {
459 const unsigned int ctrl_num = 0;
461 /* Only set LAWBAR1 if memory controller interleaving is on. */
462 fsl_ddr_set_lawbar(&info.common_timing_params[0],
463 memctl_interleaved, ctrl_num);
466 * Memory controller interleaving is NOT on;
467 * set each lawbar individually.
469 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
470 fsl_ddr_set_lawbar(&info.common_timing_params[i],
475 debug("total_memory = %llu\n", (u64)total_memory);