1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*/
73 #include <asm/processor.h>
76 #include <405gp_enet.h>
83 #if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
85 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
86 #define PHY_AUTONEGOTIATE_TIMEOUT 2000 /* 2000 ms autonegotiate timeout */
90 * Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
91 * These both variables are used to define the same thing!
92 * #define NUM_RX_BUFF 4
94 #define NUM_RX_BUFF PKTBUFSRX
96 /* Ethernet Transmit and Receive Buffers */
98 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
99 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
101 #define ENET_MAX_MTU PKTSIZE
102 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
104 static char *txbuf_ptr;
106 /* define the number of channels implemented */
110 /*-----------------------------------------------------------------------------+
111 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
112 * Interrupt Controller).
113 *-----------------------------------------------------------------------------*/
114 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
115 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
116 #define EMAC_UIC_DEF UIC_ENET
118 /*-----------------------------------------------------------------------------+
119 * Global variables. TX and RX descriptors and buffers.
120 *-----------------------------------------------------------------------------*/
121 static volatile mal_desc_t *tx;
122 static volatile mal_desc_t *rx;
123 static mal_desc_t *alloc_tx_buf = NULL;
124 static mal_desc_t *alloc_rx_buf = NULL;
127 static unsigned long emac_ier;
128 static unsigned long mal_ier;
131 /* Statistic Areas */
132 #define MAX_ERR_LOG 10
140 static struct stats { /* Statistic Block */
141 struct emac_stats emac;
143 short tx_err_log[MAX_ERR_LOG];
144 short rx_err_log[MAX_ERR_LOG];
147 static int first_init = 0;
149 static int tx_err_index = 0; /* Transmit Error Index for tx_err_log */
150 static int rx_err_index = 0; /* Receive Error Index for rx_err_log */
152 static int rx_slot = 0; /* MAL Receive Slot */
153 static int rx_i_index = 0; /* Receive Interrupt Queue Index */
154 static int rx_u_index = 0; /* Receive User Queue Index */
155 static int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
157 static int tx_slot = 0; /* MAL Transmit Slot */
158 static int tx_i_index = 0; /* Transmit Interrupt Queue Index */
159 static int tx_u_index = 0; /* Transmit User Queue Index */
160 static int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
162 #undef INFO_405_ENET 1
164 static int packetSent = 0;
165 static int packetReceived = 0;
166 static int packetHandled = 0;
169 static char emac_hwd_addr[ENET_ADDR_LENGTH];
171 static bd_t *bis_save = NULL; /* for eth_init upon mal error */
173 static int is_receiving = 0; /* sync with eth interrupt */
174 static int print_speed = 1; /* print speed message upon start */
176 static void enet_rcv (unsigned long malisr);
178 /*-----------------------------------------------------------------------------+
179 * Prototypes and externals.
180 *-----------------------------------------------------------------------------*/
181 void mal_err (unsigned long isr, unsigned long uic, unsigned long mal_def,
182 unsigned long mal_errr);
183 void emac_err (unsigned long isr);
188 mtdcr (malier, 0x00000000); /* disable mal interrupts */
189 out32 (EMAC_IER, 0x00000000); /* disable emac interrupts */
192 mtdcr (malmcr, MAL_CR_MMSR);
195 while (mfdcr (malmcr) & MAL_CR_MMSR) {
199 out32 (EMAC_M0, EMAC_M0_SRST);
201 print_speed = 1; /* print speed message again next time */
205 int eth_init (bd_t * bis)
211 unsigned long duplex;
213 unsigned short reg_short;
216 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
221 * packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
222 * In the most cases packetHandled = packetReceived, but it
223 * is possible that new packets (without relationship with
224 * current transfer) have got the time to arrived before
225 * netloop calls eth_halt
227 printf ("About preceeding transfer:\n"
228 "- Sent packet number %d\n"
229 "- Received packet number %d\n"
230 "- Handled packet number %d\n",
231 packetSent, packetReceived, packetHandled);
238 mtdcr (malmcr, MAL_CR_MMSR);
240 while (mfdcr (malmcr) & MAL_CR_MMSR) {
243 tx_err_index = 0; /* Transmit Error Index for tx_err_log */
244 rx_err_index = 0; /* Receive Error Index for rx_err_log */
246 rx_slot = 0; /* MAL Receive Slot */
247 rx_i_index = 0; /* Receive Interrupt Queue Index */
248 rx_u_index = 0; /* Receive User Queue Index */
250 tx_slot = 0; /* MAL Transmit Slot */
251 tx_i_index = 0; /* Transmit Interrupt Queue Index */
252 tx_u_index = 0; /* Transmit User Queue Index */
254 #if defined(CONFIG_440)
256 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
257 #endif /* CONFIG_440 */
260 out32 (EMAC_M0, EMAC_M0_SRST);
262 /* wait for PHY to complete auto negotiation */
264 #ifndef CONFIG_CS8952_PHY
265 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, ®_short);
268 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
270 if ((reg_short & PHY_BMSR_AUTN_ABLE)
271 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
272 puts ("Waiting for PHY auto negotiation to complete");
274 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
275 if ((i++ % 100) == 0)
277 udelay (10000); /* 10 ms */
278 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, ®_short);
283 if (i * 10 > PHY_AUTONEGOTIATE_TIMEOUT) {
284 puts (" TIMEOUT !\n");
289 udelay (500000); /* another 500 ms (results in faster booting) */
292 speed = miiphy_speed (CONFIG_PHY_ADDR);
293 duplex = miiphy_duplex (CONFIG_PHY_ADDR);
296 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
297 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
300 /* set the Mal configuration reg */
301 #if defined(CONFIG_440)
302 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
303 if( get_pvr() == PVR_440GP_RB )
304 mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
307 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
310 /* Free "old" buffers */
311 if (alloc_tx_buf) free(alloc_tx_buf);
312 if (alloc_rx_buf) free(alloc_rx_buf);
315 * Malloc MAL buffer desciptors, make sure they are
316 * aligned on cache line boundary size
317 * (401/403/IOP480 = 16, 405 = 32)
318 * and doesn't cross cache block boundaries.
320 alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
321 ((2 * CFG_CACHELINE_SIZE) - 2));
322 if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
323 tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
324 ((int)alloc_tx_buf & CACHELINE_MASK));
329 alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
330 ((2 * CFG_CACHELINE_SIZE) - 2));
331 if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
332 rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
333 ((int)alloc_rx_buf & CACHELINE_MASK));
338 for (i = 0; i < NUM_TX_BUFF; i++) {
342 txbuf_ptr = (char *) malloc (ENET_MAX_MTU_ALIGNED);
343 tx[i].data_ptr = txbuf_ptr;
344 if ((NUM_TX_BUFF - 1) == i)
345 tx[i].ctrl |= MAL_TX_CTRL_WRAP;
348 printf ("TX_BUFF %d @ 0x%08lx\n", i, (ulong) tx[i].data_ptr);
352 for (i = 0; i < NUM_RX_BUFF; i++) {
355 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
356 rx[i].data_ptr = (char *) NetRxPackets[i];
357 if ((NUM_RX_BUFF - 1) == i)
358 rx[i].ctrl |= MAL_RX_CTRL_WRAP;
359 rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
362 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
366 memcpy (emac_hwd_addr, bis->bi_enetaddr, ENET_ADDR_LENGTH);
370 reg |= emac_hwd_addr[0]; /* set high address */
372 reg |= emac_hwd_addr[1];
374 out32 (EMAC_IAH, reg);
377 reg |= emac_hwd_addr[2]; /* set low address */
379 reg |= emac_hwd_addr[3];
381 reg |= emac_hwd_addr[4];
383 reg |= emac_hwd_addr[5];
385 out32 (EMAC_IAL, reg);
387 /* setup MAL tx & rx channel pointers */
388 mtdcr (maltxctp0r, tx);
389 mtdcr (malrxctp0r, rx);
391 /* Reset transmit and receive channels */
392 mtdcr (malrxcarr, 0x80000000); /* 2 channels */
393 mtdcr (maltxcarr, 0x80000000); /* 2 channels */
395 /* Enable MAL transmit and receive channels */
396 mtdcr (maltxcasr, 0x80000000); /* 1 channel */
397 mtdcr (malrxcasr, 0x80000000); /* 1 channel */
399 /* set RX buffer size */
400 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
402 /* set transmit enable & receive enable */
403 out32 (EMAC_M0, EMAC_M0_TXE | EMAC_M0_RXE);
405 /* set receive fifo to 4k and tx fifo to 2k */
406 mode_reg = EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
409 if (speed == _100BASET)
410 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
412 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
414 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
416 out32 (EMAC_M1, mode_reg);
418 /* Enable broadcast and indvidual address */
419 out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
420 /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
422 /* we probably need to set the tx mode1 reg? maybe at tx time */
424 /* set transmit request threshold register */
425 out32 (EMAC_TRTR, 0x18000000); /* 256 byte threshold */
427 /* set receive low/high water mark register */
428 #if defined(CONFIG_440)
429 /* 440GP has a 64 byte burst length */
430 out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
431 out32 (EMAC_TXM1, 0xf8640000);
432 #else /* CONFIG_440 */
433 /* 405s have a 16 byte burst length */
434 out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
435 #endif /* CONFIG_440 */
438 out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
440 if (first_init == 0) {
442 * Connect interrupt service routines
444 irq_install_handler (VECNUM_EWU0, (interrupt_handler_t *) enetInt, NULL);
445 irq_install_handler (VECNUM_MS, (interrupt_handler_t *) enetInt, NULL);
446 irq_install_handler (VECNUM_MTE, (interrupt_handler_t *) enetInt, NULL);
447 irq_install_handler (VECNUM_MRE, (interrupt_handler_t *) enetInt, NULL);
448 irq_install_handler (VECNUM_TXDE, (interrupt_handler_t *) enetInt, NULL);
449 irq_install_handler (VECNUM_RXDE, (interrupt_handler_t *) enetInt, NULL);
450 irq_install_handler (VECNUM_ETH0, (interrupt_handler_t *) enetInt, NULL);
453 /* set up interrupt handler */
454 /* setup interrupt controler to take interrupts from the MAL &
456 mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
457 mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
459 /* set the MAL IER ??? names may change with new spec ??? */
460 mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE |
462 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
463 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
464 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
465 mtdcr (malier, mal_ier);
468 emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
469 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
470 if (speed == _100BASET)
471 emac_ier = emac_ier | EMAC_ISR_SYE;
473 out32 (EMAC_ISR, 0xffffffff); /* clear pending interrupts */
474 out32 (EMAC_IER, emac_ier);
476 mtmsr (msr); /* enable interrupts again */
485 int eth_send (volatile void *ptr, int len)
487 struct enet_frame *ef_ptr;
488 ulong time_start, time_now;
489 unsigned long temp_txm0;
491 ef_ptr = (struct enet_frame *) ptr;
493 /*-----------------------------------------------------------------------+
494 * Copy in our address into the frame.
495 *-----------------------------------------------------------------------*/
496 (void) memcpy (ef_ptr->source_addr, emac_hwd_addr, ENET_ADDR_LENGTH);
498 /*-----------------------------------------------------------------------+
499 * If frame is too long or too short, modify length.
500 *-----------------------------------------------------------------------*/
501 if (len > ENET_MAX_MTU)
504 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
505 memcpy ((void *) txbuf_ptr, (const void *) ptr, len);
507 /*-----------------------------------------------------------------------+
508 * set TX Buffer busy, and send it
509 *-----------------------------------------------------------------------*/
510 tx[tx_slot].ctrl = (MAL_TX_CTRL_LAST |
511 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
512 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
513 if ((NUM_TX_BUFF - 1) == tx_slot)
514 tx[tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
516 tx[tx_slot].data_len = (short) len;
517 tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
519 __asm__ volatile ("eieio");
520 out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
525 /*-----------------------------------------------------------------------+
526 * poll unitl the packet is sent and then make sure it is OK
527 *-----------------------------------------------------------------------*/
528 time_start = get_timer (0);
530 temp_txm0 = in32 (EMAC_TXM0);
531 /* loop until either TINT turns on or 3 seconds elapse */
532 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
533 /* transmit is done, so now check for errors
534 * If there is an error, an interrupt should
535 * happen when we return
537 time_now = get_timer (0);
538 if ((time_now - time_start) > 3000) {
548 #if defined(CONFIG_440)
549 /*-----------------------------------------------------------------------------+
551 | EnetInt is the interrupt handler. It will determine the
552 | cause of the interrupt and call the apporpriate servive
554 +-----------------------------------------------------------------------------*/
558 int rc = -1; /* default to not us */
559 unsigned long mal_isr;
560 unsigned long emac_isr = 0;
561 unsigned long mal_rx_eob;
562 unsigned long my_uic0msr, my_uic1msr;
564 /* enter loop that stays in interrupt code until nothing to service */
568 my_uic0msr = mfdcr (uic0msr);
569 my_uic1msr = mfdcr (uic1msr);
571 if (!(my_uic0msr & UIC_MRE)
572 && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
577 /* get and clear controller status interrupts */
578 /* look at Mal and EMAC interrupts */
579 if ((my_uic0msr & UIC_MRE)
580 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
581 /* we have a MAL interrupt */
582 mal_isr = mfdcr (malesr);
583 /* look for mal error */
584 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
585 mal_err (mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
590 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
591 emac_isr = in32 (EMAC_ISR);
592 if ((emac_ier & emac_isr) != 0) {
598 if ((emac_ier & emac_isr)
599 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
600 mtdcr (uic0sr, UIC_MRE); /* Clear */
601 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
602 return (rc); /* we had errors so get out */
605 /* handle MAL RX EOB interupt from a receive */
606 /* check for EOB on valid channels */
607 if (my_uic0msr & UIC_MRE) {
608 mal_rx_eob = mfdcr (malrxeobisr);
609 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
611 mtdcr(malrxeobisr, mal_rx_eob); */
613 /* indicate that we serviced an interrupt */
618 mtdcr (uic0sr, UIC_MRE); /* Clear */
619 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
624 #else /* CONFIG_440 */
625 /*-----------------------------------------------------------------------------+
627 * EnetInt is the interrupt handler. It will determine the
628 * cause of the interrupt and call the apporpriate servive
630 *-----------------------------------------------------------------------------*/
634 int rc = -1; /* default to not us */
635 unsigned long mal_isr;
636 unsigned long emac_isr = 0;
637 unsigned long mal_rx_eob;
638 unsigned long my_uicmsr;
640 /* enter loop that stays in interrupt code until nothing to service */
644 my_uicmsr = mfdcr (uicmsr);
645 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
650 /* get and clear controller status interrupts */
651 /* look at Mal and EMAC interrupts */
652 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
653 mal_isr = mfdcr (malesr);
654 /* look for mal error */
655 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
656 mal_err (mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
661 if ((EMAC_UIC_DEF & my_uicmsr) != 0) { /* look for EMAC errors */
662 emac_isr = in32 (EMAC_ISR);
663 if ((emac_ier & emac_isr) != 0) {
669 if (((emac_ier & emac_isr) != 0) | ((MAL_UIC_ERR & my_uicmsr) != 0)) {
670 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
671 return (rc); /* we had errors so get out */
675 /* handle MAL RX EOB interupt from a receive */
676 /* check for EOB on valid channels */
677 if ((my_uicmsr & UIC_MAL_RXEOB) != 0) {
678 mal_rx_eob = mfdcr (malrxeobisr);
679 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
681 mtdcr(malrxeobisr, mal_rx_eob); */
683 /* indicate that we serviced an interrupt */
688 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
694 #endif /* CONFIG_440 */
696 /*-----------------------------------------------------------------------------+
698 *-----------------------------------------------------------------------------*/
699 void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
700 unsigned long mal_errr)
702 mtdcr (malesr, isr); /* clear interrupt */
704 /* clear DE interrupt */
705 mtdcr (maltxdeir, 0xC0000000);
706 mtdcr (malrxdeir, 0x80000000);
709 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
710 isr, uic, maldef, mal_errr);
714 * MAL error is RX DE error (out of rx buffers)! This is OK here, upon
715 * many incoming packets with only 4 rx buffers.
717 printf ("M"); /* just to see something upon mal error */
721 eth_init (bis_save); /* start again... */
724 /*-----------------------------------------------------------------------------+
726 *-----------------------------------------------------------------------------*/
727 void emac_err (unsigned long isr)
729 printf ("EMAC error occured.... ISR = %lx\n", isr);
730 out32 (EMAC_ISR, isr);
733 /*-----------------------------------------------------------------------------+
734 * enet_rcv() handles the ethernet receive data
735 *-----------------------------------------------------------------------------*/
736 static void enet_rcv (unsigned long malisr)
738 struct enet_frame *ef_ptr;
739 unsigned long data_len;
740 unsigned long rx_eob_isr;
746 rx_eob_isr = mfdcr (malrxeobisr);
747 if ((0x80000000 >> (EMAC_RXCHL - 1)) & rx_eob_isr) {
749 mtdcr (malrxeobisr, rx_eob_isr);
752 while (1) { /* do all */
755 if ((MAL_RX_CTRL_EMPTY & rx[i].ctrl)
756 || (loop_count >= NUM_RX_BUFF))
760 if (NUM_RX_BUFF == rx_slot)
763 data_len = (unsigned long) rx[i].data_len; /* Get len */
765 if (data_len > ENET_MAX_MTU) /* Check len */
768 if (EMAC_RX_ERRORS & rx[i].ctrl) { /* Check Errors */
770 stats.rx_err_log[rx_err_index] = rx[i].ctrl;
772 if (rx_err_index == MAX_ERR_LOG)
775 } /* data_len < max mtu */
777 if (!data_len) { /* no data */
778 rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
780 stats.emac.data_len_err++; /* Error at Rx */
785 /* Check if user has already eaten buffer */
786 /* if not => ERROR */
787 else if (rx_ready[rx_i_index] != -1) {
789 printf ("ERROR : Receive buffers are full!\n");
792 stats.emac.rx_frames++;
793 stats.emac.rx += data_len;
794 ef_ptr = (struct enet_frame *) rx[i].data_ptr;
801 rx_ready[rx_i_index] = i;
803 if (NUM_RX_BUFF == rx_i_index)
806 /* printf("X"); /|* test-only *|/ */
809 * free receive buffer only when
810 * buffer has been handled (eth_rx)
811 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
815 } /* if EMACK_RXCHL */
825 is_receiving = 1; /* tell driver */
829 * use ring buffer and
830 * get index from rx buffer desciptor queue
832 user_index = rx_ready[rx_u_index];
833 if (user_index == -1) {
835 break; /* nothing received - leave for() loop */
839 mtmsr (msr & ~(MSR_EE));
841 length = rx[user_index].data_len;
843 /* Pass the packet up to the protocol layers. */
844 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
845 /* NetReceive(NetRxPackets[i], length); */
846 NetReceive (NetRxPackets[user_index], length - 4);
847 /* Free Recv Buffer */
848 rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
849 /* Free rx buffer descriptor queue */
850 rx_ready[rx_u_index] = -1;
852 if (NUM_RX_BUFF == rx_u_index)
859 mtmsr (msr); /* Enable IRQ's */
862 is_receiving = 0; /* tell driver */
867 #endif /* CONFIG_405GP */