1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*----------------------------------------------------------------------------+
23 * File Name: 405gp_pci.c
25 * Function: Initialization code for the 405GP PCI Configuration regs.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 09-Sep-98 Created MCG
34 * 02-Nov-98 Removed External arbiter selected message JWB
35 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
36 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
37 * from (0 to n) to (1 to n).
38 * 17-May-99 Port to Walnut JWB
39 * 17-Jun-99 Updated for VGA support JWB
40 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
41 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
42 * target latency timer values are not supported).
43 * Should be fixed in pass 2.
44 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
45 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
46 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
47 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
48 * really required after a reset since PMMxMAs are already
49 * disabled but is a good practice nonetheless. JWB
50 * 12-Jun-01 stefan.roese@esd-electronics.com
51 * - PCI host/adapter handling reworked
52 * 09-Jul-01 stefan.roese@esd-electronics.com
53 * - PCI host now configures from device 0 (not 1) to max_dev,
54 * (host configures itself)
55 * - On CPCI-405 pci base address and size is generated from
56 * SDRAM and FLASH size (CFG regs not used anymore)
57 * - Some minor changes for CPCI-405-A (adapter version)
58 * 14-Sep-01 stefan.roese@esd-electronics.com
59 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
60 * 28-Sep-01 stefan.roese@esd-electronics.com
61 * - Changed pci master configuration for linux compatibility
62 * (no need for bios_fixup() anymore)
63 * 26-Feb-02 stefan.roese@esd-electronics.com
64 * - Bug fixed in pci configuration (Andrew May)
65 * - Removed pci class code init for CPCI405 board
66 * 15-May-02 stefan.roese@esd-electronics.com
67 * - New vga device handling
68 * 29-May-02 stefan.roese@esd-electronics.com
69 * - PCI class code init added (if defined)
70 *----------------------------------------------------------------------------*/
74 #if !defined(CONFIG_440)
75 #include <405gp_pci.h>
77 #include <asm/processor.h>
80 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
86 /*-----------------------------------------------------------------------------+
87 * pci_init. Initializes the 405GP PCI Configuration regs.
88 *-----------------------------------------------------------------------------*/
89 void pci_405gp_init(struct pci_controller *hose)
91 DECLARE_GLOBAL_DATA_PTR;
96 unsigned short temp_short;
97 unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
98 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
99 unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
100 unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
102 unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
103 unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
105 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
106 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
107 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
108 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
109 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
111 unsigned long pmmla[3] = {0x80000000, 0,0};
112 unsigned long pmmma[3] = {0xC0000001, 0,0};
113 unsigned long pmmpcila[3] = {0x80000000, 0,0};
114 unsigned long pmmpciha[3] = {0x00000000, 0,0};
116 #ifdef CONFIG_PCI_PNP
117 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
125 hose->first_busno = 0;
126 hose->last_busno = 0xff;
128 /* ISA/PCI I/O space */
129 pci_set_region(hose->regions + reg_num++,
136 pci_set_region(hose->regions + reg_num++,
148 if (!i) hose->pci_fb = hose->regions + reg_num;
150 pci_set_region(hose->regions + reg_num++,
151 ptmpcila[i], ptmla[i],
152 ~(ptmms[i] & 0xfffff000) + 1,
157 /* PCI memory spaces */
161 pci_set_region(hose->regions + reg_num++,
162 pmmpcila[i], pmmla[i],
163 ~(pmmma[i] & 0xfffff000) + 1,
167 hose->region_count = reg_num;
169 pci_setup_indirect(hose,
174 pciauto_region_init(hose->pci_fb);
176 pci_register_hose(hose);
178 /*--------------------------------------------------------------------------+
179 * 405GP PCI Master configuration.
180 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
181 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
182 * Use byte reversed out routines to handle endianess.
183 *--------------------------------------------------------------------------*/
184 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
185 out32r(PMM0LA, pmmla[0]);
186 out32r(PMM0PCILA, pmmpcila[0]);
187 out32r(PMM0PCIHA, pmmpciha[0]);
188 out32r(PMM0MA, pmmma[0]);
190 /*--------------------------------------------------------------------------+
191 * PMM1 is not used. Initialize them to zero.
192 *--------------------------------------------------------------------------*/
193 out32r(PMM1MA, (pmmma[1]&~0x1));
194 out32r(PMM1LA, pmmla[1]);
195 out32r(PMM1PCILA, pmmpcila[1]);
196 out32r(PMM1PCIHA, pmmpciha[1]);
197 out32r(PMM1MA, pmmma[1]);
199 /*--------------------------------------------------------------------------+
200 * PMM2 is not used. Initialize them to zero.
201 *--------------------------------------------------------------------------*/
202 out32r(PMM2MA, (pmmma[2]&~0x1));
203 out32r(PMM2LA, pmmla[2]);
204 out32r(PMM2PCILA, pmmpcila[2]);
205 out32r(PMM2PCIHA, pmmpciha[2]);
206 out32r(PMM2MA, pmmma[2]);
208 /*--------------------------------------------------------------------------+
209 * 405GP PCI Target configuration. (PTM1)
210 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
211 *--------------------------------------------------------------------------*/
212 out32r(PTM1LA, ptmla[0]); /* insert address */
213 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
214 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
216 /*--------------------------------------------------------------------------+
217 * 405GP PCI Target configuration. (PTM2)
218 *--------------------------------------------------------------------------*/
219 out32r(PTM2LA, ptmla[1]); /* insert address */
220 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
224 out32r(PTM2MS, 0x00000001); /* set enable bit */
225 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
226 out32r(PTM2MS, 0x00000000); /* disable */
230 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
234 * Insert Subsystem Vendor and Device ID
236 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
237 #ifdef CONFIG_CPCI405
238 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
239 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
241 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
243 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
249 #ifdef CFG_PCI_CLASSCODE
250 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
251 #endif /* CFG_PCI_CLASSCODE */
253 /*--------------------------------------------------------------------------+
254 * If PCI speed = 66Mhz, set 66Mhz capable bit.
255 *--------------------------------------------------------------------------*/
256 if (bd->bi_pci_busfreq >= 66000000) {
257 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
258 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
261 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
262 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
263 if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
264 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
267 /*--------------------------------------------------------------------------+
268 * Write the 405GP PCI Configuration regs.
269 * Enable 405GP to be a master on the PCI bus (PMM).
270 * Enable 405GP to act as a PCI memory target (PTM).
271 *--------------------------------------------------------------------------*/
272 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
273 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
274 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
278 #if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
279 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
283 * Set HCE bit (Host Configuration Enabled)
285 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
286 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
288 #ifdef CONFIG_PCI_PNP
289 /*--------------------------------------------------------------------------+
290 * Scan the PCI bus and configure devices found.
291 *--------------------------------------------------------------------------*/
292 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
293 if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
294 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
297 #ifdef CONFIG_PCI_SCAN_SHOW
298 printf("PCI: Bus Dev VenId DevId Class Int\n");
301 hose->last_busno = pci_hose_scan(hose);
303 #endif /* CONFIG_PCI_PNP */
308 * drivers/pci.c skips every host bridge but the 405GP since it could
309 * be set as an Adapter.
311 * I (Andrew May) don't know what we should do here, but I don't want
312 * the auto setup of a PCI device disabling what is done pci_405gp_init
313 * as has happened before.
315 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
316 struct pci_config_table *entry)
319 printf("405gp_setup_bridge\n");
327 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
329 unsigned char int_line = 0xff;
332 * Write pci interrupt line register (cpci405 specific)
334 switch (PCI_DEV(dev) & 0x03)
350 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
353 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
354 struct pci_config_table *entry)
356 unsigned int cmdstat = 0;
358 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
360 /* always enable io space on vga boards */
361 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
362 cmdstat |= PCI_COMMAND_IO;
363 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
366 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
369 *As is these functs get called out of flash Not a horrible
370 *thing, but something to keep in mind. (no statics?)
372 static struct pci_config_table pci_405gp_config_table[] = {
373 /*if VendID is 0 it terminates the table search (ie Walnut)*/
374 #ifdef CFG_PCI_SUBSYS_VENDORID
375 {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
376 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
378 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
379 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
381 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
382 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
387 static struct pci_controller hose = {
388 fixup_irq: pci_405gp_fixup_irq,
389 config_table: pci_405gp_config_table,
392 void pci_init_board(void)
394 /*we want the ptrs to RAM not flash (ie don't use init list)*/
395 hose.fixup_irq = pci_405gp_fixup_irq;
396 hose.config_table = pci_405gp_config_table;
397 pci_405gp_init(&hose);
402 #endif /* CONFIG_PCI */
404 #endif /* CONFIG_405GP */
406 /*-----------------------------------------------------------------------------+
408 *-----------------------------------------------------------------------------*/
409 #if defined(CONFIG_440) && defined(CONFIG_PCI)
411 static struct pci_controller ppc440_hose = {0};
414 void pci_440_init (struct pci_controller *hose)
419 /*--------------------------------------------------------------------------+
420 * The PCI initialization sequence enable bit must be set ... if not abort
421 * pci setup since updating the bit requires chip reset.
422 *--------------------------------------------------------------------------*/
423 #if defined (CONFIG_440_GX)
424 mfsdr(sdr_sdstp1,strap);
425 if ( (strap & 0x00010000) == 0 ){
426 printf("PCI: SDR0_STRP1[PISE] not set.\n");
427 printf("PCI: Configuration aborted.\n");
431 strap = mfdcr(cpc0_strp1);
432 if( (strap & 0x00040000) == 0 ){
433 printf("PCI: CPC0_STRP1[PISE] not set.\n");
434 printf("PCI: Configuration aborted.\n");
438 /*--------------------------------------------------------------------------+
439 * PCI controller init
440 *--------------------------------------------------------------------------*/
441 hose->first_busno = 0;
442 hose->last_busno = 0xff;
444 pci_set_region(hose->regions + reg_num++,
450 pci_set_region(hose->regions + reg_num++,
455 hose->region_count = reg_num;
457 pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
459 #if defined(CFG_PCI_PRE_INIT)
460 /* Let board change/modify hose & do initial checks */
461 if( pci_pre_init (hose) == 0 ){
462 printf("PCI: Board-specific initialization failed.\n");
463 printf("PCI: Configuration aborted.\n");
468 pci_register_hose( hose );
470 /*--------------------------------------------------------------------------+
472 *--------------------------------------------------------------------------*/
473 #if defined(CFG_PCI_TARGET_INIT)
474 pci_target_init(hose); /* Let board setup pci target */
476 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
477 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
478 out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
481 #if defined(CONFIG_440_GX)
482 out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
483 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
485 out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
486 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
489 /*--------------------------------------------------------------------------+
490 * PCI master init: default is one 256MB region for PCI memory:
491 * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE
492 *--------------------------------------------------------------------------*/
493 #if defined(CFG_PCI_MASTER_INIT)
494 pci_master_init(hose); /* Let board setup pci master */
496 out32r( PCIX0_POM0SA, 0 ); /* disable */
497 out32r( PCIX0_POM1SA, 0 ); /* disable */
498 out32r( PCIX0_POM2SA, 0 ); /* disable */
499 out32r( PCIX0_POM0LAL, 0x00000000 );
500 out32r( PCIX0_POM0LAH, 0x00000003 );
501 out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
502 out32r( PCIX0_POM0PCIAH, 0x00000000 );
503 out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
504 out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
507 /*--------------------------------------------------------------------------+
508 * PCI host configuration -- we don't make any assumptions here ... the
509 * _board_must_indicate_ what to do -- there's just too many runtime
510 * scenarios in environments like cPCI, PPMC, etc. to make a determination
511 * based on hard-coded values or state of arbiter enable.
512 *--------------------------------------------------------------------------*/
513 if( is_pci_host(hose) ){
514 #ifdef CONFIG_PCI_SCAN_SHOW
515 printf("PCI: Bus Dev VenId DevId Class Int\n");
517 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
518 hose->last_busno = pci_hose_scan(hose);
523 void pci_init_board(void)
525 pci_440_init (&ppc440_hose);
528 #endif /* CONFIG_440 & CONFIG_PCI */