3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <asm/processor.h>
24 #include <asm-ppc/io.h>
29 #if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
31 #include "440spe_pcie.h"
35 PTYPE_LEGACY_ENDPOINT = 0x1,
36 PTYPE_ROOT_PORT = 0x4,
43 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
44 int offset, int len, u32 *val) {
48 * 440SPE implements only one function per port
50 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
53 devfn = PCI_BDF(0,0,0);
58 *val = in_8(hose->cfg_data + offset);
61 *val = in_le16((u16 *)(hose->cfg_data + offset));
64 *val = in_le32((u32 *)(hose->cfg_data + offset));
70 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
71 int offset, int len, u32 val) {
74 * 440SPE implements only one function per port
76 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
79 devfn = PCI_BDF(0,0,0);
84 out_8(hose->cfg_data + offset, val);
87 out_le16((u16 *)(hose->cfg_data + offset), val);
90 out_le32((u32 *)(hose->cfg_data + offset), val);
96 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
101 rv = pcie_read_config(hose, dev, offset, 1, &v);
106 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
111 rv = pcie_read_config(hose, dev, offset, 2, &v);
116 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
121 rv = pcie_read_config(hose, dev, offset, 3, &v);
126 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
128 return pcie_write_config(hose,(u32)dev,offset,1,val);
131 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
133 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
136 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
138 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
141 static void ppc440spe_setup_utl(u32 port) {
143 volatile void *utl_base = NULL;
150 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
151 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
152 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
153 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
157 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
158 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
159 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
160 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
164 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
165 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
166 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
167 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
170 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
173 * Set buffer allocations and then assert VRB and TXE.
175 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
176 out_be32(utl_base + PEUTL_INTR, 0x02000000);
177 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
178 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
179 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
180 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
181 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
182 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
185 static int check_error(void)
187 u32 valPE0, valPE1, valPE2;
190 /* SDR0_PEGPLLLCT1 reset */
191 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
192 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
195 valPE0 = SDR_READ(PESDR0_RCSSET);
196 valPE1 = SDR_READ(PESDR1_RCSSET);
197 valPE2 = SDR_READ(PESDR2_RCSSET);
199 /* SDR0_PExRCSSET rstgu */
200 if (!(valPE0 & 0x01000000) ||
201 !(valPE1 & 0x01000000) ||
202 !(valPE2 & 0x01000000)) {
203 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
207 /* SDR0_PExRCSSET rstdl */
208 if (!(valPE0 & 0x00010000) ||
209 !(valPE1 & 0x00010000) ||
210 !(valPE2 & 0x00010000)) {
211 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
215 /* SDR0_PExRCSSET rstpyn */
216 if ((valPE0 & 0x00001000) ||
217 (valPE1 & 0x00001000) ||
218 (valPE2 & 0x00001000)) {
219 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
223 /* SDR0_PExRCSSET hldplb */
224 if ((valPE0 & 0x10000000) ||
225 (valPE1 & 0x10000000) ||
226 (valPE2 & 0x10000000)) {
227 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
231 /* SDR0_PExRCSSET rdy */
232 if ((valPE0 & 0x00100000) ||
233 (valPE1 & 0x00100000) ||
234 (valPE2 & 0x00100000)) {
235 printf("PCIE: SDR0_PExRCSSET rdy error\n");
239 /* SDR0_PExRCSSET shutdown */
240 if ((valPE0 & 0x00000100) ||
241 (valPE1 & 0x00000100) ||
242 (valPE2 & 0x00000100)) {
243 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
250 * Initialize PCI Express core
252 int ppc440spe_init_pcie(void)
256 /* Set PLL clock receiver to LVPECL */
257 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
262 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
264 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
265 SDR_READ(PESDR0_PLLLCT2));
268 /* De-assert reset of PCIe PLL, wait for lock */
269 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
273 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
280 printf("PCIE: VCO output not locked\n");
287 * Yucca board as End point and root point setup
289 * testing inbound and out bound windows
291 * YUCCA board can be plugged into another yucca board or you can get PCI-E
292 * cable which can be used to setup loop back from one port to another port.
293 * Please rememeber that unless there is a endpoint plugged in to root port it
294 * will not initialize. It is the same in case of endpoint , unless there is
295 * root port attached it will not initialize.
297 * In this release of software all the PCI-E ports are configured as either
298 * endpoint or rootpoint.In future we will have support for selective ports
299 * setup as endpoint and root point in single board.
301 * Once your board came up as root point , you can verify by reading
302 * /proc/bus/pci/devices. Where you can see the configuration registers
303 * of end point device attached to the port.
305 * Enpoint cofiguration can be verified by connecting Yucca board to any
306 * host or another yucca board. Then try to scan the device. In case of
307 * linux use "lspci" or appripriate os command.
309 * How do I verify the inbound and out bound windows ?(yucca to yucca)
310 * in this configuration inbound and outbound windows are setup to access
311 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
312 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
313 * This is waere your POM(PLB out bound memory window) mapped. then
314 * read the data from other yucca board's u-boot prompt at address
315 * 0x9000 0000(SRAM). Data should match.
316 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
317 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
318 * data at 0x9000 0000(SRAM).Data should match.
320 int ppc440spe_init_pcie_rootport(int port)
322 static int core_init;
323 volatile u32 val = 0;
328 if (ppc440spe_init_pcie())
333 * Initialize various parts of the PCI Express core for our port:
335 * - Set as a root port and enable max width
336 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
337 * - Set up UTL configuration.
338 * - Increase SERDES drive strength to levels suggested by AMCC.
339 * - De-assert RSTPYN, RSTDL and RSTGU.
341 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
342 * default setting 0x11310000. The register has new fields,
343 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
348 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
350 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
351 if (!ppc440spe_revB())
352 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
353 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
354 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
355 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
356 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
357 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
358 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
359 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
360 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
361 SDR_WRITE(PESDR0_RCSSET,
362 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
366 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
367 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
368 if (!ppc440spe_revB())
369 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
370 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
371 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
372 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
373 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
374 SDR_WRITE(PESDR1_RCSSET,
375 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
379 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
380 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
381 if (!ppc440spe_revB())
382 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
383 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
384 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
385 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
386 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
387 SDR_WRITE(PESDR2_RCSSET,
388 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
392 * Notice: the following delay has critical impact on device
393 * initialization - if too short (<50ms) the link doesn't get up.
399 val = SDR_READ(PESDR0_RCSSTS);
402 val = SDR_READ(PESDR1_RCSSTS);
405 val = SDR_READ(PESDR2_RCSSTS);
409 if (val & (1 << 20)) {
410 printf("PCIE%d: PGRST failed %08x\n", port, val);
420 val = SDR_READ(PESDR0_LOOP);
423 val = SDR_READ(PESDR1_LOOP);
426 val = SDR_READ(PESDR2_LOOP);
429 if (!(val & 0x00001000)) {
430 printf("PCIE%d: link is not up.\n", port);
435 * Setup UTL registers - but only on revA!
436 * We use default settings for revB chip.
438 if (!ppc440spe_revB())
439 ppc440spe_setup_utl(port);
442 * We map PCI Express configuration access into the 512MB regions
444 * NOTICE: revB is very strict about PLB real addressess and ranges to
445 * be mapped for config space; it seems to only work with d_nnnn_nnnn
446 * range (hangs the core upon config transaction attempts when set
447 * otherwise) while revA uses c_nnnn_nnnn.
450 * PCIE0: 0xc_4000_0000
451 * PCIE1: 0xc_8000_0000
452 * PCIE2: 0xc_c000_0000
455 * PCIE0: 0xd_0000_0000
456 * PCIE1: 0xd_2000_0000
457 * PCIE2: 0xd_4000_0000
462 if (ppc440spe_revB()) {
463 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
464 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
467 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
468 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
470 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
474 if (ppc440spe_revB()) {
475 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
476 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
478 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
479 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
481 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
485 if (ppc440spe_revB()) {
486 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
487 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
489 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
490 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
492 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
497 * Check for VC0 active and assert RDY.
502 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
504 printf("PCIE0: VC0 not active\n");
509 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
512 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
514 printf("PCIE1: VC0 not active\n");
520 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
523 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
525 printf("PCIE2: VC0 not active\n");
531 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
539 int ppc440spe_init_pcie_endport(int port)
541 static int core_init;
542 volatile u32 val = 0;
547 if (ppc440spe_init_pcie())
552 * Initialize various parts of the PCI Express core for our port:
554 * - Set as a end port and enable max width
555 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
556 * - Set up UTL configuration.
557 * - Increase SERDES drive strength to levels suggested by AMCC.
558 * - De-assert RSTPYN, RSTDL and RSTGU.
560 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
561 * default setting 0x11310000. The register has new fields,
562 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
567 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
569 SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
570 if (!ppc440spe_revB())
571 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
572 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
573 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
574 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
575 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
576 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
577 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
578 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
579 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
580 SDR_WRITE(PESDR0_RCSSET,
581 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
585 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
586 SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
587 if (!ppc440spe_revB())
588 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
589 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
590 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
591 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
592 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
593 SDR_WRITE(PESDR1_RCSSET,
594 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
598 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
599 SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
600 if (!ppc440spe_revB())
601 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
602 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
603 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
604 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
605 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
606 SDR_WRITE(PESDR2_RCSSET,
607 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
611 * Notice: the following delay has critical impact on device
612 * initialization - if too short (<50ms) the link doesn't get up.
617 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
618 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
619 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
622 if (val & (1 << 20)) {
623 printf("PCIE%d: PGRST failed %08x\n", port, val);
634 val = SDR_READ(PESDR0_LOOP);
637 val = SDR_READ(PESDR1_LOOP);
640 val = SDR_READ(PESDR2_LOOP);
643 if (!(val & 0x00001000)) {
644 printf("PCIE%d: link is not up.\n", port);
649 * Setup UTL registers - but only on revA!
650 * We use default settings for revB chip.
652 if (!ppc440spe_revB())
653 ppc440spe_setup_utl(port);
656 * We map PCI Express configuration access into the 512MB regions
658 * NOTICE: revB is very strict about PLB real addressess and ranges to
659 * be mapped for config space; it seems to only work with d_nnnn_nnnn
660 * range (hangs the core upon config transaction attempts when set
661 * otherwise) while revA uses c_nnnn_nnnn.
664 * PCIE0: 0xc_4000_0000
665 * PCIE1: 0xc_8000_0000
666 * PCIE2: 0xc_c000_0000
669 * PCIE0: 0xd_0000_0000
670 * PCIE1: 0xd_2000_0000
671 * PCIE2: 0xd_4000_0000
675 if (ppc440spe_revB()) {
676 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
677 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
680 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
681 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
683 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
687 if (ppc440spe_revB()) {
688 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
689 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
691 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
692 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
694 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
698 if (ppc440spe_revB()) {
699 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
700 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
702 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
703 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
705 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
710 * Check for VC0 active and assert RDY.
715 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
717 printf("PCIE0: VC0 not active\n");
722 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
725 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
727 printf("PCIE1: VC0 not active\n");
733 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
736 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
738 printf("PCIE2: VC0 not active\n");
744 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
752 void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
754 volatile void *mbase = NULL;
755 volatile void *rmbase = NULL;
758 pcie_read_config_byte,
759 pcie_read_config_word,
760 pcie_read_config_dword,
761 pcie_write_config_byte,
762 pcie_write_config_word,
763 pcie_write_config_dword);
767 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
768 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
769 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
772 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
773 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
774 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
777 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
778 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
779 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
784 * Set bus numbers on our root port
786 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
787 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
788 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
791 * Set up outbound translation to hose->mem_space from PLB
792 * addresses at an offset of 0xd_0000_0000. We set the low
793 * bits of the mask to 11 to turn off splitting into 8
794 * subregions and to enable the outbound translation.
796 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
797 out_le32(mbase + PECFG_POM0LAL, 0x00000000);
801 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
802 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
803 port * CFG_PCIE_MEMSIZE);
804 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
805 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
806 ~(CFG_PCIE_MEMSIZE - 1) | 3);
809 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
810 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
811 port * CFG_PCIE_MEMSIZE));
812 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
813 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
814 ~(CFG_PCIE_MEMSIZE - 1) | 3);
817 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
818 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
819 port * CFG_PCIE_MEMSIZE));
820 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
821 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
822 ~(CFG_PCIE_MEMSIZE - 1) | 3);
826 /* Set up 16GB inbound memory window at 0 */
827 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
828 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
829 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
830 out_le32(mbase + PECFG_BAR0LMPA, 0);
832 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
833 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
834 out_le32(mbase + PECFG_PIM0LAL, 0);
835 out_le32(mbase + PECFG_PIM0LAH, 0);
836 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
837 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
838 out_le32(mbase + PECFG_PIMEN, 0x1);
840 /* Enable I/O, Mem, and Busmaster cycles */
841 out_le16((u16 *)(mbase + PCI_COMMAND),
842 in_le16((u16 *)(mbase + PCI_COMMAND)) |
843 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
844 printf("PCIE:%d successfully set as rootpoint\n",port);
847 int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
849 volatile void *mbase = NULL;
853 pcie_read_config_byte,
854 pcie_read_config_word,
855 pcie_read_config_dword,
856 pcie_write_config_byte,
857 pcie_write_config_word,
858 pcie_write_config_dword);
862 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
863 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
866 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
867 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
870 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
871 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
876 * Set up outbound translation to hose->mem_space from PLB
877 * addresses at an offset of 0xd_0000_0000. We set the low
878 * bits of the mask to 11 to turn off splitting into 8
879 * subregions and to enable the outbound translation.
881 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
882 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
886 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
887 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
888 port * CFG_PCIE_MEMSIZE);
889 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
890 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
891 ~(CFG_PCIE_MEMSIZE - 1) | 3);
894 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
895 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
896 port * CFG_PCIE_MEMSIZE));
897 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
898 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
899 ~(CFG_PCIE_MEMSIZE - 1) | 3);
902 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
903 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
904 port * CFG_PCIE_MEMSIZE));
905 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
906 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
907 ~(CFG_PCIE_MEMSIZE - 1) | 3);
911 /* Set up 16GB inbound memory window at 0 */
912 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
913 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
914 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
915 out_le32(mbase + PECFG_BAR0LMPA, 0);
916 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
917 out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
918 out_le32(mbase + PECFG_PIMEN, 0x1);
920 /* Enable I/O, Mem, and Busmaster cycles */
921 out_le16((u16 *)(mbase + PCI_COMMAND),
922 in_le16((u16 *)(mbase + PCI_COMMAND)) |
923 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
924 out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
925 out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
929 while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
931 printf("PCIE0: BMEN is not active\n");
938 while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
940 printf("PCIE1: BMEN is not active\n");
947 while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
949 printf("PCIE2: BMEN is not active\n");
956 printf("PCIE:%d successfully set as endpoint\n",port);
960 #endif /* CONFIG_440SPE && CONFIG_PCI */