3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <asm/processor.h>
24 #include <asm-ppc/io.h>
29 #include "440spe_pcie.h"
31 #if defined(CONFIG_440SPE)
32 #if defined(CONFIG_PCI)
36 PTYPE_LEGACY_ENDPOINT = 0x1,
37 PTYPE_ROOT_PORT = 0x4,
44 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
45 int offset, int len, u32 *val) {
49 * 440SPE implements only one function per port
51 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
54 devfn = PCI_BDF(0,0,0);
59 *val = in_8(hose->cfg_data + offset);
62 *val = in_le16((u16 *)(hose->cfg_data + offset));
65 *val = in_le32((u32 *)(hose->cfg_data + offset));
71 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
72 int offset, int len, u32 val) {
75 * 440SPE implements only one function per port
77 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
80 devfn = PCI_BDF(0,0,0);
85 out_8(hose->cfg_data + offset, val);
88 out_le16((u16 *)(hose->cfg_data + offset), val);
91 out_le32((u32 *)(hose->cfg_data + offset), val);
97 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
102 rv = pcie_read_config(hose, dev, offset, 1, &v);
107 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
112 rv = pcie_read_config(hose, dev, offset, 2, &v);
117 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
122 rv = pcie_read_config(hose, dev, offset, 3, &v);
127 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
129 return pcie_write_config(hose,(u32)dev,offset,1,val);
132 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
134 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
137 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
139 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
142 static void ppc440spe_setup_utl(u32 port) {
144 volatile void *utl_base = NULL;
151 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
152 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
153 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
154 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
158 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
159 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
160 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
161 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
165 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
166 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
167 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
168 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
171 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
174 * Set buffer allocations and then assert VRB and TXE.
176 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
177 out_be32(utl_base + PEUTL_INTR, 0x02000000);
178 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
179 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
180 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
181 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
182 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
183 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
186 static int check_error(void)
188 u32 valPE0, valPE1, valPE2;
191 /* SDR0_PEGPLLLCT1 reset */
192 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
193 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
196 valPE0 = SDR_READ(PESDR0_RCSSET);
197 valPE1 = SDR_READ(PESDR1_RCSSET);
198 valPE2 = SDR_READ(PESDR2_RCSSET);
200 /* SDR0_PExRCSSET rstgu */
201 if (!(valPE0 & 0x01000000) ||
202 !(valPE1 & 0x01000000) ||
203 !(valPE2 & 0x01000000)) {
204 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
208 /* SDR0_PExRCSSET rstdl */
209 if (!(valPE0 & 0x00010000) ||
210 !(valPE1 & 0x00010000) ||
211 !(valPE2 & 0x00010000)) {
212 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
216 /* SDR0_PExRCSSET rstpyn */
217 if ((valPE0 & 0x00001000) ||
218 (valPE1 & 0x00001000) ||
219 (valPE2 & 0x00001000)) {
220 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
224 /* SDR0_PExRCSSET hldplb */
225 if ((valPE0 & 0x10000000) ||
226 (valPE1 & 0x10000000) ||
227 (valPE2 & 0x10000000)) {
228 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
232 /* SDR0_PExRCSSET rdy */
233 if ((valPE0 & 0x00100000) ||
234 (valPE1 & 0x00100000) ||
235 (valPE2 & 0x00100000)) {
236 printf("PCIE: SDR0_PExRCSSET rdy error\n");
240 /* SDR0_PExRCSSET shutdown */
241 if ((valPE0 & 0x00000100) ||
242 (valPE1 & 0x00000100) ||
243 (valPE2 & 0x00000100)) {
244 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
251 * Initialize PCI Express core
253 int ppc440spe_init_pcie(void)
257 /* Set PLL clock receiver to LVPECL */
258 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
263 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
265 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
266 SDR_READ(PESDR0_PLLLCT2));
269 /* De-assert reset of PCIe PLL, wait for lock */
270 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
274 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
281 printf("PCIE: VCO output not locked\n");
287 int ppc440spe_init_pcie_rootport(int port)
289 static int core_init;
290 volatile u32 val = 0;
295 if (ppc440spe_init_pcie())
300 * Initialize various parts of the PCI Express core for our port:
302 * - Set as a root port and enable max width
303 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
304 * - Set up UTL configuration.
305 * - Increase SERDES drive strength to levels suggested by AMCC.
306 * - De-assert RSTPYN, RSTDL and RSTGU.
308 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
309 * default setting 0x11310000. The register has new fields,
310 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
315 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
317 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
318 if (!ppc440spe_revB())
319 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
320 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
321 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
322 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
323 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
324 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
325 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
326 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
327 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
328 SDR_WRITE(PESDR0_RCSSET,
329 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
333 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
334 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
335 if (!ppc440spe_revB())
336 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
337 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
338 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
339 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
340 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
341 SDR_WRITE(PESDR1_RCSSET,
342 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
346 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
347 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
348 if (!ppc440spe_revB())
349 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
350 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
351 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
352 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
353 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
354 SDR_WRITE(PESDR2_RCSSET,
355 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
359 * Notice: the following delay has critical impact on device
360 * initialization - if too short (<50ms) the link doesn't get up.
365 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
366 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
367 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
370 if (val & (1 << 20)) {
371 printf("PCIE%d: PGRST failed %08x\n", port, val);
382 val = SDR_READ(PESDR0_LOOP);
385 val = SDR_READ(PESDR1_LOOP);
388 val = SDR_READ(PESDR2_LOOP);
391 if (!(val & 0x00001000)) {
392 printf("PCIE%d: link is not up.\n", port);
397 * Setup UTL registers - but only on revA!
398 * We use default settings for revB chip.
400 if (!ppc440spe_revB())
401 ppc440spe_setup_utl(port);
404 * We map PCI Express configuration access into the 512MB regions
406 * NOTICE: revB is very strict about PLB real addressess and ranges to
407 * be mapped for config space; it seems to only work with d_nnnn_nnnn
408 * range (hangs the core upon config transaction attempts when set
409 * otherwise) while revA uses c_nnnn_nnnn.
412 * PCIE0: 0xc_4000_0000
413 * PCIE1: 0xc_8000_0000
414 * PCIE2: 0xc_c000_0000
417 * PCIE0: 0xd_0000_0000
418 * PCIE1: 0xd_2000_0000
419 * PCIE2: 0xd_4000_0000
424 if (ppc440spe_revB()) {
425 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
426 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
429 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
430 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
432 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
436 if (ppc440spe_revB()) {
437 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
438 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
440 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
441 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
443 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
447 if (ppc440spe_revB()) {
448 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
449 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
451 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
452 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
454 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
459 * Check for VC0 active and assert RDY.
464 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
466 printf("PCIE0: VC0 not active\n");
471 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
474 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
476 printf("PCIE1: VC0 not active\n");
482 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
485 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
487 printf("PCIE2: VC0 not active\n");
493 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
501 void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
503 volatile void *mbase = NULL;
506 pcie_read_config_byte,
507 pcie_read_config_word,
508 pcie_read_config_dword,
509 pcie_write_config_byte,
510 pcie_write_config_word,
511 pcie_write_config_dword);
515 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
516 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
519 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
520 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
523 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
524 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
529 * Set bus numbers on our root port
531 if (ppc440spe_revB()) {
532 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
533 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
534 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
536 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
537 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
541 * Set up outbound translation to hose->mem_space from PLB
542 * addresses at an offset of 0xd_0000_0000. We set the low
543 * bits of the mask to 11 to turn off splitting into 8
544 * subregions and to enable the outbound translation.
546 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
547 out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE +
548 port * CFG_PCIE_MEMSIZE));
552 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
553 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
554 port * CFG_PCIE_MEMSIZE);
555 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
556 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
557 ~(CFG_PCIE_MEMSIZE - 1) | 3);
560 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
561 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
562 port * CFG_PCIE_MEMSIZE));
563 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
564 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
565 ~(CFG_PCIE_MEMSIZE - 1) | 3);
568 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
569 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
570 port * CFG_PCIE_MEMSIZE));
571 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
572 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
573 ~(CFG_PCIE_MEMSIZE - 1) | 3);
577 /* Set up 16GB inbound memory window at 0 */
578 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
579 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
580 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
581 out_le32(mbase + PECFG_BAR0LMPA, 0);
582 out_le32(mbase + PECFG_PIM0LAL, 0);
583 out_le32(mbase + PECFG_PIM0LAH, 0);
584 out_le32(mbase + PECFG_PIMEN, 0x1);
586 /* Enable I/O, Mem, and Busmaster cycles */
587 out_le16((u16 *)(mbase + PCI_COMMAND),
588 in_le16((u16 *)(mbase + PCI_COMMAND)) |
589 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
591 #endif /* CONFIG_PCI */
592 #endif /* CONFIG_440SPE */