2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* define DEBUG for debugging output (obviously ;-)) */
47 #include <asm/processor.h>
49 #include <asm/cache.h>
53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
58 mfsdram(SDRAM_##mnemonic, data); \
59 printf("%20s[%02x] = 0x%08X\n", \
60 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
63 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
66 data = mfdcr(SDRAM_##mnemonic); \
67 printf("%20s[%02x] = 0x%08X\n", \
68 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
71 #if defined(CONFIG_440)
73 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
74 * memory region. Right now the cache should still be disabled in U-Boot
75 * because of the EMAC driver, that need its buffer descriptor to be located
76 * in non cached memory.
78 * If at some time this restriction doesn't apply anymore, just define
79 * CONFIG_4xx_DCACHE in the board config file and this code should setup
80 * everything correctly.
82 #ifdef CONFIG_4xx_DCACHE
83 /* enable caching on SDRAM */
84 #define MY_TLB_WORD2_I_ENABLE 0
86 /* disable caching on SDRAM */
87 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
88 #endif /* CONFIG_4xx_DCACHE */
89 #endif /* CONFIG_440 */
91 #if defined(CONFIG_SPD_EEPROM)
93 /*-----------------------------------------------------------------------------+
95 *-----------------------------------------------------------------------------*/
110 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
112 #define ONE_BILLION 1000000000
114 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
116 #define CMD_NOP (7 << 19)
117 #define CMD_PRECHARGE (2 << 19)
118 #define CMD_REFRESH (1 << 19)
119 #define CMD_EMR (0 << 19)
120 #define CMD_READ (5 << 19)
121 #define CMD_WRITE (4 << 19)
123 #define SELECT_MR (0 << 16)
124 #define SELECT_EMR (1 << 16)
125 #define SELECT_EMR2 (2 << 16)
126 #define SELECT_EMR3 (3 << 16)
129 #define DLL_RESET 0x00000100
131 #define WRITE_RECOV_2 (1 << 9)
132 #define WRITE_RECOV_3 (2 << 9)
133 #define WRITE_RECOV_4 (3 << 9)
134 #define WRITE_RECOV_5 (4 << 9)
135 #define WRITE_RECOV_6 (5 << 9)
137 #define BURST_LEN_4 0x00000002
140 #define ODT_0_OHM 0x00000000
141 #define ODT_50_OHM 0x00000044
142 #define ODT_75_OHM 0x00000004
143 #define ODT_150_OHM 0x00000040
145 #define ODS_FULL 0x00000000
146 #define ODS_REDUCED 0x00000002
147 #define OCD_CALIB_DEF 0x00000380
149 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
150 #define ODT_EB0R (0x80000000 >> 8)
151 #define ODT_EB0W (0x80000000 >> 7)
152 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
153 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
154 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
156 /* Defines for the Read Cycle Delay test */
157 #define NUMMEMTESTS 8
158 #define NUMMEMWORDS 8
159 #define NUMLOOPS 64 /* memory test loops */
162 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
163 * To support such configurations, we "only" map the first 2GB via the TLB's. We
164 * need some free virtual address space for the remaining peripherals like, SoC
165 * devices, FLASH etc.
167 * Note that ECC is currently not supported on configurations with more than 2GB
168 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
169 * the ECC parity byte of the remaining area can't be written.
173 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
175 void __spd_ddr_init_hang (void)
179 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
182 * To provide an interface for board specific config values in this common
183 * DDR setup code, we implement he "weak" default functions here. They return
184 * the default value back to the caller.
186 * Please see include/configs/yucca.h for an example fora board specific
189 u32 __ddr_wrdtr(u32 default_val)
193 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
195 u32 __ddr_clktr(u32 default_val)
199 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
202 /* Private Structure Definitions */
204 /* enum only to ease code for cas latency setting */
205 typedef enum ddr_cas_id {
213 /*-----------------------------------------------------------------------------+
215 *-----------------------------------------------------------------------------*/
216 static phys_size_t sdram_memsize(void);
217 static void get_spd_info(unsigned long *dimm_populated,
218 unsigned char *iic0_dimm_addr,
219 unsigned long num_dimm_banks);
220 static void check_mem_type(unsigned long *dimm_populated,
221 unsigned char *iic0_dimm_addr,
222 unsigned long num_dimm_banks);
223 static void check_frequency(unsigned long *dimm_populated,
224 unsigned char *iic0_dimm_addr,
225 unsigned long num_dimm_banks);
226 static void check_rank_number(unsigned long *dimm_populated,
227 unsigned char *iic0_dimm_addr,
228 unsigned long num_dimm_banks);
229 static void check_voltage_type(unsigned long *dimm_populated,
230 unsigned char *iic0_dimm_addr,
231 unsigned long num_dimm_banks);
232 static void program_memory_queue(unsigned long *dimm_populated,
233 unsigned char *iic0_dimm_addr,
234 unsigned long num_dimm_banks);
235 static void program_codt(unsigned long *dimm_populated,
236 unsigned char *iic0_dimm_addr,
237 unsigned long num_dimm_banks);
238 static void program_mode(unsigned long *dimm_populated,
239 unsigned char *iic0_dimm_addr,
240 unsigned long num_dimm_banks,
241 ddr_cas_id_t *selected_cas,
242 int *write_recovery);
243 static void program_tr(unsigned long *dimm_populated,
244 unsigned char *iic0_dimm_addr,
245 unsigned long num_dimm_banks);
246 static void program_rtr(unsigned long *dimm_populated,
247 unsigned char *iic0_dimm_addr,
248 unsigned long num_dimm_banks);
249 static void program_bxcf(unsigned long *dimm_populated,
250 unsigned char *iic0_dimm_addr,
251 unsigned long num_dimm_banks);
252 static void program_copt1(unsigned long *dimm_populated,
253 unsigned char *iic0_dimm_addr,
254 unsigned long num_dimm_banks);
255 static void program_initplr(unsigned long *dimm_populated,
256 unsigned char *iic0_dimm_addr,
257 unsigned long num_dimm_banks,
258 ddr_cas_id_t selected_cas,
260 static unsigned long is_ecc_enabled(void);
261 #ifdef CONFIG_DDR_ECC
262 static void program_ecc(unsigned long *dimm_populated,
263 unsigned char *iic0_dimm_addr,
264 unsigned long num_dimm_banks,
265 unsigned long tlb_word2_i_value);
266 static void program_ecc_addr(unsigned long start_address,
267 unsigned long num_bytes,
268 unsigned long tlb_word2_i_value);
270 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
271 static void program_DQS_calibration(unsigned long *dimm_populated,
272 unsigned char *iic0_dimm_addr,
273 unsigned long num_dimm_banks);
274 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
275 static void test(void);
277 static void DQS_calibration_process(void);
280 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
281 void dcbz_area(u32 start_address, u32 num_bytes);
283 static unsigned char spd_read(uchar chip, uint addr)
285 unsigned char data[2];
287 if (i2c_probe(chip) == 0)
288 if (i2c_read(chip, addr, 1, data, 1) == 0)
294 /*-----------------------------------------------------------------------------+
296 *-----------------------------------------------------------------------------*/
297 static phys_size_t sdram_memsize(void)
299 phys_size_t mem_size;
300 unsigned long mcopt2;
301 unsigned long mcstat;
308 mfsdram(SDRAM_MCOPT2, mcopt2);
309 mfsdram(SDRAM_MCSTAT, mcstat);
311 /* DDR controller must be enabled and not in self-refresh. */
312 /* Otherwise memsize is zero. */
313 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
314 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
315 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
316 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
317 for (i = 0; i < MAXBXCF; i++) {
318 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
320 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
321 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
324 case SDRAM_RXBAS_SDSZ_8:
327 case SDRAM_RXBAS_SDSZ_16:
330 case SDRAM_RXBAS_SDSZ_32:
333 case SDRAM_RXBAS_SDSZ_64:
336 case SDRAM_RXBAS_SDSZ_128:
339 case SDRAM_RXBAS_SDSZ_256:
342 case SDRAM_RXBAS_SDSZ_512:
345 case SDRAM_RXBAS_SDSZ_1024:
348 case SDRAM_RXBAS_SDSZ_2048:
351 case SDRAM_RXBAS_SDSZ_4096:
355 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
364 return mem_size << 20;
367 /*-----------------------------------------------------------------------------+
368 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
369 * Note: This routine runs from flash with a stack set up in the chip's
370 * sram space. It is important that the routine does not require .sbss, .bss or
371 * .data sections. It also cannot call routines that require these sections.
372 *-----------------------------------------------------------------------------*/
373 /*-----------------------------------------------------------------------------
375 * Description: Configures SDRAM memory banks for DDR operation.
376 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
377 * via the IIC bus and then configures the DDR SDRAM memory
378 * banks appropriately. If Auto Memory Configuration is
379 * not used, it is assumed that no DIMM is plugged
380 *-----------------------------------------------------------------------------*/
381 phys_size_t initdram(int board_type)
383 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
384 unsigned char spd0[MAX_SPD_BYTES];
385 unsigned char spd1[MAX_SPD_BYTES];
386 unsigned char *dimm_spd[MAXDIMMS];
387 unsigned long dimm_populated[MAXDIMMS];
388 unsigned long num_dimm_banks; /* on board dimm banks */
390 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
392 phys_size_t dram_size = 0;
394 num_dimm_banks = sizeof(iic0_dimm_addr);
396 /*------------------------------------------------------------------
397 * Set up an array of SPD matrixes.
398 *-----------------------------------------------------------------*/
402 /*------------------------------------------------------------------
403 * Reset the DDR-SDRAM controller.
404 *-----------------------------------------------------------------*/
405 mtsdr(SDR0_SRST, (0x80000000 >> 10));
406 mtsdr(SDR0_SRST, 0x00000000);
409 * Make sure I2C controller is initialized
413 /* switch to correct I2C bus */
414 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
415 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
417 /*------------------------------------------------------------------
418 * Clear out the serial presence detect buffers.
419 * Perform IIC reads from the dimm. Fill in the spds.
420 * Check to see if the dimm slots are populated
421 *-----------------------------------------------------------------*/
422 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
424 /*------------------------------------------------------------------
425 * Check the memory type for the dimms plugged.
426 *-----------------------------------------------------------------*/
427 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
429 /*------------------------------------------------------------------
430 * Check the frequency supported for the dimms plugged.
431 *-----------------------------------------------------------------*/
432 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
434 /*------------------------------------------------------------------
435 * Check the total rank number.
436 *-----------------------------------------------------------------*/
437 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
439 /*------------------------------------------------------------------
440 * Check the voltage type for the dimms plugged.
441 *-----------------------------------------------------------------*/
442 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
444 /*------------------------------------------------------------------
445 * Program SDRAM controller options 2 register
446 * Except Enabling of the memory controller.
447 *-----------------------------------------------------------------*/
448 mfsdram(SDRAM_MCOPT2, val);
449 mtsdram(SDRAM_MCOPT2,
451 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
452 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
453 SDRAM_MCOPT2_ISIE_MASK))
454 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
455 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
456 SDRAM_MCOPT2_ISIE_ENABLE));
458 /*------------------------------------------------------------------
459 * Program SDRAM controller options 1 register
460 * Note: Does not enable the memory controller.
461 *-----------------------------------------------------------------*/
462 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
464 /*------------------------------------------------------------------
465 * Set the SDRAM Controller On Die Termination Register
466 *-----------------------------------------------------------------*/
467 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
469 /*------------------------------------------------------------------
470 * Program SDRAM refresh register.
471 *-----------------------------------------------------------------*/
472 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
474 /*------------------------------------------------------------------
475 * Program SDRAM mode register.
476 *-----------------------------------------------------------------*/
477 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
478 &selected_cas, &write_recovery);
480 /*------------------------------------------------------------------
481 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
482 *-----------------------------------------------------------------*/
483 mfsdram(SDRAM_WRDTR, val);
484 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
485 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
487 /*------------------------------------------------------------------
488 * Set the SDRAM Clock Timing Register
489 *-----------------------------------------------------------------*/
490 mfsdram(SDRAM_CLKTR, val);
491 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
492 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
494 /*------------------------------------------------------------------
495 * Program the BxCF registers.
496 *-----------------------------------------------------------------*/
497 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
499 /*------------------------------------------------------------------
500 * Program SDRAM timing registers.
501 *-----------------------------------------------------------------*/
502 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
504 /*------------------------------------------------------------------
505 * Set the Extended Mode register
506 *-----------------------------------------------------------------*/
507 mfsdram(SDRAM_MEMODE, val);
508 mtsdram(SDRAM_MEMODE,
509 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
510 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
511 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
512 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
514 /*------------------------------------------------------------------
515 * Program Initialization preload registers.
516 *-----------------------------------------------------------------*/
517 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
518 selected_cas, write_recovery);
520 /*------------------------------------------------------------------
521 * Delay to ensure 200usec have elapsed since reset.
522 *-----------------------------------------------------------------*/
525 /*------------------------------------------------------------------
526 * Set the memory queue core base addr.
527 *-----------------------------------------------------------------*/
528 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
530 /*------------------------------------------------------------------
531 * Program SDRAM controller options 2 register
532 * Enable the memory controller.
533 *-----------------------------------------------------------------*/
534 mfsdram(SDRAM_MCOPT2, val);
535 mtsdram(SDRAM_MCOPT2,
536 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
537 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
538 SDRAM_MCOPT2_IPTR_EXECUTE);
540 /*------------------------------------------------------------------
541 * Wait for IPTR_EXECUTE init sequence to complete.
542 *-----------------------------------------------------------------*/
544 mfsdram(SDRAM_MCSTAT, val);
545 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
547 /* enable the controller only after init sequence completes */
548 mfsdram(SDRAM_MCOPT2, val);
549 mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
551 /* Make sure delay-line calibration is done before proceeding */
553 mfsdram(SDRAM_DLCR, val);
554 } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
556 /* get installed memory size */
557 dram_size = sdram_memsize();
562 if (dram_size > CONFIG_MAX_MEM_MAPPED)
563 dram_size = CONFIG_MAX_MEM_MAPPED;
565 /* and program tlb entries for this size (dynamic) */
568 * Program TLB entries with caches enabled, for best performace
569 * while auto-calibrating and ECC generation
571 program_tlb(0, 0, dram_size, 0);
573 /*------------------------------------------------------------------
575 *-----------------------------------------------------------------*/
576 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
577 DQS_autocalibration();
579 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
582 #ifdef CONFIG_DDR_ECC
583 /*------------------------------------------------------------------
584 * If ecc is enabled, initialize the parity bits.
585 *-----------------------------------------------------------------*/
586 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
590 * Now after initialization (auto-calibration and ECC generation)
591 * remove the TLB entries with caches enabled and program again with
592 * desired cache functionality
594 remove_tlb(0, dram_size);
595 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
597 ppc4xx_ibm_ddr2_register_dump();
600 * Clear potential errors resulting from auto-calibration.
601 * If not done, then we could get an interrupt later on when
602 * exceptions are enabled.
604 set_mcsr(get_mcsr());
606 return sdram_memsize();
609 static void get_spd_info(unsigned long *dimm_populated,
610 unsigned char *iic0_dimm_addr,
611 unsigned long num_dimm_banks)
613 unsigned long dimm_num;
614 unsigned long dimm_found;
615 unsigned char num_of_bytes;
616 unsigned char total_size;
619 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
623 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
624 debug("\nspd_read(0x%x) returned %d\n",
625 iic0_dimm_addr[dimm_num], num_of_bytes);
626 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
627 debug("spd_read(0x%x) returned %d\n",
628 iic0_dimm_addr[dimm_num], total_size);
630 if ((num_of_bytes != 0) && (total_size != 0)) {
631 dimm_populated[dimm_num] = TRUE;
633 debug("DIMM slot %lu: populated\n", dimm_num);
635 dimm_populated[dimm_num] = FALSE;
636 debug("DIMM slot %lu: Not populated\n", dimm_num);
640 if (dimm_found == FALSE) {
641 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
642 spd_ddr_init_hang ();
646 void board_add_ram_info(int use_default)
648 PPC4xx_SYS_INFO board_cfg;
651 if (is_ecc_enabled())
656 get_sys_info(&board_cfg);
658 mfsdr(SDR0_DDR0, val);
659 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
660 printf(" enabled, %d MHz", (val * 2) / 1000000);
662 mfsdram(SDRAM_MMODE, val);
663 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
664 printf(", CL%d)", val);
667 /*------------------------------------------------------------------
668 * For the memory DIMMs installed, this routine verifies that they
669 * really are DDR specific DIMMs.
670 *-----------------------------------------------------------------*/
671 static void check_mem_type(unsigned long *dimm_populated,
672 unsigned char *iic0_dimm_addr,
673 unsigned long num_dimm_banks)
675 unsigned long dimm_num;
676 unsigned long dimm_type;
678 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
679 if (dimm_populated[dimm_num] == TRUE) {
680 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
683 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
684 "slot %d.\n", (unsigned int)dimm_num);
685 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
686 printf("Replace the DIMM module with a supported DIMM.\n\n");
687 spd_ddr_init_hang ();
690 printf("ERROR: EDO DIMM detected in slot %d.\n",
691 (unsigned int)dimm_num);
692 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
693 printf("Replace the DIMM module with a supported DIMM.\n\n");
694 spd_ddr_init_hang ();
697 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
698 (unsigned int)dimm_num);
699 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
700 printf("Replace the DIMM module with a supported DIMM.\n\n");
701 spd_ddr_init_hang ();
704 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
705 (unsigned int)dimm_num);
706 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
707 printf("Replace the DIMM module with a supported DIMM.\n\n");
708 spd_ddr_init_hang ();
711 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
712 (unsigned int)dimm_num);
713 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
714 printf("Replace the DIMM module with a supported DIMM.\n\n");
715 spd_ddr_init_hang ();
718 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
719 (unsigned int)dimm_num);
720 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
721 printf("Replace the DIMM module with a supported DIMM.\n\n");
722 spd_ddr_init_hang ();
725 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
726 dimm_populated[dimm_num] = SDRAM_DDR1;
729 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
730 dimm_populated[dimm_num] = SDRAM_DDR2;
733 printf("ERROR: Unknown DIMM detected in slot %d.\n",
734 (unsigned int)dimm_num);
735 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
736 printf("Replace the DIMM module with a supported DIMM.\n\n");
737 spd_ddr_init_hang ();
742 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
743 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
744 && (dimm_populated[dimm_num] != SDRAM_NONE)
745 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
746 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
747 spd_ddr_init_hang ();
752 /*------------------------------------------------------------------
753 * For the memory DIMMs installed, this routine verifies that
754 * frequency previously calculated is supported.
755 *-----------------------------------------------------------------*/
756 static void check_frequency(unsigned long *dimm_populated,
757 unsigned char *iic0_dimm_addr,
758 unsigned long num_dimm_banks)
760 unsigned long dimm_num;
761 unsigned long tcyc_reg;
762 unsigned long cycle_time;
763 unsigned long calc_cycle_time;
764 unsigned long sdram_freq;
765 unsigned long sdr_ddrpll;
766 PPC4xx_SYS_INFO board_cfg;
768 /*------------------------------------------------------------------
769 * Get the board configuration info.
770 *-----------------------------------------------------------------*/
771 get_sys_info(&board_cfg);
773 mfsdr(SDR0_DDR0, sdr_ddrpll);
774 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
777 * calc_cycle_time is calculated from DDR frequency set by board/chip
778 * and is expressed in multiple of 10 picoseconds
779 * to match the way DIMM cycle time is calculated below.
781 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
783 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
784 if (dimm_populated[dimm_num] != SDRAM_NONE) {
785 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
787 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
788 * the higher order nibble (bits 4-7) designates the cycle time
789 * to a granularity of 1ns;
790 * the value presented by the lower order nibble (bits 0-3)
791 * has a granularity of .1ns and is added to the value designated
792 * by the higher nibble. In addition, four lines of the lower order
793 * nibble are assigned to support +.25,+.33, +.66 and +.75.
795 /* Convert from hex to decimal */
796 if ((tcyc_reg & 0x0F) == 0x0D)
797 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
798 else if ((tcyc_reg & 0x0F) == 0x0C)
799 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
800 else if ((tcyc_reg & 0x0F) == 0x0B)
801 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
802 else if ((tcyc_reg & 0x0F) == 0x0A)
803 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
805 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
806 ((tcyc_reg & 0x0F)*10);
807 debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
809 if (cycle_time > (calc_cycle_time + 10)) {
811 * the provided sdram cycle_time is too small
812 * for the available DIMM cycle_time.
813 * The additionnal 100ps is here to accept a small incertainty.
815 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
816 "slot %d \n while calculated cycle time is %d ps.\n",
817 (unsigned int)(cycle_time*10),
818 (unsigned int)dimm_num,
819 (unsigned int)(calc_cycle_time*10));
820 printf("Replace the DIMM, or change DDR frequency via "
821 "strapping bits.\n\n");
822 spd_ddr_init_hang ();
828 /*------------------------------------------------------------------
829 * For the memory DIMMs installed, this routine verifies two
830 * ranks/banks maximum are availables.
831 *-----------------------------------------------------------------*/
832 static void check_rank_number(unsigned long *dimm_populated,
833 unsigned char *iic0_dimm_addr,
834 unsigned long num_dimm_banks)
836 unsigned long dimm_num;
837 unsigned long dimm_rank;
838 unsigned long total_rank = 0;
840 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
841 if (dimm_populated[dimm_num] != SDRAM_NONE) {
842 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
843 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
844 dimm_rank = (dimm_rank & 0x0F) +1;
846 dimm_rank = dimm_rank & 0x0F;
849 if (dimm_rank > MAXRANKS) {
850 printf("ERROR: DRAM DIMM detected with %lu ranks in "
851 "slot %lu is not supported.\n", dimm_rank, dimm_num);
852 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
853 printf("Replace the DIMM module with a supported DIMM.\n\n");
854 spd_ddr_init_hang ();
856 total_rank += dimm_rank;
858 if (total_rank > MAXRANKS) {
859 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
860 "for all slots.\n", (unsigned int)total_rank);
861 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
862 printf("Remove one of the DIMM modules.\n\n");
863 spd_ddr_init_hang ();
868 /*------------------------------------------------------------------
869 * only support 2.5V modules.
870 * This routine verifies this.
871 *-----------------------------------------------------------------*/
872 static void check_voltage_type(unsigned long *dimm_populated,
873 unsigned char *iic0_dimm_addr,
874 unsigned long num_dimm_banks)
876 unsigned long dimm_num;
877 unsigned long voltage_type;
879 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
880 if (dimm_populated[dimm_num] != SDRAM_NONE) {
881 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
882 switch (voltage_type) {
884 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
885 printf("This DIMM is 5.0 Volt/TTL.\n");
886 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
887 (unsigned int)dimm_num);
888 spd_ddr_init_hang ();
891 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
892 printf("This DIMM is LVTTL.\n");
893 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
894 (unsigned int)dimm_num);
895 spd_ddr_init_hang ();
898 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
899 printf("This DIMM is 1.5 Volt.\n");
900 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
901 (unsigned int)dimm_num);
902 spd_ddr_init_hang ();
905 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
906 printf("This DIMM is 3.3 Volt/TTL.\n");
907 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
908 (unsigned int)dimm_num);
909 spd_ddr_init_hang ();
912 /* 2.5 Voltage only for DDR1 */
915 /* 1.8 Voltage only for DDR2 */
918 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
919 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
920 (unsigned int)dimm_num);
921 spd_ddr_init_hang ();
928 /*-----------------------------------------------------------------------------+
930 *-----------------------------------------------------------------------------*/
931 static void program_copt1(unsigned long *dimm_populated,
932 unsigned char *iic0_dimm_addr,
933 unsigned long num_dimm_banks)
935 unsigned long dimm_num;
936 unsigned long mcopt1;
937 unsigned long ecc_enabled;
938 unsigned long ecc = 0;
939 unsigned long data_width = 0;
940 unsigned long dimm_32bit;
941 unsigned long dimm_64bit;
942 unsigned long registered = 0;
943 unsigned long attribute = 0;
944 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
945 unsigned long bankcount;
946 unsigned long ddrtype;
949 #ifdef CONFIG_DDR_ECC
959 /*------------------------------------------------------------------
960 * Set memory controller options reg 1, SDRAM_MCOPT1.
961 *-----------------------------------------------------------------*/
962 mfsdram(SDRAM_MCOPT1, val);
963 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
964 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
965 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
966 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
967 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
968 SDRAM_MCOPT1_DREF_MASK);
970 mcopt1 |= SDRAM_MCOPT1_QDEP;
971 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
972 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
973 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
974 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
975 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
977 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
978 if (dimm_populated[dimm_num] != SDRAM_NONE) {
979 /* test ecc support */
980 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
981 if (ecc != 0x02) /* ecc not supported */
984 /* test bank count */
985 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
986 if (bankcount == 0x04) /* bank count = 4 */
987 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
988 else /* bank count = 8 */
989 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
992 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
993 /* test for buffered/unbuffered, registered, differential clocks */
994 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
995 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
997 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
999 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1000 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1001 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1002 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1003 if (registered == 1) { /* DDR2 always buffered */
1004 /* TODO: what about above comments ? */
1005 mcopt1 |= SDRAM_MCOPT1_RDEN;
1008 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1009 if ((attribute & 0x02) == 0x00) {
1010 /* buffered not supported */
1013 mcopt1 |= SDRAM_MCOPT1_RDEN;
1018 else if (dimm_num == 1) {
1019 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1020 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1021 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1022 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1023 if (registered == 1) {
1024 /* DDR2 always buffered */
1025 mcopt1 |= SDRAM_MCOPT1_RDEN;
1028 if ((attribute & 0x02) == 0x00) {
1029 /* buffered not supported */
1032 mcopt1 |= SDRAM_MCOPT1_RDEN;
1038 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1039 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1040 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1042 switch (data_width) {
1052 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1054 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1060 /* verify matching properties */
1061 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1063 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1064 spd_ddr_init_hang ();
1068 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1069 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1070 spd_ddr_init_hang ();
1072 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1073 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1074 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1075 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1077 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1078 spd_ddr_init_hang ();
1081 if (ecc_enabled == TRUE)
1082 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1084 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1086 mtsdram(SDRAM_MCOPT1, mcopt1);
1089 /*-----------------------------------------------------------------------------+
1091 *-----------------------------------------------------------------------------*/
1092 static void program_codt(unsigned long *dimm_populated,
1093 unsigned char *iic0_dimm_addr,
1094 unsigned long num_dimm_banks)
1097 unsigned long modt0 = 0;
1098 unsigned long modt1 = 0;
1099 unsigned long modt2 = 0;
1100 unsigned long modt3 = 0;
1101 unsigned char dimm_num;
1102 unsigned char dimm_rank;
1103 unsigned char total_rank = 0;
1104 unsigned char total_dimm = 0;
1105 unsigned char dimm_type = 0;
1106 unsigned char firstSlot = 0;
1108 /*------------------------------------------------------------------
1109 * Set the SDRAM Controller On Die Termination Register
1110 *-----------------------------------------------------------------*/
1111 mfsdram(SDRAM_CODT, codt);
1112 codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1113 codt |= SDRAM_CODT_IO_NMODE;
1115 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1116 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1117 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1118 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1119 dimm_rank = (dimm_rank & 0x0F) + 1;
1120 dimm_type = SDRAM_DDR2;
1122 dimm_rank = dimm_rank & 0x0F;
1123 dimm_type = SDRAM_DDR1;
1126 total_rank += dimm_rank;
1128 if ((dimm_num == 0) && (total_dimm == 1))
1134 if (dimm_type == SDRAM_DDR2) {
1135 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1136 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1137 if (total_rank == 1) { /* PUUU */
1138 codt |= CALC_ODT_R(0);
1139 modt0 = CALC_ODT_W(0);
1144 if (total_rank == 2) { /* PPUU */
1145 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1146 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1151 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1152 if (total_rank == 1) { /* UUPU */
1153 codt |= CALC_ODT_R(2);
1156 modt2 = CALC_ODT_W(2);
1159 if (total_rank == 2) { /* UUPP */
1160 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1163 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1167 if (total_dimm == 2) {
1168 if (total_rank == 2) { /* PUPU */
1169 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1170 modt0 = CALC_ODT_RW(2);
1172 modt2 = CALC_ODT_RW(0);
1175 if (total_rank == 4) { /* PPPP */
1176 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1177 CALC_ODT_R(2) | CALC_ODT_R(3);
1178 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1180 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1185 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1191 if (total_dimm == 1) {
1192 if (total_rank == 1)
1194 if (total_rank == 2)
1197 if (total_dimm == 2) {
1198 if (total_rank == 2)
1200 if (total_rank == 4)
1205 debug("nb of dimm %d\n", total_dimm);
1206 debug("nb of rank %d\n", total_rank);
1207 if (total_dimm == 1)
1208 debug("dimm in slot %d\n", firstSlot);
1210 mtsdram(SDRAM_CODT, codt);
1211 mtsdram(SDRAM_MODT0, modt0);
1212 mtsdram(SDRAM_MODT1, modt1);
1213 mtsdram(SDRAM_MODT2, modt2);
1214 mtsdram(SDRAM_MODT3, modt3);
1217 /*-----------------------------------------------------------------------------+
1219 *-----------------------------------------------------------------------------*/
1220 static void program_initplr(unsigned long *dimm_populated,
1221 unsigned char *iic0_dimm_addr,
1222 unsigned long num_dimm_banks,
1223 ddr_cas_id_t selected_cas,
1237 /******************************************************
1238 ** Assumption: if more than one DIMM, all DIMMs are the same
1239 ** as already checked in check_memory_type
1240 ******************************************************/
1242 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1243 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1244 mtsdram(SDRAM_INITPLR1, 0x81900400);
1245 mtsdram(SDRAM_INITPLR2, 0x81810000);
1246 mtsdram(SDRAM_INITPLR3, 0xff800162);
1247 mtsdram(SDRAM_INITPLR4, 0x81900400);
1248 mtsdram(SDRAM_INITPLR5, 0x86080000);
1249 mtsdram(SDRAM_INITPLR6, 0x86080000);
1250 mtsdram(SDRAM_INITPLR7, 0x81000062);
1251 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1252 switch (selected_cas) {
1263 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1264 spd_ddr_init_hang ();
1270 * ToDo - Still a problem with the write recovery:
1271 * On the Corsair CM2X512-5400C4 module, setting write recovery
1272 * in the INITPLR reg to the value calculated in program_mode()
1273 * results in not correctly working DDR2 memory (crash after
1276 * So for now, set the write recovery to 3. This seems to work
1277 * on the Corair module too.
1281 switch (write_recovery) {
1295 printf("ERROR: write recovery not support (%d)", write_recovery);
1296 spd_ddr_init_hang ();
1300 wr = WRITE_RECOV_3; /* test-only, see description above */
1303 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1304 if (dimm_populated[dimm_num] != SDRAM_NONE)
1306 if (total_dimm == 1) {
1309 } else if (total_dimm == 2) {
1313 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1314 spd_ddr_init_hang ();
1317 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1318 emr = CMD_EMR | SELECT_EMR | odt | ods;
1319 emr2 = CMD_EMR | SELECT_EMR2;
1320 emr3 = CMD_EMR | SELECT_EMR3;
1321 /* NOP - Wait 106 MemClk cycles */
1322 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1323 SDRAM_INITPLR_IMWT_ENCODE(106));
1325 /* precharge 4 MemClk cycles */
1326 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1327 SDRAM_INITPLR_IMWT_ENCODE(4));
1328 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1329 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1330 SDRAM_INITPLR_IMWT_ENCODE(2));
1331 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1332 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1333 SDRAM_INITPLR_IMWT_ENCODE(2));
1334 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1335 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1336 SDRAM_INITPLR_IMWT_ENCODE(2));
1337 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1338 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1339 SDRAM_INITPLR_IMWT_ENCODE(200));
1341 /* precharge 4 MemClk cycles */
1342 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1343 SDRAM_INITPLR_IMWT_ENCODE(4));
1344 /* Refresh 25 MemClk cycles */
1345 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1346 SDRAM_INITPLR_IMWT_ENCODE(25));
1347 /* Refresh 25 MemClk cycles */
1348 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1349 SDRAM_INITPLR_IMWT_ENCODE(25));
1350 /* Refresh 25 MemClk cycles */
1351 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1352 SDRAM_INITPLR_IMWT_ENCODE(25));
1353 /* Refresh 25 MemClk cycles */
1354 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1355 SDRAM_INITPLR_IMWT_ENCODE(25));
1356 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1357 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1358 SDRAM_INITPLR_IMWT_ENCODE(2));
1359 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1360 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1361 SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1363 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1364 SDRAM_INITPLR_IMWT_ENCODE(2));
1366 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1367 spd_ddr_init_hang ();
1371 /*------------------------------------------------------------------
1372 * This routine programs the SDRAM_MMODE register.
1373 * the selected_cas is an output parameter, that will be passed
1374 * by caller to call the above program_initplr( )
1375 *-----------------------------------------------------------------*/
1376 static void program_mode(unsigned long *dimm_populated,
1377 unsigned char *iic0_dimm_addr,
1378 unsigned long num_dimm_banks,
1379 ddr_cas_id_t *selected_cas,
1380 int *write_recovery)
1382 unsigned long dimm_num;
1383 unsigned long sdram_ddr1;
1384 unsigned long t_wr_ns;
1385 unsigned long t_wr_clk;
1386 unsigned long cas_bit;
1387 unsigned long cas_index;
1388 unsigned long sdram_freq;
1389 unsigned long ddr_check;
1390 unsigned long mmode;
1391 unsigned long tcyc_reg;
1392 unsigned long cycle_2_0_clk;
1393 unsigned long cycle_2_5_clk;
1394 unsigned long cycle_3_0_clk;
1395 unsigned long cycle_4_0_clk;
1396 unsigned long cycle_5_0_clk;
1397 unsigned long max_2_0_tcyc_ns_x_100;
1398 unsigned long max_2_5_tcyc_ns_x_100;
1399 unsigned long max_3_0_tcyc_ns_x_100;
1400 unsigned long max_4_0_tcyc_ns_x_100;
1401 unsigned long max_5_0_tcyc_ns_x_100;
1402 unsigned long cycle_time_ns_x_100[3];
1403 PPC4xx_SYS_INFO board_cfg;
1404 unsigned char cas_2_0_available;
1405 unsigned char cas_2_5_available;
1406 unsigned char cas_3_0_available;
1407 unsigned char cas_4_0_available;
1408 unsigned char cas_5_0_available;
1409 unsigned long sdr_ddrpll;
1411 /*------------------------------------------------------------------
1412 * Get the board configuration info.
1413 *-----------------------------------------------------------------*/
1414 get_sys_info(&board_cfg);
1416 mfsdr(SDR0_DDR0, sdr_ddrpll);
1417 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1418 debug("sdram_freq=%lu\n", sdram_freq);
1420 /*------------------------------------------------------------------
1421 * Handle the timing. We need to find the worst case timing of all
1422 * the dimm modules installed.
1423 *-----------------------------------------------------------------*/
1425 cas_2_0_available = TRUE;
1426 cas_2_5_available = TRUE;
1427 cas_3_0_available = TRUE;
1428 cas_4_0_available = TRUE;
1429 cas_5_0_available = TRUE;
1430 max_2_0_tcyc_ns_x_100 = 10;
1431 max_2_5_tcyc_ns_x_100 = 10;
1432 max_3_0_tcyc_ns_x_100 = 10;
1433 max_4_0_tcyc_ns_x_100 = 10;
1434 max_5_0_tcyc_ns_x_100 = 10;
1437 /* loop through all the DIMM slots on the board */
1438 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1439 /* If a dimm is installed in a particular slot ... */
1440 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1441 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1446 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1447 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1448 debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1450 /* For a particular DIMM, grab the three CAS values it supports */
1451 for (cas_index = 0; cas_index < 3; cas_index++) {
1452 switch (cas_index) {
1454 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1457 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1460 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1464 if ((tcyc_reg & 0x0F) >= 10) {
1465 if ((tcyc_reg & 0x0F) == 0x0D) {
1466 /* Convert from hex to decimal */
1467 cycle_time_ns_x_100[cas_index] =
1468 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1470 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1471 "in slot %d\n", (unsigned int)dimm_num);
1472 spd_ddr_init_hang ();
1475 /* Convert from hex to decimal */
1476 cycle_time_ns_x_100[cas_index] =
1477 (((tcyc_reg & 0xF0) >> 4) * 100) +
1478 ((tcyc_reg & 0x0F)*10);
1480 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1481 cycle_time_ns_x_100[cas_index]);
1484 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1485 /* supported for a particular DIMM. */
1490 * DDR devices use the following bitmask for CAS latency:
1491 * Bit 7 6 5 4 3 2 1 0
1492 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1494 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1495 (cycle_time_ns_x_100[cas_index] != 0)) {
1496 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1497 cycle_time_ns_x_100[cas_index]);
1502 cas_4_0_available = FALSE;
1505 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1506 (cycle_time_ns_x_100[cas_index] != 0)) {
1507 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1508 cycle_time_ns_x_100[cas_index]);
1513 cas_3_0_available = FALSE;
1516 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1517 (cycle_time_ns_x_100[cas_index] != 0)) {
1518 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1519 cycle_time_ns_x_100[cas_index]);
1524 cas_2_5_available = FALSE;
1527 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1528 (cycle_time_ns_x_100[cas_index] != 0)) {
1529 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1530 cycle_time_ns_x_100[cas_index]);
1535 cas_2_0_available = FALSE;
1539 * DDR2 devices use the following bitmask for CAS latency:
1540 * Bit 7 6 5 4 3 2 1 0
1541 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1543 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1544 (cycle_time_ns_x_100[cas_index] != 0)) {
1545 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1546 cycle_time_ns_x_100[cas_index]);
1551 cas_5_0_available = FALSE;
1554 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1555 (cycle_time_ns_x_100[cas_index] != 0)) {
1556 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1557 cycle_time_ns_x_100[cas_index]);
1562 cas_4_0_available = FALSE;
1565 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1566 (cycle_time_ns_x_100[cas_index] != 0)) {
1567 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1568 cycle_time_ns_x_100[cas_index]);
1573 cas_3_0_available = FALSE;
1579 /*------------------------------------------------------------------
1580 * Set the SDRAM mode, SDRAM_MMODE
1581 *-----------------------------------------------------------------*/
1582 mfsdram(SDRAM_MMODE, mmode);
1583 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1585 /* add 10 here because of rounding problems */
1586 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1587 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1588 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1589 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1590 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1591 debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1592 debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1593 debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1595 if (sdram_ddr1 == TRUE) { /* DDR1 */
1596 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1597 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1598 *selected_cas = DDR_CAS_2;
1599 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1600 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1601 *selected_cas = DDR_CAS_2_5;
1602 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1603 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1604 *selected_cas = DDR_CAS_3;
1606 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1607 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1608 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1609 spd_ddr_init_hang ();
1612 debug("cas_3_0_available=%d\n", cas_3_0_available);
1613 debug("cas_4_0_available=%d\n", cas_4_0_available);
1614 debug("cas_5_0_available=%d\n", cas_5_0_available);
1615 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1616 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1617 *selected_cas = DDR_CAS_3;
1618 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1619 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1620 *selected_cas = DDR_CAS_4;
1621 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1622 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1623 *selected_cas = DDR_CAS_5;
1625 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1626 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1627 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1628 printf("cas3=%d cas4=%d cas5=%d\n",
1629 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1630 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1631 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1632 spd_ddr_init_hang ();
1636 if (sdram_ddr1 == TRUE)
1637 mmode |= SDRAM_MMODE_WR_DDR1;
1640 /* loop through all the DIMM slots on the board */
1641 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1642 /* If a dimm is installed in a particular slot ... */
1643 if (dimm_populated[dimm_num] != SDRAM_NONE)
1644 t_wr_ns = max(t_wr_ns,
1645 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1649 * convert from nanoseconds to ddr clocks
1650 * round up if necessary
1652 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1653 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1654 if (sdram_freq != ddr_check)
1662 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1665 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1668 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1671 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1674 *write_recovery = t_wr_clk;
1677 debug("CAS latency = %d\n", *selected_cas);
1678 debug("Write recovery = %d\n", *write_recovery);
1680 mtsdram(SDRAM_MMODE, mmode);
1683 /*-----------------------------------------------------------------------------+
1685 *-----------------------------------------------------------------------------*/
1686 static void program_rtr(unsigned long *dimm_populated,
1687 unsigned char *iic0_dimm_addr,
1688 unsigned long num_dimm_banks)
1690 PPC4xx_SYS_INFO board_cfg;
1691 unsigned long max_refresh_rate;
1692 unsigned long dimm_num;
1693 unsigned long refresh_rate_type;
1694 unsigned long refresh_rate;
1696 unsigned long sdram_freq;
1697 unsigned long sdr_ddrpll;
1700 /*------------------------------------------------------------------
1701 * Get the board configuration info.
1702 *-----------------------------------------------------------------*/
1703 get_sys_info(&board_cfg);
1705 /*------------------------------------------------------------------
1706 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1707 *-----------------------------------------------------------------*/
1708 mfsdr(SDR0_DDR0, sdr_ddrpll);
1709 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1711 max_refresh_rate = 0;
1712 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1713 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1715 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1716 refresh_rate_type &= 0x7F;
1717 switch (refresh_rate_type) {
1719 refresh_rate = 15625;
1722 refresh_rate = 3906;
1725 refresh_rate = 7812;
1728 refresh_rate = 31250;
1731 refresh_rate = 62500;
1734 refresh_rate = 125000;
1738 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1739 (unsigned int)dimm_num);
1740 printf("Replace the DIMM module with a supported DIMM.\n\n");
1741 spd_ddr_init_hang ();
1745 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1749 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1750 mfsdram(SDRAM_RTR, val);
1751 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1752 (SDRAM_RTR_RINT_ENCODE(rint)));
1755 /*------------------------------------------------------------------
1756 * This routine programs the SDRAM_TRx registers.
1757 *-----------------------------------------------------------------*/
1758 static void program_tr(unsigned long *dimm_populated,
1759 unsigned char *iic0_dimm_addr,
1760 unsigned long num_dimm_banks)
1762 unsigned long dimm_num;
1763 unsigned long sdram_ddr1;
1764 unsigned long t_rp_ns;
1765 unsigned long t_rcd_ns;
1766 unsigned long t_rrd_ns;
1767 unsigned long t_ras_ns;
1768 unsigned long t_rc_ns;
1769 unsigned long t_rfc_ns;
1770 unsigned long t_wpc_ns;
1771 unsigned long t_wtr_ns;
1772 unsigned long t_rpc_ns;
1773 unsigned long t_rp_clk;
1774 unsigned long t_rcd_clk;
1775 unsigned long t_rrd_clk;
1776 unsigned long t_ras_clk;
1777 unsigned long t_rc_clk;
1778 unsigned long t_rfc_clk;
1779 unsigned long t_wpc_clk;
1780 unsigned long t_wtr_clk;
1781 unsigned long t_rpc_clk;
1782 unsigned long sdtr1, sdtr2, sdtr3;
1783 unsigned long ddr_check;
1784 unsigned long sdram_freq;
1785 unsigned long sdr_ddrpll;
1787 PPC4xx_SYS_INFO board_cfg;
1789 /*------------------------------------------------------------------
1790 * Get the board configuration info.
1791 *-----------------------------------------------------------------*/
1792 get_sys_info(&board_cfg);
1794 mfsdr(SDR0_DDR0, sdr_ddrpll);
1795 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1797 /*------------------------------------------------------------------
1798 * Handle the timing. We need to find the worst case timing of all
1799 * the dimm modules installed.
1800 *-----------------------------------------------------------------*/
1812 /* loop through all the DIMM slots on the board */
1813 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1814 /* If a dimm is installed in a particular slot ... */
1815 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1816 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1821 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1822 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1823 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1824 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1825 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1826 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1830 /*------------------------------------------------------------------
1831 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1832 *-----------------------------------------------------------------*/
1833 mfsdram(SDRAM_SDTR1, sdtr1);
1834 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1835 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1837 /* default values */
1838 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1839 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1841 /* normal operations */
1842 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1843 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1845 mtsdram(SDRAM_SDTR1, sdtr1);
1847 /*------------------------------------------------------------------
1848 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1849 *-----------------------------------------------------------------*/
1850 mfsdram(SDRAM_SDTR2, sdtr2);
1851 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1852 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1853 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1854 SDRAM_SDTR2_RRD_MASK);
1857 * convert t_rcd from nanoseconds to ddr clocks
1858 * round up if necessary
1860 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1861 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1862 if (sdram_freq != ddr_check)
1865 switch (t_rcd_clk) {
1868 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1871 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1874 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1877 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1880 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1884 if (sdram_ddr1 == TRUE) { /* DDR1 */
1885 if (sdram_freq < 200000000) {
1886 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1887 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1888 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1890 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1891 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1892 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1895 /* loop through all the DIMM slots on the board */
1896 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1897 /* If a dimm is installed in a particular slot ... */
1898 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1899 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1900 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1901 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1906 * convert from nanoseconds to ddr clocks
1907 * round up if necessary
1909 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1910 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1911 if (sdram_freq != ddr_check)
1914 switch (t_wpc_clk) {
1918 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1921 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1924 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1927 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1930 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1935 * convert from nanoseconds to ddr clocks
1936 * round up if necessary
1938 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1939 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1940 if (sdram_freq != ddr_check)
1943 switch (t_wtr_clk) {
1946 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1949 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1952 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1955 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1960 * convert from nanoseconds to ddr clocks
1961 * round up if necessary
1963 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1964 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1965 if (sdram_freq != ddr_check)
1968 switch (t_rpc_clk) {
1972 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1975 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1978 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1984 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1987 * convert t_rrd from nanoseconds to ddr clocks
1988 * round up if necessary
1990 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1991 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1992 if (sdram_freq != ddr_check)
1996 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1998 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2001 * convert t_rp from nanoseconds to ddr clocks
2002 * round up if necessary
2004 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2005 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2006 if (sdram_freq != ddr_check)
2014 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2017 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2020 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2023 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2026 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2030 mtsdram(SDRAM_SDTR2, sdtr2);
2032 /*------------------------------------------------------------------
2033 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2034 *-----------------------------------------------------------------*/
2035 mfsdram(SDRAM_SDTR3, sdtr3);
2036 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2037 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2040 * convert t_ras from nanoseconds to ddr clocks
2041 * round up if necessary
2043 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2044 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2045 if (sdram_freq != ddr_check)
2048 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2051 * convert t_rc from nanoseconds to ddr clocks
2052 * round up if necessary
2054 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2055 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2056 if (sdram_freq != ddr_check)
2059 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2061 /* default xcs value */
2062 sdtr3 |= SDRAM_SDTR3_XCS;
2065 * convert t_rfc from nanoseconds to ddr clocks
2066 * round up if necessary
2068 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2069 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2070 if (sdram_freq != ddr_check)
2073 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2075 mtsdram(SDRAM_SDTR3, sdtr3);
2078 /*-----------------------------------------------------------------------------+
2080 *-----------------------------------------------------------------------------*/
2081 static void program_bxcf(unsigned long *dimm_populated,
2082 unsigned char *iic0_dimm_addr,
2083 unsigned long num_dimm_banks)
2085 unsigned long dimm_num;
2086 unsigned long num_col_addr;
2087 unsigned long num_ranks;
2088 unsigned long num_banks;
2090 unsigned long ind_rank;
2092 unsigned long ind_bank;
2093 unsigned long bank_0_populated;
2095 /*------------------------------------------------------------------
2096 * Set the BxCF regs. First, wipe out the bank config registers.
2097 *-----------------------------------------------------------------*/
2098 mtsdram(SDRAM_MB0CF, 0x00000000);
2099 mtsdram(SDRAM_MB1CF, 0x00000000);
2100 mtsdram(SDRAM_MB2CF, 0x00000000);
2101 mtsdram(SDRAM_MB3CF, 0x00000000);
2103 mode = SDRAM_BXCF_M_BE_ENABLE;
2105 bank_0_populated = 0;
2107 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2108 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2109 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2110 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2111 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2112 num_ranks = (num_ranks & 0x0F) +1;
2114 num_ranks = num_ranks & 0x0F;
2116 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2118 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2123 switch (num_col_addr) {
2125 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2128 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2131 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2134 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2137 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2140 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2141 (unsigned int)dimm_num);
2142 printf("ERROR: Unsupported value for number of "
2143 "column addresses: %d.\n", (unsigned int)num_col_addr);
2144 printf("Replace the DIMM module with a supported DIMM.\n\n");
2145 spd_ddr_init_hang ();
2149 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2150 bank_0_populated = 1;
2152 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2153 mtsdram(SDRAM_MB0CF +
2154 ((dimm_num + bank_0_populated + ind_rank) << 2),
2161 /*------------------------------------------------------------------
2162 * program memory queue.
2163 *-----------------------------------------------------------------*/
2164 static void program_memory_queue(unsigned long *dimm_populated,
2165 unsigned char *iic0_dimm_addr,
2166 unsigned long num_dimm_banks)
2168 unsigned long dimm_num;
2169 phys_size_t rank_base_addr;
2170 unsigned long rank_reg;
2171 phys_size_t rank_size_bytes;
2172 unsigned long rank_size_id;
2173 unsigned long num_ranks;
2174 unsigned long baseadd_size;
2176 unsigned long bank_0_populated = 0;
2177 phys_size_t total_size = 0;
2179 /*------------------------------------------------------------------
2180 * Reset the rank_base_address.
2181 *-----------------------------------------------------------------*/
2182 rank_reg = SDRAM_R0BAS;
2184 rank_base_addr = 0x00000000;
2186 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2187 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2188 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2189 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2190 num_ranks = (num_ranks & 0x0F) + 1;
2192 num_ranks = num_ranks & 0x0F;
2194 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2196 /*------------------------------------------------------------------
2198 *-----------------------------------------------------------------*/
2200 switch (rank_size_id) {
2202 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2206 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2210 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2214 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2218 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2222 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2226 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2230 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2234 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2235 (unsigned int)dimm_num);
2236 printf("ERROR: Unsupported value for the banksize: %d.\n",
2237 (unsigned int)rank_size_id);
2238 printf("Replace the DIMM module with a supported DIMM.\n\n");
2239 spd_ddr_init_hang ();
2241 rank_size_bytes = total_size << 20;
2243 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2244 bank_0_populated = 1;
2246 for (i = 0; i < num_ranks; i++) {
2247 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2248 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2250 rank_base_addr += rank_size_bytes;
2255 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2256 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2257 defined(CONFIG_460SX)
2259 * Enable high bandwidth access
2260 * This is currently not used, but with this setup
2261 * it is possible to use it later on in e.g. the Linux
2262 * EMAC driver for performance gain.
2264 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2265 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2268 * Set optimal value for Memory Queue HB/LL Configuration registers
2270 mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2271 SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2272 SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2273 mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2274 SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2275 SDRAM_CONF1LL_RPLM);
2276 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2280 /*-----------------------------------------------------------------------------+
2282 *-----------------------------------------------------------------------------*/
2283 static unsigned long is_ecc_enabled(void)
2285 unsigned long dimm_num;
2290 /* loop through all the DIMM slots on the board */
2291 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2292 mfsdram(SDRAM_MCOPT1, val);
2293 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2299 #ifdef CONFIG_DDR_ECC
2300 /*-----------------------------------------------------------------------------+
2302 *-----------------------------------------------------------------------------*/
2303 static void program_ecc(unsigned long *dimm_populated,
2304 unsigned char *iic0_dimm_addr,
2305 unsigned long num_dimm_banks,
2306 unsigned long tlb_word2_i_value)
2308 unsigned long mcopt1;
2309 unsigned long mcopt2;
2310 unsigned long mcstat;
2311 unsigned long dimm_num;
2315 /* loop through all the DIMM slots on the board */
2316 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2317 /* If a dimm is installed in a particular slot ... */
2318 if (dimm_populated[dimm_num] != SDRAM_NONE)
2319 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2324 if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2325 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2329 mfsdram(SDRAM_MCOPT1, mcopt1);
2330 mfsdram(SDRAM_MCOPT2, mcopt2);
2332 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2333 /* DDR controller must be enabled and not in self-refresh. */
2334 mfsdram(SDRAM_MCSTAT, mcstat);
2335 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2336 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2337 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2338 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2340 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2347 static void wait_ddr_idle(void)
2352 mfsdram(SDRAM_MCSTAT, val);
2353 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2356 /*-----------------------------------------------------------------------------+
2358 *-----------------------------------------------------------------------------*/
2359 static void program_ecc_addr(unsigned long start_address,
2360 unsigned long num_bytes,
2361 unsigned long tlb_word2_i_value)
2363 unsigned long current_address;
2364 unsigned long end_address;
2365 unsigned long address_increment;
2366 unsigned long mcopt1;
2367 char str[] = "ECC generation -";
2368 char slash[] = "\\|/-\\|/-";
2372 current_address = start_address;
2373 mfsdram(SDRAM_MCOPT1, mcopt1);
2374 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2375 mtsdram(SDRAM_MCOPT1,
2376 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2382 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2383 /* ECC bit set method for non-cached memory */
2384 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2385 address_increment = 4;
2387 address_increment = 8;
2388 end_address = current_address + num_bytes;
2390 while (current_address < end_address) {
2391 *((unsigned long *)current_address) = 0x00000000;
2392 current_address += address_increment;
2394 if ((loop++ % (2 << 20)) == 0) {
2396 putc(slash[loopi++ % 8]);
2401 /* ECC bit set method for cached memory */
2402 dcbz_area(start_address, num_bytes);
2403 /* Write modified dcache lines back to memory */
2404 clean_dcache_range(start_address, start_address + num_bytes);
2407 blank_string(strlen(str));
2413 /* clear ECC error repoting registers */
2414 mtsdram(SDRAM_ECCCR, 0xffffffff);
2415 mtdcr(0x4c, 0xffffffff);
2417 mtsdram(SDRAM_MCOPT1,
2418 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2426 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2427 /*-----------------------------------------------------------------------------+
2428 * program_DQS_calibration.
2429 *-----------------------------------------------------------------------------*/
2430 static void program_DQS_calibration(unsigned long *dimm_populated,
2431 unsigned char *iic0_dimm_addr,
2432 unsigned long num_dimm_banks)
2436 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2437 mtsdram(SDRAM_RQDC, 0x80000037);
2438 mtsdram(SDRAM_RDCC, 0x40000000);
2439 mtsdram(SDRAM_RFDC, 0x000001DF);
2443 /*------------------------------------------------------------------
2444 * Program RDCC register
2445 * Read sample cycle auto-update enable
2446 *-----------------------------------------------------------------*/
2448 mfsdram(SDRAM_RDCC, val);
2450 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2451 | SDRAM_RDCC_RSAE_ENABLE);
2453 /*------------------------------------------------------------------
2454 * Program RQDC register
2455 * Internal DQS delay mechanism enable
2456 *-----------------------------------------------------------------*/
2457 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2459 /*------------------------------------------------------------------
2460 * Program RFDC register
2461 * Set Feedback Fractional Oversample
2462 * Auto-detect read sample cycle enable
2463 * Set RFOS to 1/4 of memclk cycle (0x3f)
2464 *-----------------------------------------------------------------*/
2465 mfsdram(SDRAM_RFDC, val);
2467 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2468 SDRAM_RFDC_RFFD_MASK))
2469 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2470 SDRAM_RFDC_RFFD_ENCODE(0)));
2472 DQS_calibration_process();
2476 static int short_mem_test(void)
2483 phys_size_t base_addr;
2484 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2485 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2486 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2487 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2488 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2489 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2490 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2491 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2492 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2493 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2494 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2495 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2496 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2497 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2498 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2499 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2500 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2503 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2504 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2507 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2508 /* Bank is enabled */
2511 * Only run test on accessable memory (below 2GB)
2513 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2514 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2517 /*------------------------------------------------------------------
2518 * Run the short memory test.
2519 *-----------------------------------------------------------------*/
2520 membase = (u32 *)(u32)base_addr;
2522 for (i = 0; i < NUMMEMTESTS; i++) {
2523 for (j = 0; j < NUMMEMWORDS; j++) {
2524 membase[j] = test[i][j];
2525 ppcDcbf((u32)&(membase[j]));
2528 for (l=0; l<NUMLOOPS; l++) {
2529 for (j = 0; j < NUMMEMWORDS; j++) {
2530 if (membase[j] != test[i][j]) {
2531 ppcDcbf((u32)&(membase[j]));
2534 ppcDcbf((u32)&(membase[j]));
2539 } /* if bank enabled */
2540 } /* for bxcf_num */
2545 #ifndef HARD_CODED_DQS
2546 /*-----------------------------------------------------------------------------+
2547 * DQS_calibration_process.
2548 *-----------------------------------------------------------------------------*/
2549 static void DQS_calibration_process(void)
2551 unsigned long rfdc_reg;
2557 unsigned long begin_rqfd[MAXRANKS];
2558 unsigned long begin_rffd[MAXRANKS];
2559 unsigned long end_rqfd[MAXRANKS];
2560 unsigned long end_rffd[MAXRANKS];
2562 unsigned long dlycal;
2563 unsigned long dly_val;
2564 unsigned long max_pass_length;
2565 unsigned long current_pass_length;
2566 unsigned long current_fail_length;
2567 unsigned long current_start;
2569 unsigned char fail_found;
2570 unsigned char pass_found;
2571 #if !defined(CONFIG_DDR_RQDC_FIXED)
2577 char str[] = "Auto calibration -";
2578 char slash[] = "\\|/-\\|/-";
2580 /*------------------------------------------------------------------
2581 * Test to determine the best read clock delay tuning bits.
2583 * Before the DDR controller can be used, the read clock delay needs to be
2584 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2585 * This value cannot be hardcoded into the program because it changes
2586 * depending on the board's setup and environment.
2587 * To do this, all delay values are tested to see if they
2588 * work or not. By doing this, you get groups of fails with groups of
2589 * passing values. The idea is to find the start and end of a passing
2590 * window and take the center of it to use as the read clock delay.
2592 * A failure has to be seen first so that when we hit a pass, we know
2593 * that it is truely the start of the window. If we get passing values
2594 * to start off with, we don't know if we are at the start of the window.
2596 * The code assumes that a failure will always be found.
2597 * If a failure is not found, there is no easy way to get the middle
2598 * of the passing window. I guess we can pretty much pick any value
2599 * but some values will be better than others. Since the lowest speed
2600 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2601 * from experimentation it is safe to say you will always have a failure.
2602 *-----------------------------------------------------------------*/
2604 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2605 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2610 mfsdram(SDRAM_RQDC, rqdc_reg);
2611 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2612 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2613 #else /* CONFIG_DDR_RQDC_FIXED */
2615 * On Katmai the complete auto-calibration somehow doesn't seem to
2616 * produce the best results, meaning optimal values for RQFD/RFFD.
2617 * This was discovered by GDA using a high bandwidth scope,
2618 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2619 * so now on Katmai "only" RFFD is auto-calibrated.
2621 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2622 #endif /* CONFIG_DDR_RQDC_FIXED */
2634 window_found = FALSE;
2636 max_pass_length = 0;
2639 current_pass_length = 0;
2640 current_fail_length = 0;
2642 window_found = FALSE;
2647 * get the delay line calibration register value
2649 mfsdram(SDRAM_DLCR, dlycal);
2650 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2652 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2653 mfsdram(SDRAM_RFDC, rfdc_reg);
2654 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2656 /*------------------------------------------------------------------
2657 * Set the timing reg for the test.
2658 *-----------------------------------------------------------------*/
2659 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2661 /*------------------------------------------------------------------
2662 * See if the rffd value passed.
2663 *-----------------------------------------------------------------*/
2664 if (short_mem_test()) {
2665 if (fail_found == TRUE) {
2667 if (current_pass_length == 0)
2668 current_start = rffd;
2670 current_fail_length = 0;
2671 current_pass_length++;
2673 if (current_pass_length > max_pass_length) {
2674 max_pass_length = current_pass_length;
2675 max_start = current_start;
2680 current_pass_length = 0;
2681 current_fail_length++;
2683 if (current_fail_length >= (dly_val >> 2)) {
2684 if (fail_found == FALSE) {
2686 } else if (pass_found == TRUE) {
2687 window_found = TRUE;
2694 /*------------------------------------------------------------------
2695 * Set the average RFFD value
2696 *-----------------------------------------------------------------*/
2697 rffd_average = ((max_start + max_end) >> 1);
2699 if (rffd_average < 0)
2702 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2703 rffd_average = SDRAM_RFDC_RFFD_MAX;
2704 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2705 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2707 #if !defined(CONFIG_DDR_RQDC_FIXED)
2708 max_pass_length = 0;
2711 current_pass_length = 0;
2712 current_fail_length = 0;
2714 window_found = FALSE;
2718 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2719 mfsdram(SDRAM_RQDC, rqdc_reg);
2720 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2722 /*------------------------------------------------------------------
2723 * Set the timing reg for the test.
2724 *-----------------------------------------------------------------*/
2725 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2727 /*------------------------------------------------------------------
2728 * See if the rffd value passed.
2729 *-----------------------------------------------------------------*/
2730 if (short_mem_test()) {
2731 if (fail_found == TRUE) {
2733 if (current_pass_length == 0)
2734 current_start = rqfd;
2736 current_fail_length = 0;
2737 current_pass_length++;
2739 if (current_pass_length > max_pass_length) {
2740 max_pass_length = current_pass_length;
2741 max_start = current_start;
2746 current_pass_length = 0;
2747 current_fail_length++;
2749 if (fail_found == FALSE) {
2751 } else if (pass_found == TRUE) {
2752 window_found = TRUE;
2758 rqfd_average = ((max_start + max_end) >> 1);
2760 /*------------------------------------------------------------------
2761 * Make sure we found the valid read passing window. Halt if not
2762 *-----------------------------------------------------------------*/
2763 if (window_found == FALSE) {
2764 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2766 putc(slash[loopi++ % 8]);
2768 /* try again from with a different RQFD start value */
2770 goto calibration_loop;
2773 printf("\nERROR: Cannot determine a common read delay for the "
2774 "DIMM(s) installed.\n");
2775 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2776 ppc4xx_ibm_ddr2_register_dump();
2777 spd_ddr_init_hang ();
2780 if (rqfd_average < 0)
2783 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2784 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2787 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2788 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2790 blank_string(strlen(str));
2791 #endif /* CONFIG_DDR_RQDC_FIXED */
2794 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2795 * PowerPC440SP/SPe DDR2 application note:
2796 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2798 mfsdram(SDRAM_RTSR, val);
2799 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2800 mfsdram(SDRAM_RDCC, val);
2801 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2803 mtsdram(SDRAM_RDCC, val);
2807 mfsdram(SDRAM_DLCR, val);
2808 debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2809 mfsdram(SDRAM_RQDC, val);
2810 debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2811 mfsdram(SDRAM_RFDC, val);
2812 debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2813 mfsdram(SDRAM_RDCC, val);
2814 debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2816 #else /* calibration test with hardvalues */
2817 /*-----------------------------------------------------------------------------+
2818 * DQS_calibration_process.
2819 *-----------------------------------------------------------------------------*/
2820 static void test(void)
2822 unsigned long dimm_num;
2823 unsigned long ecc_temp;
2825 unsigned long *membase;
2826 unsigned long bxcf[MAXRANKS];
2829 char begin_found[MAXDIMMS];
2830 char end_found[MAXDIMMS];
2831 char search_end[MAXDIMMS];
2832 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2833 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2834 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2835 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2836 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2837 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2838 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2839 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2840 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2841 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2842 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2843 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2844 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2845 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2846 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2847 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2848 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2850 /*------------------------------------------------------------------
2851 * Test to determine the best read clock delay tuning bits.
2853 * Before the DDR controller can be used, the read clock delay needs to be
2854 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2855 * This value cannot be hardcoded into the program because it changes
2856 * depending on the board's setup and environment.
2857 * To do this, all delay values are tested to see if they
2858 * work or not. By doing this, you get groups of fails with groups of
2859 * passing values. The idea is to find the start and end of a passing
2860 * window and take the center of it to use as the read clock delay.
2862 * A failure has to be seen first so that when we hit a pass, we know
2863 * that it is truely the start of the window. If we get passing values
2864 * to start off with, we don't know if we are at the start of the window.
2866 * The code assumes that a failure will always be found.
2867 * If a failure is not found, there is no easy way to get the middle
2868 * of the passing window. I guess we can pretty much pick any value
2869 * but some values will be better than others. Since the lowest speed
2870 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2871 * from experimentation it is safe to say you will always have a failure.
2872 *-----------------------------------------------------------------*/
2873 mfsdram(SDRAM_MCOPT1, ecc_temp);
2874 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2875 mfsdram(SDRAM_MCOPT1, val);
2876 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2877 SDRAM_MCOPT1_MCHK_NON);
2879 window_found = FALSE;
2880 begin_found[0] = FALSE;
2881 end_found[0] = FALSE;
2882 search_end[0] = FALSE;
2883 begin_found[1] = FALSE;
2884 end_found[1] = FALSE;
2885 search_end[1] = FALSE;
2887 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2888 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2891 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2893 /* Bank is enabled */
2895 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2897 /*------------------------------------------------------------------
2898 * Run the short memory test.
2899 *-----------------------------------------------------------------*/
2900 for (i = 0; i < NUMMEMTESTS; i++) {
2901 for (j = 0; j < NUMMEMWORDS; j++) {
2902 membase[j] = test[i][j];
2903 ppcDcbf((u32)&(membase[j]));
2906 for (j = 0; j < NUMMEMWORDS; j++) {
2907 if (membase[j] != test[i][j]) {
2908 ppcDcbf((u32)&(membase[j]));
2911 ppcDcbf((u32)&(membase[j]));
2914 if (j < NUMMEMWORDS)
2918 /*------------------------------------------------------------------
2919 * See if the rffd value passed.
2920 *-----------------------------------------------------------------*/
2921 if (i < NUMMEMTESTS) {
2922 if ((end_found[dimm_num] == FALSE) &&
2923 (search_end[dimm_num] == TRUE)) {
2924 end_found[dimm_num] = TRUE;
2926 if ((end_found[0] == TRUE) &&
2927 (end_found[1] == TRUE))
2930 if (begin_found[dimm_num] == FALSE) {
2931 begin_found[dimm_num] = TRUE;
2932 search_end[dimm_num] = TRUE;
2936 begin_found[dimm_num] = TRUE;
2937 end_found[dimm_num] = TRUE;
2941 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2942 window_found = TRUE;
2944 /*------------------------------------------------------------------
2945 * Make sure we found the valid read passing window. Halt if not
2946 *-----------------------------------------------------------------*/
2947 if (window_found == FALSE) {
2948 printf("ERROR: Cannot determine a common read delay for the "
2949 "DIMM(s) installed.\n");
2950 spd_ddr_init_hang ();
2953 /*------------------------------------------------------------------
2954 * Restore the ECC variable to what it originally was
2955 *-----------------------------------------------------------------*/
2956 mtsdram(SDRAM_MCOPT1,
2957 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2960 #endif /* !HARD_CODED_DQS */
2961 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2963 #else /* CONFIG_SPD_EEPROM */
2965 /*-----------------------------------------------------------------------------
2966 * Function: initdram
2967 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2968 * The configuration is performed using static, compile-
2970 * Configures the PPC405EX(r) and PPC460EX/GT
2971 *---------------------------------------------------------------------------*/
2972 phys_size_t initdram(int board_type)
2975 * Only run this SDRAM init code once. For NAND booting
2976 * targets like Kilauea, we call initdram() early from the
2977 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2978 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2979 * which calls initdram() again. This time the controller
2980 * mustn't be reconfigured again since we're already running
2983 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2986 #if defined(CONFIG_440)
2987 mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
2988 mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
2989 mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
2990 mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
2991 mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
2992 mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
2993 mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
2994 mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
2995 mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
2998 /* Set Memory Bank Configuration Registers */
3000 mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
3001 mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
3002 mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
3003 mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
3005 /* Set Memory Clock Timing Register */
3007 mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
3009 /* Set Refresh Time Register */
3011 mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
3013 /* Set SDRAM Timing Registers */
3015 mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
3016 mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
3017 mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
3019 /* Set Mode and Extended Mode Registers */
3021 mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
3022 mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
3024 /* Set Memory Controller Options 1 Register */
3026 mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
3028 /* Set Manual Initialization Control Registers */
3030 mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
3031 mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
3032 mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
3033 mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
3034 mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
3035 mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
3036 mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
3037 mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
3038 mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
3039 mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
3040 mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
3041 mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
3042 mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
3043 mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
3044 mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
3045 mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
3047 /* Set On-Die Termination Registers */
3049 mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
3050 mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
3051 mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
3053 /* Set Write Timing Register */
3055 mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
3058 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3059 * SDRAM0_MCOPT2[IPTR] = 1
3062 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3063 SDRAM_MCOPT2_IPTR_EXECUTE));
3066 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3067 * completion of initialization.
3071 mfsdram(SDRAM_MCSTAT, val);
3072 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3074 /* Set Delay Control Registers */
3076 mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
3078 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3079 mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
3080 mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3081 mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3082 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3085 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3088 mfsdram(SDRAM_MCOPT2, val);
3089 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3091 #if defined(CONFIG_440)
3093 * Program TLB entries with caches enabled, for best performace
3094 * while auto-calibrating and ECC generation
3096 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3099 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3100 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3101 /*------------------------------------------------------------------
3103 +-----------------------------------------------------------------*/
3104 DQS_autocalibration();
3105 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3106 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3108 #if defined(CONFIG_DDR_ECC)
3109 ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
3110 #endif /* defined(CONFIG_DDR_ECC) */
3112 #if defined(CONFIG_440)
3114 * Now after initialization (auto-calibration and ECC generation)
3115 * remove the TLB entries with caches enabled and program again with
3116 * desired cache functionality
3118 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3119 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3122 ppc4xx_ibm_ddr2_register_dump();
3124 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3126 * Clear potential errors resulting from auto-calibration.
3127 * If not done, then we could get an interrupt later on when
3128 * exceptions are enabled.
3130 set_mcsr(get_mcsr());
3131 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3133 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3135 return (CONFIG_SYS_MBYTES_SDRAM << 20);
3137 #endif /* CONFIG_SPD_EEPROM */
3139 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3140 #if defined(CONFIG_440)
3141 u32 mfdcr_any(u32 dcr)
3146 case SDRAM_R0BAS + 0:
3147 val = mfdcr(SDRAM_R0BAS + 0);
3149 case SDRAM_R0BAS + 1:
3150 val = mfdcr(SDRAM_R0BAS + 1);
3152 case SDRAM_R0BAS + 2:
3153 val = mfdcr(SDRAM_R0BAS + 2);
3155 case SDRAM_R0BAS + 3:
3156 val = mfdcr(SDRAM_R0BAS + 3);
3159 printf("DCR %d not defined in case statement!!!\n", dcr);
3160 val = 0; /* just to satisfy the compiler */
3166 void mtdcr_any(u32 dcr, u32 val)
3169 case SDRAM_R0BAS + 0:
3170 mtdcr(SDRAM_R0BAS + 0, val);
3172 case SDRAM_R0BAS + 1:
3173 mtdcr(SDRAM_R0BAS + 1, val);
3175 case SDRAM_R0BAS + 2:
3176 mtdcr(SDRAM_R0BAS + 2, val);
3178 case SDRAM_R0BAS + 3:
3179 mtdcr(SDRAM_R0BAS + 3, val);
3182 printf("DCR %d not defined in case statement!!!\n", dcr);
3185 #endif /* defined(CONFIG_440) */
3187 void blank_string(int size)
3191 for (i = 0; i < size; i++)
3193 for (i = 0; i < size; i++)
3195 for (i = 0; i < size; i++)
3198 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3200 inline void ppc4xx_ibm_ddr2_register_dump(void)
3203 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3205 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3206 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3207 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3208 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3209 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3210 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3211 #endif /* (defined(CONFIG_440SP) || ... */
3212 #if defined(CONFIG_405EX)
3213 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3214 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3215 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3216 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3217 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3218 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3219 #endif /* defined(CONFIG_405EX) */
3220 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3221 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3222 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3223 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3224 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3225 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3226 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3227 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3228 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3229 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3230 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3231 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3232 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3233 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3234 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3235 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3237 * OPART is only used as a trigger register.
3239 * No data is contained in this register, and reading or writing
3240 * to is can cause bad things to happen (hangs). Just skip it and
3243 printf("%20s = N/A\n", "SDRAM_OPART");
3244 #endif /* defined(CONFIG_440SP) || ... */
3245 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3246 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3247 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3248 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3249 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3250 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3251 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3252 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3253 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3254 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3255 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3256 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3257 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3258 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3259 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3260 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3261 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3262 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3263 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3264 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3265 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3266 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3267 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3268 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3269 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3270 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3271 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3272 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3273 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3274 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3275 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3276 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3277 #endif /* defined(CONFIG_440SP) || ... */
3278 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3279 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3280 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3281 #endif /* defined(DEBUG) */
3284 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */