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   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2008
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  52
  53 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  54         do {                                                            \
  55                 u32 data;                                               \
  56                 mfsdram(SDRAM_##mnemonic, data);                        \
  57                 printf("%20s[%02x] = 0x%08X\n",                         \
  58                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  59         } while (0)
  60
  61 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  62         do {                                                            \
  63                 u32 data;                                               \
  64                 data = mfdcr(SDRAM_##mnemonic);                         \
  65                 printf("%20s[%02x] = 0x%08X\n",                         \
  66                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  67         } while (0)
  68
  69 #if defined(CONFIG_440)
  70 /*
  71  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  72  * memory region. Right now the cache should still be disabled in U-Boot
  73  * because of the EMAC driver, that need its buffer descriptor to be located
  74  * in non cached memory.
  75  *
  76  * If at some time this restriction doesn't apply anymore, just define
  77  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  78  * everything correctly.
  79  */
  80 #ifdef CONFIG_4xx_DCACHE
  81 /* enable caching on SDRAM */
  82 #define MY_TLB_WORD2_I_ENABLE           0
  83 #else
  84 /* disable caching on SDRAM */
  85 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
  86 #endif /* CONFIG_4xx_DCACHE */
  87
  88 void dcbz_area(u32 start_address, u32 num_bytes);
  89 #endif /* CONFIG_440 */
  90
  91 #define MAXRANKS        4
  92 #define MAXBXCF         4
  93
  94 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  95
  96 static unsigned long is_ecc_enabled(void);
  97
  98 /*-----------------------------------------------------------------------------+
  99  * wait_ddr_idle
 100  *-----------------------------------------------------------------------------*/
 101 static void wait_ddr_idle(void)
 102 {
 103         u32 val;
 104
 105         do {
 106                 mfsdram(SDRAM_MCSTAT, val);
 107         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
 108 }
 109
 110 /*-----------------------------------------------------------------------------+
 111  * sdram_memsize
 112  *-----------------------------------------------------------------------------*/
 113 static phys_size_t sdram_memsize(void)
 114 {
 115         phys_size_t mem_size;
 116         unsigned long mcopt2;
 117         unsigned long mcstat;
 118         unsigned long mb0cf;
 119         unsigned long sdsz;
 120         unsigned long i;
 121
 122         mem_size = 0;
 123
 124         mfsdram(SDRAM_MCOPT2, mcopt2);
 125         mfsdram(SDRAM_MCSTAT, mcstat);
 126
 127         /* DDR controller must be enabled and not in self-refresh. */
 128         /* Otherwise memsize is zero. */
 129         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 130             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 131             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 132                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 133                 for (i = 0; i < MAXBXCF; i++) {
 134                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 135                         /* Banks enabled */
 136                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 137 #if defined(CONFIG_440)
 138                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 139 #else
 140                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
 141 #endif
 142                                 switch(sdsz) {
 143                                 case SDRAM_RXBAS_SDSZ_8:
 144                                         mem_size+=8;
 145                                         break;
 146                                 case SDRAM_RXBAS_SDSZ_16:
 147                                         mem_size+=16;
 148                                         break;
 149                                 case SDRAM_RXBAS_SDSZ_32:
 150                                         mem_size+=32;
 151                                         break;
 152                                 case SDRAM_RXBAS_SDSZ_64:
 153                                         mem_size+=64;
 154                                         break;
 155                                 case SDRAM_RXBAS_SDSZ_128:
 156                                         mem_size+=128;
 157                                         break;
 158                                 case SDRAM_RXBAS_SDSZ_256:
 159                                         mem_size+=256;
 160                                         break;
 161                                 case SDRAM_RXBAS_SDSZ_512:
 162                                         mem_size+=512;
 163                                         break;
 164                                 case SDRAM_RXBAS_SDSZ_1024:
 165                                         mem_size+=1024;
 166                                         break;
 167                                 case SDRAM_RXBAS_SDSZ_2048:
 168                                         mem_size+=2048;
 169                                         break;
 170                                 case SDRAM_RXBAS_SDSZ_4096:
 171                                         mem_size+=4096;
 172                                         break;
 173                                 default:
 174                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 175                                                , sdsz);
 176                                         mem_size=0;
 177                                         break;
 178                                 }
 179                         }
 180                 }
 181         }
 182
 183         return mem_size << 20;
 184 }
 185
 186 /*-----------------------------------------------------------------------------+
 187  * board_add_ram_info
 188  *-----------------------------------------------------------------------------*/
 189 void board_add_ram_info(int use_default)
 190 {
 191         PPC4xx_SYS_INFO board_cfg;
 192         u32 val;
 193
 194         if (is_ecc_enabled())
 195                 puts(" (ECC");
 196         else
 197                 puts(" (ECC not");
 198
 199         get_sys_info(&board_cfg);
 200
 201 #if defined(CONFIG_440)
 202         mfsdr(SDR0_DDR0, val);
 203         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 204 #else
 205         mfsdr(SDR0_SDSTP0, val);
 206         val = MULDIV64((board_cfg.freqPLB), SDR0_SDSTP0_PLB2xDV0_DECODE(val), 1);
 207 #endif
 208         printf(" enabled, %d MHz", (val * 2) / 1000000);
 209
 210         mfsdram(SDRAM_MMODE, val);
 211         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 212         printf(", CL%d)", val);
 213 }
 214
 215 #ifdef CONFIG_DDR_ECC
 216 /*-----------------------------------------------------------------------------+
 217  * program_ecc_addr.
 218  *-----------------------------------------------------------------------------*/
 219 static void program_ecc_addr(unsigned long start_address,
 220                              unsigned long num_bytes,
 221                              unsigned long tlb_word2_i_value)
 222 {
 223         unsigned long current_address;
 224         unsigned long end_address;
 225         unsigned long address_increment;
 226         unsigned long mcopt1;
 227         char str[] = "ECC generation -";
 228         char slash[] = "\\|/-\\|/-";
 229         int loop = 0;
 230         int loopi = 0;
 231
 232         current_address = start_address;
 233         mfsdram(SDRAM_MCOPT1, mcopt1);
 234         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
 235                 mtsdram(SDRAM_MCOPT1,
 236                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
 237                 sync();
 238                 eieio();
 239                 wait_ddr_idle();
 240
 241                 puts(str);
 242
 243 #ifdef CONFIG_440
 244                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
 245 #endif
 246                         /* ECC bit set method for non-cached memory */
 247                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
 248                                 address_increment = 4;
 249                         else
 250                                 address_increment = 8;
 251                         end_address = current_address + num_bytes;
 252
 253                         while (current_address < end_address) {
 254                                 *((unsigned long *)current_address) = 0x00000000;
 255                                 current_address += address_increment;
 256
 257                                 if ((loop++ % (2 << 20)) == 0) {
 258                                         putc('\b');
 259                                         putc(slash[loopi++ % 8]);
 260                                 }
 261                         }
 262 #ifdef CONFIG_440
 263                 } else {
 264                         /* ECC bit set method for cached memory */
 265                         dcbz_area(start_address, num_bytes);
 266                         /* Write modified dcache lines back to memory */
 267                         clean_dcache_range(start_address, start_address + num_bytes);
 268                 }
 269 #endif /* CONFIG_440 */
 270
 271                 blank_string(strlen(str));
 272
 273                 sync();
 274                 eieio();
 275                 wait_ddr_idle();
 276
 277                 /* clear ECC error repoting registers */
 278                 mtsdram(SDRAM_ECCCR, 0xffffffff);
 279                 mtdcr(0x4c, 0xffffffff);
 280
 281                 mtsdram(SDRAM_MCOPT1,
 282                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
 283                 sync();
 284                 eieio();
 285                 wait_ddr_idle();
 286         }
 287 }
 288
 289 /*-----------------------------------------------------------------------------+
 290  * do_program_ecc.
 291  *-----------------------------------------------------------------------------*/
 292 static void do_program_ecc(unsigned long tlb_word2_i_value)
 293 {
 294         unsigned long mcopt1;
 295         unsigned long mcopt2;
 296         unsigned long mcstat;
 297         phys_size_t memsize = sdram_memsize();
 298
 299         if (memsize > CONFIG_MAX_MEM_MAPPED) {
 300                 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
 301                 return;
 302         }
 303
 304         mfsdram(SDRAM_MCOPT1, mcopt1);
 305         mfsdram(SDRAM_MCOPT2, mcopt2);
 306
 307         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
 308                 /* DDR controller must be enabled and not in self-refresh. */
 309                 mfsdram(SDRAM_MCSTAT, mcstat);
 310                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 311                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 312                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 313                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 314
 315                         program_ecc_addr(0, memsize, tlb_word2_i_value);
 316                 }
 317         }
 318 }
 319 #endif /* CONFIG_DDR_ECC */
 320
 321 #if defined(CONFIG_SPD_EEPROM)
 322
 323 /*-----------------------------------------------------------------------------+
 324  * Defines
 325  *-----------------------------------------------------------------------------*/
 326 #ifndef TRUE
 327 #define TRUE            1
 328 #endif
 329 #ifndef FALSE
 330 #define FALSE           0
 331 #endif
 332
 333 #define SDRAM_DDR1      1
 334 #define SDRAM_DDR2      2
 335 #define SDRAM_NONE      0
 336
 337 #define MAXDIMMS        2
 338 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 339
 340 #define ONE_BILLION     1000000000
 341
 342 #define CMD_NOP         (7 << 19)
 343 #define CMD_PRECHARGE   (2 << 19)
 344 #define CMD_REFRESH     (1 << 19)
 345 #define CMD_EMR         (0 << 19)
 346 #define CMD_READ        (5 << 19)
 347 #define CMD_WRITE       (4 << 19)
 348
 349 #define SELECT_MR       (0 << 16)
 350 #define SELECT_EMR      (1 << 16)
 351 #define SELECT_EMR2     (2 << 16)
 352 #define SELECT_EMR3     (3 << 16)
 353
 354 /* MR */
 355 #define DLL_RESET       0x00000100
 356
 357 #define WRITE_RECOV_2   (1 << 9)
 358 #define WRITE_RECOV_3   (2 << 9)
 359 #define WRITE_RECOV_4   (3 << 9)
 360 #define WRITE_RECOV_5   (4 << 9)
 361 #define WRITE_RECOV_6   (5 << 9)
 362
 363 #define BURST_LEN_4     0x00000002
 364
 365 /* EMR */
 366 #define ODT_0_OHM       0x00000000
 367 #define ODT_50_OHM      0x00000044
 368 #define ODT_75_OHM      0x00000004
 369 #define ODT_150_OHM     0x00000040
 370
 371 #define ODS_FULL        0x00000000
 372 #define ODS_REDUCED     0x00000002
 373 #define OCD_CALIB_DEF   0x00000380
 374
 375 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 376 #define ODT_EB0R        (0x80000000 >> 8)
 377 #define ODT_EB0W        (0x80000000 >> 7)
 378 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 379 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 380 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 381
 382 /* Defines for the Read Cycle Delay test */
 383 #define NUMMEMTESTS     8
 384 #define NUMMEMWORDS     8
 385 #define NUMLOOPS        64              /* memory test loops */
 386
 387 /*
 388  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 389  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 390  * need some free virtual address space for the remaining peripherals like, SoC
 391  * devices, FLASH etc.
 392  *
 393  * Note that ECC is currently not supported on configurations with more than 2GB
 394  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 395  * the ECC parity byte of the remaining area can't be written.
 396  */
 397
 398 /*
 399  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 400  */
 401 void __spd_ddr_init_hang (void)
 402 {
 403         hang ();
 404 }
 405 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 406
 407 /*
 408  * To provide an interface for board specific config values in this common
 409  * DDR setup code, we implement he "weak" default functions here. They return
 410  * the default value back to the caller.
 411  *
 412  * Please see include/configs/yucca.h for an example fora board specific
 413  * implementation.
 414  */
 415 u32 __ddr_wrdtr(u32 default_val)
 416 {
 417         return default_val;
 418 }
 419 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 420
 421 u32 __ddr_clktr(u32 default_val)
 422 {
 423         return default_val;
 424 }
 425 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 426
 427
 428 /* Private Structure Definitions */
 429
 430 /* enum only to ease code for cas latency setting */
 431 typedef enum ddr_cas_id {
 432         DDR_CAS_2      = 20,
 433         DDR_CAS_2_5    = 25,
 434         DDR_CAS_3      = 30,
 435         DDR_CAS_4      = 40,
 436         DDR_CAS_5      = 50
 437 } ddr_cas_id_t;
 438
 439 /*-----------------------------------------------------------------------------+
 440  * Prototypes
 441  *-----------------------------------------------------------------------------*/
 442 static phys_size_t sdram_memsize(void);
 443 static void get_spd_info(unsigned long *dimm_populated,
 444                          unsigned char *iic0_dimm_addr,
 445                          unsigned long num_dimm_banks);
 446 static void check_mem_type(unsigned long *dimm_populated,
 447                            unsigned char *iic0_dimm_addr,
 448                            unsigned long num_dimm_banks);
 449 static void check_frequency(unsigned long *dimm_populated,
 450                             unsigned char *iic0_dimm_addr,
 451                             unsigned long num_dimm_banks);
 452 static void check_rank_number(unsigned long *dimm_populated,
 453                               unsigned char *iic0_dimm_addr,
 454                               unsigned long num_dimm_banks);
 455 static void check_voltage_type(unsigned long *dimm_populated,
 456                                unsigned char *iic0_dimm_addr,
 457                                unsigned long num_dimm_banks);
 458 static void program_memory_queue(unsigned long *dimm_populated,
 459                                  unsigned char *iic0_dimm_addr,
 460                                  unsigned long num_dimm_banks);
 461 static void program_codt(unsigned long *dimm_populated,
 462                          unsigned char *iic0_dimm_addr,
 463                          unsigned long num_dimm_banks);
 464 static void program_mode(unsigned long *dimm_populated,
 465                          unsigned char *iic0_dimm_addr,
 466                          unsigned long num_dimm_banks,
 467                          ddr_cas_id_t *selected_cas,
 468                          int *write_recovery);
 469 static void program_tr(unsigned long *dimm_populated,
 470                        unsigned char *iic0_dimm_addr,
 471                        unsigned long num_dimm_banks);
 472 static void program_rtr(unsigned long *dimm_populated,
 473                         unsigned char *iic0_dimm_addr,
 474                         unsigned long num_dimm_banks);
 475 static void program_bxcf(unsigned long *dimm_populated,
 476                          unsigned char *iic0_dimm_addr,
 477                          unsigned long num_dimm_banks);
 478 static void program_copt1(unsigned long *dimm_populated,
 479                           unsigned char *iic0_dimm_addr,
 480                           unsigned long num_dimm_banks);
 481 static void program_initplr(unsigned long *dimm_populated,
 482                             unsigned char *iic0_dimm_addr,
 483                             unsigned long num_dimm_banks,
 484                             ddr_cas_id_t selected_cas,
 485                             int write_recovery);
 486 #ifdef CONFIG_DDR_ECC
 487 static void program_ecc(unsigned long *dimm_populated,
 488                         unsigned char *iic0_dimm_addr,
 489                         unsigned long num_dimm_banks,
 490                         unsigned long tlb_word2_i_value);
 491 #endif
 492 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 493 static void program_DQS_calibration(unsigned long *dimm_populated,
 494                                 unsigned char *iic0_dimm_addr,
 495                                 unsigned long num_dimm_banks);
 496 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 497 static void     test(void);
 498 #else
 499 static void     DQS_calibration_process(void);
 500 #endif
 501 #endif
 502 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 503
 504 static unsigned char spd_read(uchar chip, uint addr)
 505 {
 506         unsigned char data[2];
 507
 508         if (i2c_probe(chip) == 0)
 509                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 510                         return data[0];
 511
 512         return 0;
 513 }
 514
 515 /*-----------------------------------------------------------------------------+
 516  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 517  * Note: This routine runs from flash with a stack set up in the chip's
 518  * sram space.  It is important that the routine does not require .sbss, .bss or
 519  * .data sections.  It also cannot call routines that require these sections.
 520  *-----------------------------------------------------------------------------*/
 521 /*-----------------------------------------------------------------------------
 522  * Function:     initdram
 523  * Description:  Configures SDRAM memory banks for DDR operation.
 524  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 525  *               via the IIC bus and then configures the DDR SDRAM memory
 526  *               banks appropriately. If Auto Memory Configuration is
 527  *               not used, it is assumed that no DIMM is plugged
 528  *-----------------------------------------------------------------------------*/
 529 phys_size_t initdram(int board_type)
 530 {
 531         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 532         unsigned char spd0[MAX_SPD_BYTES];
 533         unsigned char spd1[MAX_SPD_BYTES];
 534         unsigned char *dimm_spd[MAXDIMMS];
 535         unsigned long dimm_populated[MAXDIMMS];
 536         unsigned long num_dimm_banks;           /* on board dimm banks */
 537         unsigned long val;
 538         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 539         int write_recovery;
 540         phys_size_t dram_size = 0;
 541
 542         num_dimm_banks = sizeof(iic0_dimm_addr);
 543
 544         /*------------------------------------------------------------------
 545          * Set up an array of SPD matrixes.
 546          *-----------------------------------------------------------------*/
 547         dimm_spd[0] = spd0;
 548         dimm_spd[1] = spd1;
 549
 550         /*------------------------------------------------------------------
 551          * Reset the DDR-SDRAM controller.
 552          *-----------------------------------------------------------------*/
 553         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 554         mtsdr(SDR0_SRST, 0x00000000);
 555
 556         /*
 557          * Make sure I2C controller is initialized
 558          * before continuing.
 559          */
 560
 561         /* switch to correct I2C bus */
 562         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 563         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 564
 565         /*------------------------------------------------------------------
 566          * Clear out the serial presence detect buffers.
 567          * Perform IIC reads from the dimm.  Fill in the spds.
 568          * Check to see if the dimm slots are populated
 569          *-----------------------------------------------------------------*/
 570         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 571
 572         /*------------------------------------------------------------------
 573          * Check the memory type for the dimms plugged.
 574          *-----------------------------------------------------------------*/
 575         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 576
 577         /*------------------------------------------------------------------
 578          * Check the frequency supported for the dimms plugged.
 579          *-----------------------------------------------------------------*/
 580         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 581
 582         /*------------------------------------------------------------------
 583          * Check the total rank number.
 584          *-----------------------------------------------------------------*/
 585         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 586
 587         /*------------------------------------------------------------------
 588          * Check the voltage type for the dimms plugged.
 589          *-----------------------------------------------------------------*/
 590         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 591
 592         /*------------------------------------------------------------------
 593          * Program SDRAM controller options 2 register
 594          * Except Enabling of the memory controller.
 595          *-----------------------------------------------------------------*/
 596         mfsdram(SDRAM_MCOPT2, val);
 597         mtsdram(SDRAM_MCOPT2,
 598                 (val &
 599                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 600                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 601                    SDRAM_MCOPT2_ISIE_MASK))
 602                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 603                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 604                    SDRAM_MCOPT2_ISIE_ENABLE));
 605
 606         /*------------------------------------------------------------------
 607          * Program SDRAM controller options 1 register
 608          * Note: Does not enable the memory controller.
 609          *-----------------------------------------------------------------*/
 610         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 611
 612         /*------------------------------------------------------------------
 613          * Set the SDRAM Controller On Die Termination Register
 614          *-----------------------------------------------------------------*/
 615         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 616
 617         /*------------------------------------------------------------------
 618          * Program SDRAM refresh register.
 619          *-----------------------------------------------------------------*/
 620         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 621
 622         /*------------------------------------------------------------------
 623          * Program SDRAM mode register.
 624          *-----------------------------------------------------------------*/
 625         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 626                      &selected_cas, &write_recovery);
 627
 628         /*------------------------------------------------------------------
 629          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 630          *-----------------------------------------------------------------*/
 631         mfsdram(SDRAM_WRDTR, val);
 632         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 633                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 634
 635         /*------------------------------------------------------------------
 636          * Set the SDRAM Clock Timing Register
 637          *-----------------------------------------------------------------*/
 638         mfsdram(SDRAM_CLKTR, val);
 639         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 640                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 641
 642         /*------------------------------------------------------------------
 643          * Program the BxCF registers.
 644          *-----------------------------------------------------------------*/
 645         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 646
 647         /*------------------------------------------------------------------
 648          * Program SDRAM timing registers.
 649          *-----------------------------------------------------------------*/
 650         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 651
 652         /*------------------------------------------------------------------
 653          * Set the Extended Mode register
 654          *-----------------------------------------------------------------*/
 655         mfsdram(SDRAM_MEMODE, val);
 656         mtsdram(SDRAM_MEMODE,
 657                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 658                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 659                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 660                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 661
 662         /*------------------------------------------------------------------
 663          * Program Initialization preload registers.
 664          *-----------------------------------------------------------------*/
 665         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 666                         selected_cas, write_recovery);
 667
 668         /*------------------------------------------------------------------
 669          * Delay to ensure 200usec have elapsed since reset.
 670          *-----------------------------------------------------------------*/
 671         udelay(400);
 672
 673         /*------------------------------------------------------------------
 674          * Set the memory queue core base addr.
 675          *-----------------------------------------------------------------*/
 676         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 677
 678         /*------------------------------------------------------------------
 679          * Program SDRAM controller options 2 register
 680          * Enable the memory controller.
 681          *-----------------------------------------------------------------*/
 682         mfsdram(SDRAM_MCOPT2, val);
 683         mtsdram(SDRAM_MCOPT2,
 684                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 685                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 686                          SDRAM_MCOPT2_IPTR_EXECUTE);
 687
 688         /*------------------------------------------------------------------
 689          * Wait for IPTR_EXECUTE init sequence to complete.
 690          *-----------------------------------------------------------------*/
 691         do {
 692                 mfsdram(SDRAM_MCSTAT, val);
 693         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 694
 695         /* enable the controller only after init sequence completes */
 696         mfsdram(SDRAM_MCOPT2, val);
 697         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 698
 699         /* Make sure delay-line calibration is done before proceeding */
 700         do {
 701                 mfsdram(SDRAM_DLCR, val);
 702         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 703
 704         /* get installed memory size */
 705         dram_size = sdram_memsize();
 706
 707         /*
 708          * Limit size to 2GB
 709          */
 710         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 711                 dram_size = CONFIG_MAX_MEM_MAPPED;
 712
 713         /* and program tlb entries for this size (dynamic) */
 714
 715         /*
 716          * Program TLB entries with caches enabled, for best performace
 717          * while auto-calibrating and ECC generation
 718          */
 719         program_tlb(0, 0, dram_size, 0);
 720
 721         /*------------------------------------------------------------------
 722          * DQS calibration.
 723          *-----------------------------------------------------------------*/
 724 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 725         DQS_autocalibration();
 726 #else
 727         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 728 #endif
 729
 730 #ifdef CONFIG_DDR_ECC
 731         /*------------------------------------------------------------------
 732          * If ecc is enabled, initialize the parity bits.
 733          *-----------------------------------------------------------------*/
 734         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 735 #endif
 736
 737         /*
 738          * Now after initialization (auto-calibration and ECC generation)
 739          * remove the TLB entries with caches enabled and program again with
 740          * desired cache functionality
 741          */
 742         remove_tlb(0, dram_size);
 743         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 744
 745         ppc4xx_ibm_ddr2_register_dump();
 746
 747         /*
 748          * Clear potential errors resulting from auto-calibration.
 749          * If not done, then we could get an interrupt later on when
 750          * exceptions are enabled.
 751          */
 752         set_mcsr(get_mcsr());
 753
 754         return sdram_memsize();
 755 }
 756
 757 static void get_spd_info(unsigned long *dimm_populated,
 758                          unsigned char *iic0_dimm_addr,
 759                          unsigned long num_dimm_banks)
 760 {
 761         unsigned long dimm_num;
 762         unsigned long dimm_found;
 763         unsigned char num_of_bytes;
 764         unsigned char total_size;
 765
 766         dimm_found = FALSE;
 767         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 768                 num_of_bytes = 0;
 769                 total_size = 0;
 770
 771                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 772                 debug("\nspd_read(0x%x) returned %d\n",
 773                       iic0_dimm_addr[dimm_num], num_of_bytes);
 774                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 775                 debug("spd_read(0x%x) returned %d\n",
 776                       iic0_dimm_addr[dimm_num], total_size);
 777
 778                 if ((num_of_bytes != 0) && (total_size != 0)) {
 779                         dimm_populated[dimm_num] = TRUE;
 780                         dimm_found = TRUE;
 781                         debug("DIMM slot %lu: populated\n", dimm_num);
 782                 } else {
 783                         dimm_populated[dimm_num] = FALSE;
 784                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 785                 }
 786         }
 787
 788         if (dimm_found == FALSE) {
 789                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 790                 spd_ddr_init_hang ();
 791         }
 792 }
 793
 794
 795 /*------------------------------------------------------------------
 796  * For the memory DIMMs installed, this routine verifies that they
 797  * really are DDR specific DIMMs.
 798  *-----------------------------------------------------------------*/
 799 static void check_mem_type(unsigned long *dimm_populated,
 800                            unsigned char *iic0_dimm_addr,
 801                            unsigned long num_dimm_banks)
 802 {
 803         unsigned long dimm_num;
 804         unsigned long dimm_type;
 805
 806         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 807                 if (dimm_populated[dimm_num] == TRUE) {
 808                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 809                         switch (dimm_type) {
 810                         case 1:
 811                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 812                                        "slot %d.\n", (unsigned int)dimm_num);
 813                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 814                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 815                                 spd_ddr_init_hang ();
 816                                 break;
 817                         case 2:
 818                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 819                                        (unsigned int)dimm_num);
 820                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 821                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 822                                 spd_ddr_init_hang ();
 823                                 break;
 824                         case 3:
 825                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 826                                        (unsigned int)dimm_num);
 827                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 828                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 829                                 spd_ddr_init_hang ();
 830                                 break;
 831                         case 4:
 832                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 833                                        (unsigned int)dimm_num);
 834                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 835                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 836                                 spd_ddr_init_hang ();
 837                                 break;
 838                         case 5:
 839                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 840                                        (unsigned int)dimm_num);
 841                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 842                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 843                                 spd_ddr_init_hang ();
 844                                 break;
 845                         case 6:
 846                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 847                                        (unsigned int)dimm_num);
 848                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 849                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 850                                 spd_ddr_init_hang ();
 851                                 break;
 852                         case 7:
 853                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 854                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 855                                 break;
 856                         case 8:
 857                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 858                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 859                                 break;
 860                         default:
 861                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 862                                        (unsigned int)dimm_num);
 863                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 864                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 865                                 spd_ddr_init_hang ();
 866                                 break;
 867                         }
 868                 }
 869         }
 870         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 871                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 872                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 873                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 874                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 875                         spd_ddr_init_hang ();
 876                 }
 877         }
 878 }
 879
 880 /*------------------------------------------------------------------
 881  * For the memory DIMMs installed, this routine verifies that
 882  * frequency previously calculated is supported.
 883  *-----------------------------------------------------------------*/
 884 static void check_frequency(unsigned long *dimm_populated,
 885                             unsigned char *iic0_dimm_addr,
 886                             unsigned long num_dimm_banks)
 887 {
 888         unsigned long dimm_num;
 889         unsigned long tcyc_reg;
 890         unsigned long cycle_time;
 891         unsigned long calc_cycle_time;
 892         unsigned long sdram_freq;
 893         unsigned long sdr_ddrpll;
 894         PPC4xx_SYS_INFO board_cfg;
 895
 896         /*------------------------------------------------------------------
 897          * Get the board configuration info.
 898          *-----------------------------------------------------------------*/
 899         get_sys_info(&board_cfg);
 900
 901         mfsdr(SDR0_DDR0, sdr_ddrpll);
 902         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 903
 904         /*
 905          * calc_cycle_time is calculated from DDR frequency set by board/chip
 906          * and is expressed in multiple of 10 picoseconds
 907          * to match the way DIMM cycle time is calculated below.
 908          */
 909         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 910
 911         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 912                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 913                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 914                         /*
 915                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 916                          * the higher order nibble (bits 4-7) designates the cycle time
 917                          * to a granularity of 1ns;
 918                          * the value presented by the lower order nibble (bits 0-3)
 919                          * has a granularity of .1ns and is added to the value designated
 920                          * by the higher nibble. In addition, four lines of the lower order
 921                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 922                          */
 923                          /* Convert from hex to decimal */
 924                         if ((tcyc_reg & 0x0F) == 0x0D)
 925                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 926                         else if ((tcyc_reg & 0x0F) == 0x0C)
 927                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 928                         else if ((tcyc_reg & 0x0F) == 0x0B)
 929                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 930                         else if ((tcyc_reg & 0x0F) == 0x0A)
 931                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 932                         else
 933                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 934                                         ((tcyc_reg & 0x0F)*10);
 935                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 936
 937                         if  (cycle_time > (calc_cycle_time + 10)) {
 938                                 /*
 939                                  * the provided sdram cycle_time is too small
 940                                  * for the available DIMM cycle_time.
 941                                  * The additionnal 100ps is here to accept a small incertainty.
 942                                  */
 943                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 944                                        "slot %d \n while calculated cycle time is %d ps.\n",
 945                                        (unsigned int)(cycle_time*10),
 946                                        (unsigned int)dimm_num,
 947                                        (unsigned int)(calc_cycle_time*10));
 948                                 printf("Replace the DIMM, or change DDR frequency via "
 949                                        "strapping bits.\n\n");
 950                                 spd_ddr_init_hang ();
 951                         }
 952                 }
 953         }
 954 }
 955
 956 /*------------------------------------------------------------------
 957  * For the memory DIMMs installed, this routine verifies two
 958  * ranks/banks maximum are availables.
 959  *-----------------------------------------------------------------*/
 960 static void check_rank_number(unsigned long *dimm_populated,
 961                               unsigned char *iic0_dimm_addr,
 962                               unsigned long num_dimm_banks)
 963 {
 964         unsigned long dimm_num;
 965         unsigned long dimm_rank;
 966         unsigned long total_rank = 0;
 967
 968         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 969                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 970                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 971                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 972                                 dimm_rank = (dimm_rank & 0x0F) +1;
 973                         else
 974                                 dimm_rank = dimm_rank & 0x0F;
 975
 976
 977                         if (dimm_rank > MAXRANKS) {
 978                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 979                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 980                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 981                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 982                                 spd_ddr_init_hang ();
 983                         } else
 984                                 total_rank += dimm_rank;
 985                 }
 986                 if (total_rank > MAXRANKS) {
 987                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 988                                "for all slots.\n", (unsigned int)total_rank);
 989                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 990                         printf("Remove one of the DIMM modules.\n\n");
 991                         spd_ddr_init_hang ();
 992                 }
 993         }
 994 }
 995
 996 /*------------------------------------------------------------------
 997  * only support 2.5V modules.
 998  * This routine verifies this.
 999  *-----------------------------------------------------------------*/
1000 static void check_voltage_type(unsigned long *dimm_populated,
1001                                unsigned char *iic0_dimm_addr,
1002                                unsigned long num_dimm_banks)
1003 {
1004         unsigned long dimm_num;
1005         unsigned long voltage_type;
1006
1007         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1008                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1009                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
1010                         switch (voltage_type) {
1011                         case 0x00:
1012                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
1013                                 printf("This DIMM is 5.0 Volt/TTL.\n");
1014                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
1015                                        (unsigned int)dimm_num);
1016                                 spd_ddr_init_hang ();
1017                                 break;
1018                         case 0x01:
1019                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
1020                                 printf("This DIMM is LVTTL.\n");
1021                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
1022                                        (unsigned int)dimm_num);
1023                                 spd_ddr_init_hang ();
1024                                 break;
1025                         case 0x02:
1026                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
1027                                 printf("This DIMM is 1.5 Volt.\n");
1028                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
1029                                        (unsigned int)dimm_num);
1030                                 spd_ddr_init_hang ();
1031                                 break;
1032                         case 0x03:
1033                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
1034                                 printf("This DIMM is 3.3 Volt/TTL.\n");
1035                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
1036                                        (unsigned int)dimm_num);
1037                                 spd_ddr_init_hang ();
1038                                 break;
1039                         case 0x04:
1040                                 /* 2.5 Voltage only for DDR1 */
1041                                 break;
1042                         case 0x05:
1043                                 /* 1.8 Voltage only for DDR2 */
1044                                 break;
1045                         default:
1046                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
1047                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
1048                                        (unsigned int)dimm_num);
1049                                 spd_ddr_init_hang ();
1050                                 break;
1051                         }
1052                 }
1053         }
1054 }
1055
1056 /*-----------------------------------------------------------------------------+
1057  * program_copt1.
1058  *-----------------------------------------------------------------------------*/
1059 static void program_copt1(unsigned long *dimm_populated,
1060                           unsigned char *iic0_dimm_addr,
1061                           unsigned long num_dimm_banks)
1062 {
1063         unsigned long dimm_num;
1064         unsigned long mcopt1;
1065         unsigned long ecc_enabled;
1066         unsigned long ecc = 0;
1067         unsigned long data_width = 0;
1068         unsigned long dimm_32bit;
1069         unsigned long dimm_64bit;
1070         unsigned long registered = 0;
1071         unsigned long attribute = 0;
1072         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1073         unsigned long bankcount;
1074         unsigned long ddrtype;
1075         unsigned long val;
1076
1077 #ifdef CONFIG_DDR_ECC
1078         ecc_enabled = TRUE;
1079 #else
1080         ecc_enabled = FALSE;
1081 #endif
1082         dimm_32bit = FALSE;
1083         dimm_64bit = FALSE;
1084         buf0 = FALSE;
1085         buf1 = FALSE;
1086
1087         /*------------------------------------------------------------------
1088          * Set memory controller options reg 1, SDRAM_MCOPT1.
1089          *-----------------------------------------------------------------*/
1090         mfsdram(SDRAM_MCOPT1, val);
1091         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1092                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
1093                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1094                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1095                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1096                          SDRAM_MCOPT1_DREF_MASK);
1097
1098         mcopt1 |= SDRAM_MCOPT1_QDEP;
1099         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1100         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1101         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1102         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1103         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1104
1105         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1106                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1107                         /* test ecc support */
1108                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1109                         if (ecc != 0x02) /* ecc not supported */
1110                                 ecc_enabled = FALSE;
1111
1112                         /* test bank count */
1113                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1114                         if (bankcount == 0x04) /* bank count = 4 */
1115                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1116                         else /* bank count = 8 */
1117                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1118
1119                         /* test DDR type */
1120                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1121                         /* test for buffered/unbuffered, registered, differential clocks */
1122                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1123                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1124
1125                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1126                         if (dimm_num == 0) {
1127                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1128                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1129                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1130                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1131                                 if (registered == 1) { /* DDR2 always buffered */
1132                                         /* TODO: what about above  comments ? */
1133                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1134                                         buf0 = TRUE;
1135                                 } else {
1136                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1137                                         if ((attribute & 0x02) == 0x00) {
1138                                                 /* buffered not supported */
1139                                                 buf0 = FALSE;
1140                                         } else {
1141                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1142                                                 buf0 = TRUE;
1143                                         }
1144                                 }
1145                         }
1146                         else if (dimm_num == 1) {
1147                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1148                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1149                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1150                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1151                                 if (registered == 1) {
1152                                         /* DDR2 always buffered */
1153                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1154                                         buf1 = TRUE;
1155                                 } else {
1156                                         if ((attribute & 0x02) == 0x00) {
1157                                                 /* buffered not supported */
1158                                                 buf1 = FALSE;
1159                                         } else {
1160                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1161                                                 buf1 = TRUE;
1162                                         }
1163                                 }
1164                         }
1165
1166                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1167                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1168                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1169
1170                         switch (data_width) {
1171                         case 72:
1172                         case 64:
1173                                 dimm_64bit = TRUE;
1174                                 break;
1175                         case 40:
1176                         case 32:
1177                                 dimm_32bit = TRUE;
1178                                 break;
1179                         default:
1180                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1181                                        data_width);
1182                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1183                                 break;
1184                         }
1185                 }
1186         }
1187
1188         /* verify matching properties */
1189         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1190                 if (buf0 != buf1) {
1191                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1192                         spd_ddr_init_hang ();
1193                 }
1194         }
1195
1196         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1197                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1198                 spd_ddr_init_hang ();
1199         }
1200         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1201                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1202         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1203                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1204         } else {
1205                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1206                 spd_ddr_init_hang ();
1207         }
1208
1209         if (ecc_enabled == TRUE)
1210                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1211         else
1212                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1213
1214         mtsdram(SDRAM_MCOPT1, mcopt1);
1215 }
1216
1217 /*-----------------------------------------------------------------------------+
1218  * program_codt.
1219  *-----------------------------------------------------------------------------*/
1220 static void program_codt(unsigned long *dimm_populated,
1221                          unsigned char *iic0_dimm_addr,
1222                          unsigned long num_dimm_banks)
1223 {
1224         unsigned long codt;
1225         unsigned long modt0 = 0;
1226         unsigned long modt1 = 0;
1227         unsigned long modt2 = 0;
1228         unsigned long modt3 = 0;
1229         unsigned char dimm_num;
1230         unsigned char dimm_rank;
1231         unsigned char total_rank = 0;
1232         unsigned char total_dimm = 0;
1233         unsigned char dimm_type = 0;
1234         unsigned char firstSlot = 0;
1235
1236         /*------------------------------------------------------------------
1237          * Set the SDRAM Controller On Die Termination Register
1238          *-----------------------------------------------------------------*/
1239         mfsdram(SDRAM_CODT, codt);
1240         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1241         codt |= SDRAM_CODT_IO_NMODE;
1242
1243         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1244                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1245                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1246                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1247                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1248                                 dimm_type = SDRAM_DDR2;
1249                         } else {
1250                                 dimm_rank = dimm_rank & 0x0F;
1251                                 dimm_type = SDRAM_DDR1;
1252                         }
1253
1254                         total_rank += dimm_rank;
1255                         total_dimm++;
1256                         if ((dimm_num == 0) && (total_dimm == 1))
1257                                 firstSlot = TRUE;
1258                         else
1259                                 firstSlot = FALSE;
1260                 }
1261         }
1262         if (dimm_type == SDRAM_DDR2) {
1263                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1264                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1265                         if (total_rank == 1) {  /* PUUU */
1266                                 codt |= CALC_ODT_R(0);
1267                                 modt0 = CALC_ODT_W(0);
1268                                 modt1 = 0x00000000;
1269                                 modt2 = 0x00000000;
1270                                 modt3 = 0x00000000;
1271                         }
1272                         if (total_rank == 2) {  /* PPUU */
1273                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1274                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1275                                 modt1 = 0x00000000;
1276                                 modt2 = 0x00000000;
1277                                 modt3 = 0x00000000;
1278                         }
1279                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1280                         if (total_rank == 1) {  /* UUPU */
1281                                 codt |= CALC_ODT_R(2);
1282                                 modt0 = 0x00000000;
1283                                 modt1 = 0x00000000;
1284                                 modt2 = CALC_ODT_W(2);
1285                                 modt3 = 0x00000000;
1286                         }
1287                         if (total_rank == 2) {  /* UUPP */
1288                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1289                                 modt0 = 0x00000000;
1290                                 modt1 = 0x00000000;
1291                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1292                                 modt3 = 0x00000000;
1293                         }
1294                 }
1295                 if (total_dimm == 2) {
1296                         if (total_rank == 2) {  /* PUPU */
1297                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1298                                 modt0 = CALC_ODT_RW(2);
1299                                 modt1 = 0x00000000;
1300                                 modt2 = CALC_ODT_RW(0);
1301                                 modt3 = 0x00000000;
1302                         }
1303                         if (total_rank == 4) {  /* PPPP */
1304                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1305                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1306                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1307                                 modt1 = 0x00000000;
1308                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1309                                 modt3 = 0x00000000;
1310                         }
1311                 }
1312         } else {
1313                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1314                 modt0 = 0x00000000;
1315                 modt1 = 0x00000000;
1316                 modt2 = 0x00000000;
1317                 modt3 = 0x00000000;
1318
1319                 if (total_dimm == 1) {
1320                         if (total_rank == 1)
1321                                 codt |= 0x00800000;
1322                         if (total_rank == 2)
1323                                 codt |= 0x02800000;
1324                 }
1325                 if (total_dimm == 2) {
1326                         if (total_rank == 2)
1327                                 codt |= 0x08800000;
1328                         if (total_rank == 4)
1329                                 codt |= 0x2a800000;
1330                 }
1331         }
1332
1333         debug("nb of dimm %d\n", total_dimm);
1334         debug("nb of rank %d\n", total_rank);
1335         if (total_dimm == 1)
1336                 debug("dimm in slot %d\n", firstSlot);
1337
1338         mtsdram(SDRAM_CODT, codt);
1339         mtsdram(SDRAM_MODT0, modt0);
1340         mtsdram(SDRAM_MODT1, modt1);
1341         mtsdram(SDRAM_MODT2, modt2);
1342         mtsdram(SDRAM_MODT3, modt3);
1343 }
1344
1345 /*-----------------------------------------------------------------------------+
1346  * program_initplr.
1347  *-----------------------------------------------------------------------------*/
1348 static void program_initplr(unsigned long *dimm_populated,
1349                             unsigned char *iic0_dimm_addr,
1350                             unsigned long num_dimm_banks,
1351                             ddr_cas_id_t selected_cas,
1352                             int write_recovery)
1353 {
1354         u32 cas = 0;
1355         u32 odt = 0;
1356         u32 ods = 0;
1357         u32 mr;
1358         u32 wr;
1359         u32 emr;
1360         u32 emr2;
1361         u32 emr3;
1362         int dimm_num;
1363         int total_dimm = 0;
1364
1365         /******************************************************
1366          ** Assumption: if more than one DIMM, all DIMMs are the same
1367          **             as already checked in check_memory_type
1368          ******************************************************/
1369
1370         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1371                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1372                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1373                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1374                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1375                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1376                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1377                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1378                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1379         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1380                 switch (selected_cas) {
1381                 case DDR_CAS_3:
1382                         cas = 3 << 4;
1383                         break;
1384                 case DDR_CAS_4:
1385                         cas = 4 << 4;
1386                         break;
1387                 case DDR_CAS_5:
1388                         cas = 5 << 4;
1389                         break;
1390                 default:
1391                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1392                         spd_ddr_init_hang ();
1393                         break;
1394                 }
1395
1396 #if 0
1397                 /*
1398                  * ToDo - Still a problem with the write recovery:
1399                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1400                  * in the INITPLR reg to the value calculated in program_mode()
1401                  * results in not correctly working DDR2 memory (crash after
1402                  * relocation).
1403                  *
1404                  * So for now, set the write recovery to 3. This seems to work
1405                  * on the Corair module too.
1406                  *
1407                  * 2007-03-01, sr
1408                  */
1409                 switch (write_recovery) {
1410                 case 3:
1411                         wr = WRITE_RECOV_3;
1412                         break;
1413                 case 4:
1414                         wr = WRITE_RECOV_4;
1415                         break;
1416                 case 5:
1417                         wr = WRITE_RECOV_5;
1418                         break;
1419                 case 6:
1420                         wr = WRITE_RECOV_6;
1421                         break;
1422                 default:
1423                         printf("ERROR: write recovery not support (%d)", write_recovery);
1424                         spd_ddr_init_hang ();
1425                         break;
1426                 }
1427 #else
1428                 wr = WRITE_RECOV_3; /* test-only, see description above */
1429 #endif
1430
1431                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1432                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1433                                 total_dimm++;
1434                 if (total_dimm == 1) {
1435                         odt = ODT_150_OHM;
1436                         ods = ODS_FULL;
1437                 } else if (total_dimm == 2) {
1438                         odt = ODT_75_OHM;
1439                         ods = ODS_REDUCED;
1440                 } else {
1441                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1442                         spd_ddr_init_hang ();
1443                 }
1444
1445                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1446                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1447                 emr2 = CMD_EMR | SELECT_EMR2;
1448                 emr3 = CMD_EMR | SELECT_EMR3;
1449                 /* NOP - Wait 106 MemClk cycles */
1450                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1451                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1452                 udelay(1000);
1453                 /* precharge 4 MemClk cycles */
1454                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1455                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1456                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1457                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1458                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1459                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1460                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1461                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1462                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1463                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1464                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1465                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1466                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1467                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1468                 udelay(1000);
1469                 /* precharge 4 MemClk cycles */
1470                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1471                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1472                 /* Refresh 25 MemClk cycles */
1473                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1474                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1475                 /* Refresh 25 MemClk cycles */
1476                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1477                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1478                 /* Refresh 25 MemClk cycles */
1479                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1480                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1481                 /* Refresh 25 MemClk cycles */
1482                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1483                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1484                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1485                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1486                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1487                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1488                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1489                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1490                 /* EMR OCD Exit */
1491                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1492                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1493         } else {
1494                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1495                 spd_ddr_init_hang ();
1496         }
1497 }
1498
1499 /*------------------------------------------------------------------
1500  * This routine programs the SDRAM_MMODE register.
1501  * the selected_cas is an output parameter, that will be passed
1502  * by caller to call the above program_initplr( )
1503  *-----------------------------------------------------------------*/
1504 static void program_mode(unsigned long *dimm_populated,
1505                          unsigned char *iic0_dimm_addr,
1506                          unsigned long num_dimm_banks,
1507                          ddr_cas_id_t *selected_cas,
1508                          int *write_recovery)
1509 {
1510         unsigned long dimm_num;
1511         unsigned long sdram_ddr1;
1512         unsigned long t_wr_ns;
1513         unsigned long t_wr_clk;
1514         unsigned long cas_bit;
1515         unsigned long cas_index;
1516         unsigned long sdram_freq;
1517         unsigned long ddr_check;
1518         unsigned long mmode;
1519         unsigned long tcyc_reg;
1520         unsigned long cycle_2_0_clk;
1521         unsigned long cycle_2_5_clk;
1522         unsigned long cycle_3_0_clk;
1523         unsigned long cycle_4_0_clk;
1524         unsigned long cycle_5_0_clk;
1525         unsigned long max_2_0_tcyc_ns_x_100;
1526         unsigned long max_2_5_tcyc_ns_x_100;
1527         unsigned long max_3_0_tcyc_ns_x_100;
1528         unsigned long max_4_0_tcyc_ns_x_100;
1529         unsigned long max_5_0_tcyc_ns_x_100;
1530         unsigned long cycle_time_ns_x_100[3];
1531         PPC4xx_SYS_INFO board_cfg;
1532         unsigned char cas_2_0_available;
1533         unsigned char cas_2_5_available;
1534         unsigned char cas_3_0_available;
1535         unsigned char cas_4_0_available;
1536         unsigned char cas_5_0_available;
1537         unsigned long sdr_ddrpll;
1538
1539         /*------------------------------------------------------------------
1540          * Get the board configuration info.
1541          *-----------------------------------------------------------------*/
1542         get_sys_info(&board_cfg);
1543
1544         mfsdr(SDR0_DDR0, sdr_ddrpll);
1545         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1546         debug("sdram_freq=%lu\n", sdram_freq);
1547
1548         /*------------------------------------------------------------------
1549          * Handle the timing.  We need to find the worst case timing of all
1550          * the dimm modules installed.
1551          *-----------------------------------------------------------------*/
1552         t_wr_ns = 0;
1553         cas_2_0_available = TRUE;
1554         cas_2_5_available = TRUE;
1555         cas_3_0_available = TRUE;
1556         cas_4_0_available = TRUE;
1557         cas_5_0_available = TRUE;
1558         max_2_0_tcyc_ns_x_100 = 10;
1559         max_2_5_tcyc_ns_x_100 = 10;
1560         max_3_0_tcyc_ns_x_100 = 10;
1561         max_4_0_tcyc_ns_x_100 = 10;
1562         max_5_0_tcyc_ns_x_100 = 10;
1563         sdram_ddr1 = TRUE;
1564
1565         /* loop through all the DIMM slots on the board */
1566         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1567                 /* If a dimm is installed in a particular slot ... */
1568                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1569                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1570                                 sdram_ddr1 = TRUE;
1571                         else
1572                                 sdram_ddr1 = FALSE;
1573
1574                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1575                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1576                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1577
1578                         /* For a particular DIMM, grab the three CAS values it supports */
1579                         for (cas_index = 0; cas_index < 3; cas_index++) {
1580                                 switch (cas_index) {
1581                                 case 0:
1582                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1583                                         break;
1584                                 case 1:
1585                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1586                                         break;
1587                                 default:
1588                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1589                                         break;
1590                                 }
1591
1592                                 if ((tcyc_reg & 0x0F) >= 10) {
1593                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1594                                                 /* Convert from hex to decimal */
1595                                                 cycle_time_ns_x_100[cas_index] =
1596                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1597                                         } else {
1598                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1599                                                        "in slot %d\n", (unsigned int)dimm_num);
1600                                                 spd_ddr_init_hang ();
1601                                         }
1602                                 } else {
1603                                         /* Convert from hex to decimal */
1604                                         cycle_time_ns_x_100[cas_index] =
1605                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1606                                                 ((tcyc_reg & 0x0F)*10);
1607                                 }
1608                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1609                                       cycle_time_ns_x_100[cas_index]);
1610                         }
1611
1612                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1613                         /* supported for a particular DIMM. */
1614                         cas_index = 0;
1615
1616                         if (sdram_ddr1) {
1617                                 /*
1618                                  * DDR devices use the following bitmask for CAS latency:
1619                                  *  Bit   7    6    5    4    3    2    1    0
1620                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1621                                  */
1622                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1623                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1624                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1625                                                                     cycle_time_ns_x_100[cas_index]);
1626                                         cas_index++;
1627                                 } else {
1628                                         if (cas_index != 0)
1629                                                 cas_index++;
1630                                         cas_4_0_available = FALSE;
1631                                 }
1632
1633                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1634                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1635                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1636                                                                     cycle_time_ns_x_100[cas_index]);
1637                                         cas_index++;
1638                                 } else {
1639                                         if (cas_index != 0)
1640                                                 cas_index++;
1641                                         cas_3_0_available = FALSE;
1642                                 }
1643
1644                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1645                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1646                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1647                                                                     cycle_time_ns_x_100[cas_index]);
1648                                         cas_index++;
1649                                 } else {
1650                                         if (cas_index != 0)
1651                                                 cas_index++;
1652                                         cas_2_5_available = FALSE;
1653                                 }
1654
1655                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1656                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1657                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1658                                                                     cycle_time_ns_x_100[cas_index]);
1659                                         cas_index++;
1660                                 } else {
1661                                         if (cas_index != 0)
1662                                                 cas_index++;
1663                                         cas_2_0_available = FALSE;
1664                                 }
1665                         } else {
1666                                 /*
1667                                  * DDR2 devices use the following bitmask for CAS latency:
1668                                  *  Bit   7    6    5    4    3    2    1    0
1669                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1670                                  */
1671                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1672                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1673                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1674                                                                     cycle_time_ns_x_100[cas_index]);
1675                                         cas_index++;
1676                                 } else {
1677                                         if (cas_index != 0)
1678                                                 cas_index++;
1679                                         cas_5_0_available = FALSE;
1680                                 }
1681
1682                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1683                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1684                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1685                                                                     cycle_time_ns_x_100[cas_index]);
1686                                         cas_index++;
1687                                 } else {
1688                                         if (cas_index != 0)
1689                                                 cas_index++;
1690                                         cas_4_0_available = FALSE;
1691                                 }
1692
1693                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1694                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1695                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1696                                                                     cycle_time_ns_x_100[cas_index]);
1697                                         cas_index++;
1698                                 } else {
1699                                         if (cas_index != 0)
1700                                                 cas_index++;
1701                                         cas_3_0_available = FALSE;
1702                                 }
1703                         }
1704                 }
1705         }
1706
1707         /*------------------------------------------------------------------
1708          * Set the SDRAM mode, SDRAM_MMODE
1709          *-----------------------------------------------------------------*/
1710         mfsdram(SDRAM_MMODE, mmode);
1711         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1712
1713         /* add 10 here because of rounding problems */
1714         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1715         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1716         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1717         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1718         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1719         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1720         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1721         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1722
1723         if (sdram_ddr1 == TRUE) { /* DDR1 */
1724                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1725                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1726                         *selected_cas = DDR_CAS_2;
1727                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1728                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1729                         *selected_cas = DDR_CAS_2_5;
1730                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1731                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1732                         *selected_cas = DDR_CAS_3;
1733                 } else {
1734                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1735                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1736                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1737                         spd_ddr_init_hang ();
1738                 }
1739         } else { /* DDR2 */
1740                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1741                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1742                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1743                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1744                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1745                         *selected_cas = DDR_CAS_3;
1746                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1747                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1748                         *selected_cas = DDR_CAS_4;
1749                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1750                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1751                         *selected_cas = DDR_CAS_5;
1752                 } else {
1753                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1754                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1755                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1756                         printf("cas3=%d cas4=%d cas5=%d\n",
1757                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1758                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1759                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1760                         spd_ddr_init_hang ();
1761                 }
1762         }
1763
1764         if (sdram_ddr1 == TRUE)
1765                 mmode |= SDRAM_MMODE_WR_DDR1;
1766         else {
1767
1768                 /* loop through all the DIMM slots on the board */
1769                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1770                         /* If a dimm is installed in a particular slot ... */
1771                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1772                                 t_wr_ns = max(t_wr_ns,
1773                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1774                 }
1775
1776                 /*
1777                  * convert from nanoseconds to ddr clocks
1778                  * round up if necessary
1779                  */
1780                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1781                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1782                 if (sdram_freq != ddr_check)
1783                         t_wr_clk++;
1784
1785                 switch (t_wr_clk) {
1786                 case 0:
1787                 case 1:
1788                 case 2:
1789                 case 3:
1790                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1791                         break;
1792                 case 4:
1793                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1794                         break;
1795                 case 5:
1796                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1797                         break;
1798                 default:
1799                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1800                         break;
1801                 }
1802                 *write_recovery = t_wr_clk;
1803         }
1804
1805         debug("CAS latency = %d\n", *selected_cas);
1806         debug("Write recovery = %d\n", *write_recovery);
1807
1808         mtsdram(SDRAM_MMODE, mmode);
1809 }
1810
1811 /*-----------------------------------------------------------------------------+
1812  * program_rtr.
1813  *-----------------------------------------------------------------------------*/
1814 static void program_rtr(unsigned long *dimm_populated,
1815                         unsigned char *iic0_dimm_addr,
1816                         unsigned long num_dimm_banks)
1817 {
1818         PPC4xx_SYS_INFO board_cfg;
1819         unsigned long max_refresh_rate;
1820         unsigned long dimm_num;
1821         unsigned long refresh_rate_type;
1822         unsigned long refresh_rate;
1823         unsigned long rint;
1824         unsigned long sdram_freq;
1825         unsigned long sdr_ddrpll;
1826         unsigned long val;
1827
1828         /*------------------------------------------------------------------
1829          * Get the board configuration info.
1830          *-----------------------------------------------------------------*/
1831         get_sys_info(&board_cfg);
1832
1833         /*------------------------------------------------------------------
1834          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1835          *-----------------------------------------------------------------*/
1836         mfsdr(SDR0_DDR0, sdr_ddrpll);
1837         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1838
1839         max_refresh_rate = 0;
1840         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1841                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1842
1843                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1844                         refresh_rate_type &= 0x7F;
1845                         switch (refresh_rate_type) {
1846                         case 0:
1847                                 refresh_rate =  15625;
1848                                 break;
1849                         case 1:
1850                                 refresh_rate =   3906;
1851                                 break;
1852                         case 2:
1853                                 refresh_rate =   7812;
1854                                 break;
1855                         case 3:
1856                                 refresh_rate =  31250;
1857                                 break;
1858                         case 4:
1859                                 refresh_rate =  62500;
1860                                 break;
1861                         case 5:
1862                                 refresh_rate = 125000;
1863                                 break;
1864                         default:
1865                                 refresh_rate = 0;
1866                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1867                                        (unsigned int)dimm_num);
1868                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1869                                 spd_ddr_init_hang ();
1870                                 break;
1871                         }
1872
1873                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1874                 }
1875         }
1876
1877         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1878         mfsdram(SDRAM_RTR, val);
1879         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1880                 (SDRAM_RTR_RINT_ENCODE(rint)));
1881 }
1882
1883 /*------------------------------------------------------------------
1884  * This routine programs the SDRAM_TRx registers.
1885  *-----------------------------------------------------------------*/
1886 static void program_tr(unsigned long *dimm_populated,
1887                        unsigned char *iic0_dimm_addr,
1888                        unsigned long num_dimm_banks)
1889 {
1890         unsigned long dimm_num;
1891         unsigned long sdram_ddr1;
1892         unsigned long t_rp_ns;
1893         unsigned long t_rcd_ns;
1894         unsigned long t_rrd_ns;
1895         unsigned long t_ras_ns;
1896         unsigned long t_rc_ns;
1897         unsigned long t_rfc_ns;
1898         unsigned long t_wpc_ns;
1899         unsigned long t_wtr_ns;
1900         unsigned long t_rpc_ns;
1901         unsigned long t_rp_clk;
1902         unsigned long t_rcd_clk;
1903         unsigned long t_rrd_clk;
1904         unsigned long t_ras_clk;
1905         unsigned long t_rc_clk;
1906         unsigned long t_rfc_clk;
1907         unsigned long t_wpc_clk;
1908         unsigned long t_wtr_clk;
1909         unsigned long t_rpc_clk;
1910         unsigned long sdtr1, sdtr2, sdtr3;
1911         unsigned long ddr_check;
1912         unsigned long sdram_freq;
1913         unsigned long sdr_ddrpll;
1914
1915         PPC4xx_SYS_INFO board_cfg;
1916
1917         /*------------------------------------------------------------------
1918          * Get the board configuration info.
1919          *-----------------------------------------------------------------*/
1920         get_sys_info(&board_cfg);
1921
1922         mfsdr(SDR0_DDR0, sdr_ddrpll);
1923         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1924
1925         /*------------------------------------------------------------------
1926          * Handle the timing.  We need to find the worst case timing of all
1927          * the dimm modules installed.
1928          *-----------------------------------------------------------------*/
1929         t_rp_ns = 0;
1930         t_rrd_ns = 0;
1931         t_rcd_ns = 0;
1932         t_ras_ns = 0;
1933         t_rc_ns = 0;
1934         t_rfc_ns = 0;
1935         t_wpc_ns = 0;
1936         t_wtr_ns = 0;
1937         t_rpc_ns = 0;
1938         sdram_ddr1 = TRUE;
1939
1940         /* loop through all the DIMM slots on the board */
1941         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1942                 /* If a dimm is installed in a particular slot ... */
1943                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1944                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1945                                 sdram_ddr1 = TRUE;
1946                         else
1947                                 sdram_ddr1 = FALSE;
1948
1949                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1950                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1951                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1952                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1953                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1954                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1955                 }
1956         }
1957
1958         /*------------------------------------------------------------------
1959          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1960          *-----------------------------------------------------------------*/
1961         mfsdram(SDRAM_SDTR1, sdtr1);
1962         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1963                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1964
1965         /* default values */
1966         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1967         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1968
1969         /* normal operations */
1970         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1971         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1972
1973         mtsdram(SDRAM_SDTR1, sdtr1);
1974
1975         /*------------------------------------------------------------------
1976          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1977          *-----------------------------------------------------------------*/
1978         mfsdram(SDRAM_SDTR2, sdtr2);
1979         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1980                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1981                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1982                    SDRAM_SDTR2_RRD_MASK);
1983
1984         /*
1985          * convert t_rcd from nanoseconds to ddr clocks
1986          * round up if necessary
1987          */
1988         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1989         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1990         if (sdram_freq != ddr_check)
1991                 t_rcd_clk++;
1992
1993         switch (t_rcd_clk) {
1994         case 0:
1995         case 1:
1996                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1997                 break;
1998         case 2:
1999                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
2000                 break;
2001         case 3:
2002                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
2003                 break;
2004         case 4:
2005                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
2006                 break;
2007         default:
2008                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
2009                 break;
2010         }
2011
2012         if (sdram_ddr1 == TRUE) { /* DDR1 */
2013                 if (sdram_freq < 200000000) {
2014                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
2015                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
2016                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2017                 } else {
2018                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
2019                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
2020                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2021                 }
2022         } else { /* DDR2 */
2023                 /* loop through all the DIMM slots on the board */
2024                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2025                         /* If a dimm is installed in a particular slot ... */
2026                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
2027                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
2028                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
2029                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
2030                         }
2031                 }
2032
2033                 /*
2034                  * convert from nanoseconds to ddr clocks
2035                  * round up if necessary
2036                  */
2037                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
2038                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
2039                 if (sdram_freq != ddr_check)
2040                         t_wpc_clk++;
2041
2042                 switch (t_wpc_clk) {
2043                 case 0:
2044                 case 1:
2045                 case 2:
2046                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
2047                         break;
2048                 case 3:
2049                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
2050                         break;
2051                 case 4:
2052                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
2053                         break;
2054                 case 5:
2055                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
2056                         break;
2057                 default:
2058                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
2059                         break;
2060                 }
2061
2062                 /*
2063                  * convert from nanoseconds to ddr clocks
2064                  * round up if necessary
2065                  */
2066                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
2067                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
2068                 if (sdram_freq != ddr_check)
2069                         t_wtr_clk++;
2070
2071                 switch (t_wtr_clk) {
2072                 case 0:
2073                 case 1:
2074                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
2075                         break;
2076                 case 2:
2077                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
2078                         break;
2079                 case 3:
2080                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
2081                         break;
2082                 default:
2083                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
2084                         break;
2085                 }
2086
2087                 /*
2088                  * convert from nanoseconds to ddr clocks
2089                  * round up if necessary
2090                  */
2091                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2092                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2093                 if (sdram_freq != ddr_check)
2094                         t_rpc_clk++;
2095
2096                 switch (t_rpc_clk) {
2097                 case 0:
2098                 case 1:
2099                 case 2:
2100                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2101                         break;
2102                 case 3:
2103                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2104                         break;
2105                 default:
2106                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2107                         break;
2108                 }
2109         }
2110
2111         /* default value */
2112         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2113
2114         /*
2115          * convert t_rrd from nanoseconds to ddr clocks
2116          * round up if necessary
2117          */
2118         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2119         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2120         if (sdram_freq != ddr_check)
2121                 t_rrd_clk++;
2122
2123         if (t_rrd_clk == 3)
2124                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2125         else
2126                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2127
2128         /*
2129          * convert t_rp from nanoseconds to ddr clocks
2130          * round up if necessary
2131          */
2132         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2133         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2134         if (sdram_freq != ddr_check)
2135                 t_rp_clk++;
2136
2137         switch (t_rp_clk) {
2138         case 0:
2139         case 1:
2140         case 2:
2141         case 3:
2142                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2143                 break;
2144         case 4:
2145                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2146                 break;
2147         case 5:
2148                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2149                 break;
2150         case 6:
2151                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2152                 break;
2153         default:
2154                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2155                 break;
2156         }
2157
2158         mtsdram(SDRAM_SDTR2, sdtr2);
2159
2160         /*------------------------------------------------------------------
2161          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2162          *-----------------------------------------------------------------*/
2163         mfsdram(SDRAM_SDTR3, sdtr3);
2164         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2165                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2166
2167         /*
2168          * convert t_ras from nanoseconds to ddr clocks
2169          * round up if necessary
2170          */
2171         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2172         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2173         if (sdram_freq != ddr_check)
2174                 t_ras_clk++;
2175
2176         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2177
2178         /*
2179          * convert t_rc from nanoseconds to ddr clocks
2180          * round up if necessary
2181          */
2182         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2183         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2184         if (sdram_freq != ddr_check)
2185                 t_rc_clk++;
2186
2187         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2188
2189         /* default xcs value */
2190         sdtr3 |= SDRAM_SDTR3_XCS;
2191
2192         /*
2193          * convert t_rfc from nanoseconds to ddr clocks
2194          * round up if necessary
2195          */
2196         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2197         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2198         if (sdram_freq != ddr_check)
2199                 t_rfc_clk++;
2200
2201         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2202
2203         mtsdram(SDRAM_SDTR3, sdtr3);
2204 }
2205
2206 /*-----------------------------------------------------------------------------+
2207  * program_bxcf.
2208  *-----------------------------------------------------------------------------*/
2209 static void program_bxcf(unsigned long *dimm_populated,
2210                          unsigned char *iic0_dimm_addr,
2211                          unsigned long num_dimm_banks)
2212 {
2213         unsigned long dimm_num;
2214         unsigned long num_col_addr;
2215         unsigned long num_ranks;
2216         unsigned long num_banks;
2217         unsigned long mode;
2218         unsigned long ind_rank;
2219         unsigned long ind;
2220         unsigned long ind_bank;
2221         unsigned long bank_0_populated;
2222
2223         /*------------------------------------------------------------------
2224          * Set the BxCF regs.  First, wipe out the bank config registers.
2225          *-----------------------------------------------------------------*/
2226         mtsdram(SDRAM_MB0CF, 0x00000000);
2227         mtsdram(SDRAM_MB1CF, 0x00000000);
2228         mtsdram(SDRAM_MB2CF, 0x00000000);
2229         mtsdram(SDRAM_MB3CF, 0x00000000);
2230
2231         mode = SDRAM_BXCF_M_BE_ENABLE;
2232
2233         bank_0_populated = 0;
2234
2235         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2236                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2237                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2238                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2239                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2240                                 num_ranks = (num_ranks & 0x0F) +1;
2241                         else
2242                                 num_ranks = num_ranks & 0x0F;
2243
2244                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2245
2246                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2247                                 if (num_banks == 4)
2248                                         ind = 0;
2249                                 else
2250                                         ind = 5 << 8;
2251                                 switch (num_col_addr) {
2252                                 case 0x08:
2253                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2254                                         break;
2255                                 case 0x09:
2256                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2257                                         break;
2258                                 case 0x0A:
2259                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2260                                         break;
2261                                 case 0x0B:
2262                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2263                                         break;
2264                                 case 0x0C:
2265                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2266                                         break;
2267                                 default:
2268                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2269                                                (unsigned int)dimm_num);
2270                                         printf("ERROR: Unsupported value for number of "
2271                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2272                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2273                                         spd_ddr_init_hang ();
2274                                 }
2275                         }
2276
2277                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2278                                 bank_0_populated = 1;
2279
2280                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2281                                 mtsdram(SDRAM_MB0CF +
2282                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2283                                         mode);
2284                         }
2285                 }
2286         }
2287 }
2288
2289 /*------------------------------------------------------------------
2290  * program memory queue.
2291  *-----------------------------------------------------------------*/
2292 static void program_memory_queue(unsigned long *dimm_populated,
2293                                  unsigned char *iic0_dimm_addr,
2294                                  unsigned long num_dimm_banks)
2295 {
2296         unsigned long dimm_num;
2297         phys_size_t rank_base_addr;
2298         unsigned long rank_reg;
2299         phys_size_t rank_size_bytes;
2300         unsigned long rank_size_id;
2301         unsigned long num_ranks;
2302         unsigned long baseadd_size;
2303         unsigned long i;
2304         unsigned long bank_0_populated = 0;
2305         phys_size_t total_size = 0;
2306
2307         /*------------------------------------------------------------------
2308          * Reset the rank_base_address.
2309          *-----------------------------------------------------------------*/
2310         rank_reg   = SDRAM_R0BAS;
2311
2312         rank_base_addr = 0x00000000;
2313
2314         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2315                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2316                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2317                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2318                                 num_ranks = (num_ranks & 0x0F) + 1;
2319                         else
2320                                 num_ranks = num_ranks & 0x0F;
2321
2322                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2323
2324                         /*------------------------------------------------------------------
2325                          * Set the sizes
2326                          *-----------------------------------------------------------------*/
2327                         baseadd_size = 0;
2328                         switch (rank_size_id) {
2329                         case 0x01:
2330                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2331                                 total_size = 1024;
2332                                 break;
2333                         case 0x02:
2334                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2335                                 total_size = 2048;
2336                                 break;
2337                         case 0x04:
2338                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2339                                 total_size = 4096;
2340                                 break;
2341                         case 0x08:
2342                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2343                                 total_size = 32;
2344                                 break;
2345                         case 0x10:
2346                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2347                                 total_size = 64;
2348                                 break;
2349                         case 0x20:
2350                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2351                                 total_size = 128;
2352                                 break;
2353                         case 0x40:
2354                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2355                                 total_size = 256;
2356                                 break;
2357                         case 0x80:
2358                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2359                                 total_size = 512;
2360                                 break;
2361                         default:
2362                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2363                                        (unsigned int)dimm_num);
2364                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2365                                        (unsigned int)rank_size_id);
2366                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2367                                 spd_ddr_init_hang ();
2368                         }
2369                         rank_size_bytes = total_size << 20;
2370
2371                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2372                                 bank_0_populated = 1;
2373
2374                         for (i = 0; i < num_ranks; i++) {
2375                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2376                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2377                                            baseadd_size));
2378                                 rank_base_addr += rank_size_bytes;
2379                         }
2380                 }
2381         }
2382
2383 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2384     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2385     defined(CONFIG_460SX)
2386         /*
2387          * Enable high bandwidth access
2388          * This is currently not used, but with this setup
2389          * it is possible to use it later on in e.g. the Linux
2390          * EMAC driver for performance gain.
2391          */
2392         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2393         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2394
2395         /*
2396          * Set optimal value for Memory Queue HB/LL Configuration registers
2397          */
2398         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2399               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2400               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2401         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2402               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2403               SDRAM_CONF1LL_RPLM);
2404         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2405 #endif
2406 }
2407
2408 /*-----------------------------------------------------------------------------+
2409  * is_ecc_enabled.
2410  *-----------------------------------------------------------------------------*/
2411 static unsigned long is_ecc_enabled(void)
2412 {
2413         unsigned long dimm_num;
2414         unsigned long ecc;
2415         unsigned long val;
2416
2417         ecc = 0;
2418         /* loop through all the DIMM slots on the board */
2419         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2420                 mfsdram(SDRAM_MCOPT1, val);
2421                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2422         }
2423
2424         return ecc;
2425 }
2426
2427 #ifdef CONFIG_DDR_ECC
2428 /*-----------------------------------------------------------------------------+
2429  * program_ecc.
2430  *-----------------------------------------------------------------------------*/
2431 static void program_ecc(unsigned long *dimm_populated,
2432                         unsigned char *iic0_dimm_addr,
2433                         unsigned long num_dimm_banks,
2434                         unsigned long tlb_word2_i_value)
2435 {
2436         unsigned long dimm_num;
2437         unsigned long ecc;
2438
2439         ecc = 0;
2440         /* loop through all the DIMM slots on the board */
2441         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2442                 /* If a dimm is installed in a particular slot ... */
2443                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2444                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2445         }
2446         if (ecc == 0)
2447                 return;
2448
2449         do_program_ecc(tlb_word2_i_value);
2450 }
2451 #endif
2452
2453 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2454 /*-----------------------------------------------------------------------------+
2455  * program_DQS_calibration.
2456  *-----------------------------------------------------------------------------*/
2457 static void program_DQS_calibration(unsigned long *dimm_populated,
2458                                     unsigned char *iic0_dimm_addr,
2459                                     unsigned long num_dimm_banks)
2460 {
2461         unsigned long val;
2462
2463 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2464         mtsdram(SDRAM_RQDC, 0x80000037);
2465         mtsdram(SDRAM_RDCC, 0x40000000);
2466         mtsdram(SDRAM_RFDC, 0x000001DF);
2467
2468         test();
2469 #else
2470         /*------------------------------------------------------------------
2471          * Program RDCC register
2472          * Read sample cycle auto-update enable
2473          *-----------------------------------------------------------------*/
2474
2475         mfsdram(SDRAM_RDCC, val);
2476         mtsdram(SDRAM_RDCC,
2477                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2478                 | SDRAM_RDCC_RSAE_ENABLE);
2479
2480         /*------------------------------------------------------------------
2481          * Program RQDC register
2482          * Internal DQS delay mechanism enable
2483          *-----------------------------------------------------------------*/
2484         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2485
2486         /*------------------------------------------------------------------
2487          * Program RFDC register
2488          * Set Feedback Fractional Oversample
2489          * Auto-detect read sample cycle enable
2490          * Set RFOS to 1/4 of memclk cycle (0x3f)
2491          *-----------------------------------------------------------------*/
2492         mfsdram(SDRAM_RFDC, val);
2493         mtsdram(SDRAM_RFDC,
2494                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2495                          SDRAM_RFDC_RFFD_MASK))
2496                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2497                    SDRAM_RFDC_RFFD_ENCODE(0)));
2498
2499         DQS_calibration_process();
2500 #endif
2501 }
2502
2503 static int short_mem_test(void)
2504 {
2505         u32 *membase;
2506         u32 bxcr_num;
2507         u32 bxcf;
2508         int i;
2509         int j;
2510         phys_size_t base_addr;
2511         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2512                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2513                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2514                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2515                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2516                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2517                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2518                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2519                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2520                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2521                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2522                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2523                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2524                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2525                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2526                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2527                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2528         int l;
2529
2530         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2531                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2532
2533                 /* Banks enabled */
2534                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2535                         /* Bank is enabled */
2536
2537                         /*
2538                          * Only run test on accessable memory (below 2GB)
2539                          */
2540                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2541                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2542                                 continue;
2543
2544                         /*------------------------------------------------------------------
2545                          * Run the short memory test.
2546                          *-----------------------------------------------------------------*/
2547                         membase = (u32 *)(u32)base_addr;
2548
2549                         for (i = 0; i < NUMMEMTESTS; i++) {
2550                                 for (j = 0; j < NUMMEMWORDS; j++) {
2551                                         membase[j] = test[i][j];
2552                                         ppcDcbf((u32)&(membase[j]));
2553                                 }
2554                                 sync();
2555                                 for (l=0; l<NUMLOOPS; l++) {
2556                                         for (j = 0; j < NUMMEMWORDS; j++) {
2557                                                 if (membase[j] != test[i][j]) {
2558                                                         ppcDcbf((u32)&(membase[j]));
2559                                                         return 0;
2560                                                 }
2561                                                 ppcDcbf((u32)&(membase[j]));
2562                                         }
2563                                         sync();
2564                                 }
2565                         }
2566                 }       /* if bank enabled */
2567         }               /* for bxcf_num */
2568
2569         return 1;
2570 }
2571
2572 #ifndef HARD_CODED_DQS
2573 /*-----------------------------------------------------------------------------+
2574  * DQS_calibration_process.
2575  *-----------------------------------------------------------------------------*/
2576 static void DQS_calibration_process(void)
2577 {
2578         unsigned long rfdc_reg;
2579         unsigned long rffd;
2580         unsigned long val;
2581         long rffd_average;
2582         long max_start;
2583         long min_end;
2584         unsigned long begin_rqfd[MAXRANKS];
2585         unsigned long begin_rffd[MAXRANKS];
2586         unsigned long end_rqfd[MAXRANKS];
2587         unsigned long end_rffd[MAXRANKS];
2588         char window_found;
2589         unsigned long dlycal;
2590         unsigned long dly_val;
2591         unsigned long max_pass_length;
2592         unsigned long current_pass_length;
2593         unsigned long current_fail_length;
2594         unsigned long current_start;
2595         long max_end;
2596         unsigned char fail_found;
2597         unsigned char pass_found;
2598 #if !defined(CONFIG_DDR_RQDC_FIXED)
2599         u32 rqdc_reg;
2600         u32 rqfd;
2601         u32 rqfd_start;
2602         u32 rqfd_average;
2603         int loopi = 0;
2604         char str[] = "Auto calibration -";
2605         char slash[] = "\\|/-\\|/-";
2606
2607         /*------------------------------------------------------------------
2608          * Test to determine the best read clock delay tuning bits.
2609          *
2610          * Before the DDR controller can be used, the read clock delay needs to be
2611          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2612          * This value cannot be hardcoded into the program because it changes
2613          * depending on the board's setup and environment.
2614          * To do this, all delay values are tested to see if they
2615          * work or not.  By doing this, you get groups of fails with groups of
2616          * passing values.  The idea is to find the start and end of a passing
2617          * window and take the center of it to use as the read clock delay.
2618          *
2619          * A failure has to be seen first so that when we hit a pass, we know
2620          * that it is truely the start of the window.  If we get passing values
2621          * to start off with, we don't know if we are at the start of the window.
2622          *
2623          * The code assumes that a failure will always be found.
2624          * If a failure is not found, there is no easy way to get the middle
2625          * of the passing window.  I guess we can pretty much pick any value
2626          * but some values will be better than others.  Since the lowest speed
2627          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2628          * from experimentation it is safe to say you will always have a failure.
2629          *-----------------------------------------------------------------*/
2630
2631         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2632         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2633
2634         puts(str);
2635
2636 calibration_loop:
2637         mfsdram(SDRAM_RQDC, rqdc_reg);
2638         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2639                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2640 #else /* CONFIG_DDR_RQDC_FIXED */
2641         /*
2642          * On Katmai the complete auto-calibration somehow doesn't seem to
2643          * produce the best results, meaning optimal values for RQFD/RFFD.
2644          * This was discovered by GDA using a high bandwidth scope,
2645          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2646          * so now on Katmai "only" RFFD is auto-calibrated.
2647          */
2648         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2649 #endif /* CONFIG_DDR_RQDC_FIXED */
2650
2651         max_start = 0;
2652         min_end = 0;
2653         begin_rqfd[0] = 0;
2654         begin_rffd[0] = 0;
2655         begin_rqfd[1] = 0;
2656         begin_rffd[1] = 0;
2657         end_rqfd[0] = 0;
2658         end_rffd[0] = 0;
2659         end_rqfd[1] = 0;
2660         end_rffd[1] = 0;
2661         window_found = FALSE;
2662
2663         max_pass_length = 0;
2664         max_start = 0;
2665         max_end = 0;
2666         current_pass_length = 0;
2667         current_fail_length = 0;
2668         current_start = 0;
2669         window_found = FALSE;
2670         fail_found = FALSE;
2671         pass_found = FALSE;
2672
2673         /*
2674          * get the delay line calibration register value
2675          */
2676         mfsdram(SDRAM_DLCR, dlycal);
2677         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2678
2679         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2680                 mfsdram(SDRAM_RFDC, rfdc_reg);
2681                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2682
2683                 /*------------------------------------------------------------------
2684                  * Set the timing reg for the test.
2685                  *-----------------------------------------------------------------*/
2686                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2687
2688                 /*------------------------------------------------------------------
2689                  * See if the rffd value passed.
2690                  *-----------------------------------------------------------------*/
2691                 if (short_mem_test()) {
2692                         if (fail_found == TRUE) {
2693                                 pass_found = TRUE;
2694                                 if (current_pass_length == 0)
2695                                         current_start = rffd;
2696
2697                                 current_fail_length = 0;
2698                                 current_pass_length++;
2699
2700                                 if (current_pass_length > max_pass_length) {
2701                                         max_pass_length = current_pass_length;
2702                                         max_start = current_start;
2703                                         max_end = rffd;
2704                                 }
2705                         }
2706                 } else {
2707                         current_pass_length = 0;
2708                         current_fail_length++;
2709
2710                         if (current_fail_length >= (dly_val >> 2)) {
2711                                 if (fail_found == FALSE) {
2712                                         fail_found = TRUE;
2713                                 } else if (pass_found == TRUE) {
2714                                         window_found = TRUE;
2715                                         break;
2716                                 }
2717                         }
2718                 }
2719         }               /* for rffd */
2720
2721         /*------------------------------------------------------------------
2722          * Set the average RFFD value
2723          *-----------------------------------------------------------------*/
2724         rffd_average = ((max_start + max_end) >> 1);
2725
2726         if (rffd_average < 0)
2727                 rffd_average = 0;
2728
2729         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2730                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2731         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2732         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2733
2734 #if !defined(CONFIG_DDR_RQDC_FIXED)
2735         max_pass_length = 0;
2736         max_start = 0;
2737         max_end = 0;
2738         current_pass_length = 0;
2739         current_fail_length = 0;
2740         current_start = 0;
2741         window_found = FALSE;
2742         fail_found = FALSE;
2743         pass_found = FALSE;
2744
2745         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2746                 mfsdram(SDRAM_RQDC, rqdc_reg);
2747                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2748
2749                 /*------------------------------------------------------------------
2750                  * Set the timing reg for the test.
2751                  *-----------------------------------------------------------------*/
2752                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2753
2754                 /*------------------------------------------------------------------
2755                  * See if the rffd value passed.
2756                  *-----------------------------------------------------------------*/
2757                 if (short_mem_test()) {
2758                         if (fail_found == TRUE) {
2759                                 pass_found = TRUE;
2760                                 if (current_pass_length == 0)
2761                                         current_start = rqfd;
2762
2763                                 current_fail_length = 0;
2764                                 current_pass_length++;
2765
2766                                 if (current_pass_length > max_pass_length) {
2767                                         max_pass_length = current_pass_length;
2768                                         max_start = current_start;
2769                                         max_end = rqfd;
2770                                 }
2771                         }
2772                 } else {
2773                         current_pass_length = 0;
2774                         current_fail_length++;
2775
2776                         if (fail_found == FALSE) {
2777                                 fail_found = TRUE;
2778                         } else if (pass_found == TRUE) {
2779                                 window_found = TRUE;
2780                                 break;
2781                         }
2782                 }
2783         }
2784
2785         rqfd_average = ((max_start + max_end) >> 1);
2786
2787         /*------------------------------------------------------------------
2788          * Make sure we found the valid read passing window.  Halt if not
2789          *-----------------------------------------------------------------*/
2790         if (window_found == FALSE) {
2791                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2792                         putc('\b');
2793                         putc(slash[loopi++ % 8]);
2794
2795                         /* try again from with a different RQFD start value */
2796                         rqfd_start++;
2797                         goto calibration_loop;
2798                 }
2799
2800                 printf("\nERROR: Cannot determine a common read delay for the "
2801                        "DIMM(s) installed.\n");
2802                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2803                 ppc4xx_ibm_ddr2_register_dump();
2804                 spd_ddr_init_hang ();
2805         }
2806
2807         if (rqfd_average < 0)
2808                 rqfd_average = 0;
2809
2810         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2811                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2812
2813         mtsdram(SDRAM_RQDC,
2814                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2815                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2816
2817         blank_string(strlen(str));
2818 #endif /* CONFIG_DDR_RQDC_FIXED */
2819
2820         /*
2821          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2822          * PowerPC440SP/SPe DDR2 application note:
2823          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2824          */
2825         mfsdram(SDRAM_RTSR, val);
2826         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2827                 mfsdram(SDRAM_RDCC, val);
2828                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2829                         val += 0x40000000;
2830                         mtsdram(SDRAM_RDCC, val);
2831                 }
2832         }
2833
2834         mfsdram(SDRAM_DLCR, val);
2835         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2836         mfsdram(SDRAM_RQDC, val);
2837         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2838         mfsdram(SDRAM_RFDC, val);
2839         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2840         mfsdram(SDRAM_RDCC, val);
2841         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2842 }
2843 #else /* calibration test with hardvalues */
2844 /*-----------------------------------------------------------------------------+
2845  * DQS_calibration_process.
2846  *-----------------------------------------------------------------------------*/
2847 static void test(void)
2848 {
2849         unsigned long dimm_num;
2850         unsigned long ecc_temp;
2851         unsigned long i, j;
2852         unsigned long *membase;
2853         unsigned long bxcf[MAXRANKS];
2854         unsigned long val;
2855         char window_found;
2856         char begin_found[MAXDIMMS];
2857         char end_found[MAXDIMMS];
2858         char search_end[MAXDIMMS];
2859         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2860                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2861                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2862                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2863                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2864                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2865                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2866                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2867                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2868                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2869                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2870                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2871                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2872                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2873                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2874                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2875                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2876
2877         /*------------------------------------------------------------------
2878          * Test to determine the best read clock delay tuning bits.
2879          *
2880          * Before the DDR controller can be used, the read clock delay needs to be
2881          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2882          * This value cannot be hardcoded into the program because it changes
2883          * depending on the board's setup and environment.
2884          * To do this, all delay values are tested to see if they
2885          * work or not.  By doing this, you get groups of fails with groups of
2886          * passing values.  The idea is to find the start and end of a passing
2887          * window and take the center of it to use as the read clock delay.
2888          *
2889          * A failure has to be seen first so that when we hit a pass, we know
2890          * that it is truely the start of the window.  If we get passing values
2891          * to start off with, we don't know if we are at the start of the window.
2892          *
2893          * The code assumes that a failure will always be found.
2894          * If a failure is not found, there is no easy way to get the middle
2895          * of the passing window.  I guess we can pretty much pick any value
2896          * but some values will be better than others.  Since the lowest speed
2897          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2898          * from experimentation it is safe to say you will always have a failure.
2899          *-----------------------------------------------------------------*/
2900         mfsdram(SDRAM_MCOPT1, ecc_temp);
2901         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2902         mfsdram(SDRAM_MCOPT1, val);
2903         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2904                 SDRAM_MCOPT1_MCHK_NON);
2905
2906         window_found = FALSE;
2907         begin_found[0] = FALSE;
2908         end_found[0] = FALSE;
2909         search_end[0] = FALSE;
2910         begin_found[1] = FALSE;
2911         end_found[1] = FALSE;
2912         search_end[1] = FALSE;
2913
2914         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2915                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2916
2917                 /* Banks enabled */
2918                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2919
2920                         /* Bank is enabled */
2921                         membase =
2922                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2923
2924                         /*------------------------------------------------------------------
2925                          * Run the short memory test.
2926                          *-----------------------------------------------------------------*/
2927                         for (i = 0; i < NUMMEMTESTS; i++) {
2928                                 for (j = 0; j < NUMMEMWORDS; j++) {
2929                                         membase[j] = test[i][j];
2930                                         ppcDcbf((u32)&(membase[j]));
2931                                 }
2932                                 sync();
2933                                 for (j = 0; j < NUMMEMWORDS; j++) {
2934                                         if (membase[j] != test[i][j]) {
2935                                                 ppcDcbf((u32)&(membase[j]));
2936                                                 break;
2937                                         }
2938                                         ppcDcbf((u32)&(membase[j]));
2939                                 }
2940                                 sync();
2941                                 if (j < NUMMEMWORDS)
2942                                         break;
2943                         }
2944
2945                         /*------------------------------------------------------------------
2946                          * See if the rffd value passed.
2947                          *-----------------------------------------------------------------*/
2948                         if (i < NUMMEMTESTS) {
2949                                 if ((end_found[dimm_num] == FALSE) &&
2950                                     (search_end[dimm_num] == TRUE)) {
2951                                         end_found[dimm_num] = TRUE;
2952                                 }
2953                                 if ((end_found[0] == TRUE) &&
2954                                     (end_found[1] == TRUE))
2955                                         break;
2956                         } else {
2957                                 if (begin_found[dimm_num] == FALSE) {
2958                                         begin_found[dimm_num] = TRUE;
2959                                         search_end[dimm_num] = TRUE;
2960                                 }
2961                         }
2962                 } else {
2963                         begin_found[dimm_num] = TRUE;
2964                         end_found[dimm_num] = TRUE;
2965                 }
2966         }
2967
2968         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2969                 window_found = TRUE;
2970
2971         /*------------------------------------------------------------------
2972          * Make sure we found the valid read passing window.  Halt if not
2973          *-----------------------------------------------------------------*/
2974         if (window_found == FALSE) {
2975                 printf("ERROR: Cannot determine a common read delay for the "
2976                        "DIMM(s) installed.\n");
2977                 spd_ddr_init_hang ();
2978         }
2979
2980         /*------------------------------------------------------------------
2981          * Restore the ECC variable to what it originally was
2982          *-----------------------------------------------------------------*/
2983         mtsdram(SDRAM_MCOPT1,
2984                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2985                 | ecc_temp);
2986 }
2987 #endif /* !HARD_CODED_DQS */
2988 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2989
2990 #else /* CONFIG_SPD_EEPROM */
2991
2992 /*-----------------------------------------------------------------------------+
2993  * is_ecc_enabled
2994  *-----------------------------------------------------------------------------*/
2995 static unsigned long is_ecc_enabled(void)
2996 {
2997         unsigned long ecc;
2998         unsigned long val;
2999
3000         ecc = 0;
3001         mfsdram(SDRAM_MCOPT1, val);
3002         ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
3003
3004         return ecc;
3005 }
3006
3007 /*-----------------------------------------------------------------------------
3008  * Function:    initdram
3009  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
3010  *              The configuration is performed using static, compile-
3011  *              time parameters.
3012  *              Configures the PPC405EX(r) and PPC460EX/GT
3013  *---------------------------------------------------------------------------*/
3014 phys_size_t initdram(int board_type)
3015 {
3016         /*
3017          * Only run this SDRAM init code once. For NAND booting
3018          * targets like Kilauea, we call initdram() early from the
3019          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
3020          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
3021          * which calls initdram() again. This time the controller
3022          * mustn't be reconfigured again since we're already running
3023          * from SDRAM.
3024          */
3025 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
3026         unsigned long val;
3027
3028 #if defined(CONFIG_440)
3029         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
3030         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
3031         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
3032         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
3033         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
3034         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
3035         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
3036         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
3037         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
3038 #endif
3039
3040         /* Set Memory Bank Configuration Registers */
3041
3042         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
3043         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
3044         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
3045         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
3046
3047         /* Set Memory Clock Timing Register */
3048
3049         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
3050
3051         /* Set Refresh Time Register */
3052
3053         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
3054
3055         /* Set SDRAM Timing Registers */
3056
3057         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
3058         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
3059         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
3060
3061         /* Set Mode and Extended Mode Registers */
3062
3063         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
3064         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
3065
3066         /* Set Memory Controller Options 1 Register */
3067
3068         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
3069
3070         /* Set Manual Initialization Control Registers */
3071
3072         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
3073         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
3074         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
3075         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
3076         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
3077         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
3078         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
3079         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
3080         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
3081         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
3082         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
3083         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
3084         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
3085         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
3086         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
3087         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
3088
3089         /* Set On-Die Termination Registers */
3090
3091         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
3092         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
3093         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
3094
3095         /* Set Write Timing Register */
3096
3097         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
3098
3099         /*
3100          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3101          * SDRAM0_MCOPT2[IPTR] = 1
3102          */
3103
3104         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3105                                SDRAM_MCOPT2_IPTR_EXECUTE));
3106
3107         /*
3108          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3109          * completion of initialization.
3110          */
3111
3112         do {
3113                 mfsdram(SDRAM_MCSTAT, val);
3114         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3115
3116         /* Set Delay Control Registers */
3117
3118         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
3119
3120 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3121         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
3122         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3123         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3124 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3125
3126         /*
3127          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3128          */
3129
3130         mfsdram(SDRAM_MCOPT2, val);
3131         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3132
3133 #if defined(CONFIG_440)
3134         /*
3135          * Program TLB entries with caches enabled, for best performace
3136          * while auto-calibrating and ECC generation
3137          */
3138         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3139 #endif
3140
3141 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3142 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3143         /*------------------------------------------------------------------
3144          | DQS calibration.
3145          +-----------------------------------------------------------------*/
3146         DQS_autocalibration();
3147 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3148 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3149
3150 #if defined(CONFIG_DDR_ECC)
3151         do_program_ecc(0);
3152 #endif /* defined(CONFIG_DDR_ECC) */
3153
3154 #if defined(CONFIG_440)
3155         /*
3156          * Now after initialization (auto-calibration and ECC generation)
3157          * remove the TLB entries with caches enabled and program again with
3158          * desired cache functionality
3159          */
3160         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3161         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3162 #endif
3163
3164         ppc4xx_ibm_ddr2_register_dump();
3165
3166 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3167         /*
3168          * Clear potential errors resulting from auto-calibration.
3169          * If not done, then we could get an interrupt later on when
3170          * exceptions are enabled.
3171          */
3172         set_mcsr(get_mcsr());
3173 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3174
3175 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3176
3177         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3178 }
3179 #endif /* CONFIG_SPD_EEPROM */
3180
3181 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3182 #if defined(CONFIG_440)
3183 u32 mfdcr_any(u32 dcr)
3184 {
3185         u32 val;
3186
3187         switch (dcr) {
3188         case SDRAM_R0BAS + 0:
3189                 val = mfdcr(SDRAM_R0BAS + 0);
3190                 break;
3191         case SDRAM_R0BAS + 1:
3192                 val = mfdcr(SDRAM_R0BAS + 1);
3193                 break;
3194         case SDRAM_R0BAS + 2:
3195                 val = mfdcr(SDRAM_R0BAS + 2);
3196                 break;
3197         case SDRAM_R0BAS + 3:
3198                 val = mfdcr(SDRAM_R0BAS + 3);
3199                 break;
3200         default:
3201                 printf("DCR %d not defined in case statement!!!\n", dcr);
3202                 val = 0; /* just to satisfy the compiler */
3203         }
3204
3205         return val;
3206 }
3207
3208 void mtdcr_any(u32 dcr, u32 val)
3209 {
3210         switch (dcr) {
3211         case SDRAM_R0BAS + 0:
3212                 mtdcr(SDRAM_R0BAS + 0, val);
3213                 break;
3214         case SDRAM_R0BAS + 1:
3215                 mtdcr(SDRAM_R0BAS + 1, val);
3216                 break;
3217         case SDRAM_R0BAS + 2:
3218                 mtdcr(SDRAM_R0BAS + 2, val);
3219                 break;
3220         case SDRAM_R0BAS + 3:
3221                 mtdcr(SDRAM_R0BAS + 3, val);
3222                 break;
3223         default:
3224                 printf("DCR %d not defined in case statement!!!\n", dcr);
3225         }
3226 }
3227 #endif /* defined(CONFIG_440) */
3228
3229 void blank_string(int size)
3230 {
3231         int i;
3232
3233         for (i = 0; i < size; i++)
3234                 putc('\b');
3235         for (i = 0; i < size; i++)
3236                 putc(' ');
3237         for (i = 0; i < size; i++)
3238                 putc('\b');
3239 }
3240 #endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
3241
3242 inline void ppc4xx_ibm_ddr2_register_dump(void)
3243 {
3244 #if defined(DEBUG)
3245         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3246
3247 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3248      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3249         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3250         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3251         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3252         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3253 #endif /* (defined(CONFIG_440SP) || ... */
3254 #if defined(CONFIG_405EX)
3255         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3256         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3257         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3258         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3259         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3260         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3261 #endif /* defined(CONFIG_405EX) */
3262         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3263         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3264         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3265         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3266         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3267         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3268         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3269         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3270         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3271         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3272         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3273         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3274 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3275      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3276         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3277         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3278         /*
3279          * OPART is only used as a trigger register.
3280          *
3281          * No data is contained in this register, and reading or writing
3282          * to is can cause bad things to happen (hangs). Just skip it and
3283          * report "N/A".
3284          */
3285         printf("%20s = N/A\n", "SDRAM_OPART");
3286 #endif /* defined(CONFIG_440SP) || ... */
3287         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3288         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3289         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3290         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3291         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3292         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3293         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3294         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3295         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3296         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3297         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3298         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3299         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3300         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3301         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3302         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3303         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3304         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3305         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3306         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3307         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3308         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3309         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3310         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3311         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3312         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3313         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3314         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3315         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3316 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3317      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3318         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3319 #endif /* defined(CONFIG_440SP) || ... */
3320         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3321         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3322         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3323 #endif /* defined(DEBUG) */
3324 }
3325
3326 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */