2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those are 440SP/SPe.
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * COPYRIGHT AMCC CORPORATION 2004
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* define DEBUG for debugging output (obviously ;-)) */
41 #include <asm/processor.h>
44 #if defined(CONFIG_SPD_EEPROM) && \
45 (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
47 /*-----------------------------------------------------------------------------+
49 *-----------------------------------------------------------------------------*/
64 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
66 #define ONE_BILLION 1000000000
68 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
70 #define CMD_NOP (7 << 19)
71 #define CMD_PRECHARGE (2 << 19)
72 #define CMD_REFRESH (1 << 19)
73 #define CMD_EMR (0 << 19)
74 #define CMD_READ (5 << 19)
75 #define CMD_WRITE (4 << 19)
77 #define SELECT_MR (0 << 16)
78 #define SELECT_EMR (1 << 16)
79 #define SELECT_EMR2 (2 << 16)
80 #define SELECT_EMR3 (3 << 16)
83 #define DLL_RESET 0x00000100
85 #define WRITE_RECOV_2 (1 << 9)
86 #define WRITE_RECOV_3 (2 << 9)
87 #define WRITE_RECOV_4 (3 << 9)
88 #define WRITE_RECOV_5 (4 << 9)
89 #define WRITE_RECOV_6 (5 << 9)
91 #define BURST_LEN_4 0x00000002
94 #define ODT_0_OHM 0x00000000
95 #define ODT_50_OHM 0x00000044
96 #define ODT_75_OHM 0x00000004
97 #define ODT_150_OHM 0x00000040
99 #define ODS_FULL 0x00000000
100 #define ODS_REDUCED 0x00000002
102 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
103 #define ODT_EB0R (0x80000000 >> 8)
104 #define ODT_EB0W (0x80000000 >> 7)
105 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
106 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
107 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
109 /* Defines for the Read Cycle Delay test */
110 #define NUMMEMTESTS 8
111 #define NUMMEMWORDS 8
112 #define NUMLOOPS 256 /* memory test loops */
114 #undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
117 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
118 * region. Right now the cache should still be disabled in U-Boot because of the
119 * EMAC driver, that need it's buffer descriptor to be located in non cached
122 * If at some time this restriction doesn't apply anymore, just define
123 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
124 * everything correctly.
126 #ifdef CFG_ENABLE_SDRAM_CACHE
127 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
129 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
132 /* Private Structure Definitions */
134 /* enum only to ease code for cas latency setting */
135 typedef enum ddr_cas_id {
143 /*-----------------------------------------------------------------------------+
145 *-----------------------------------------------------------------------------*/
146 static unsigned long sdram_memsize(void);
147 void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
148 static void get_spd_info(unsigned long *dimm_populated,
149 unsigned char *iic0_dimm_addr,
150 unsigned long num_dimm_banks);
151 static void check_mem_type(unsigned long *dimm_populated,
152 unsigned char *iic0_dimm_addr,
153 unsigned long num_dimm_banks);
154 static void check_frequency(unsigned long *dimm_populated,
155 unsigned char *iic0_dimm_addr,
156 unsigned long num_dimm_banks);
157 static void check_rank_number(unsigned long *dimm_populated,
158 unsigned char *iic0_dimm_addr,
159 unsigned long num_dimm_banks);
160 static void check_voltage_type(unsigned long *dimm_populated,
161 unsigned char *iic0_dimm_addr,
162 unsigned long num_dimm_banks);
163 static void program_memory_queue(unsigned long *dimm_populated,
164 unsigned char *iic0_dimm_addr,
165 unsigned long num_dimm_banks);
166 static void program_codt(unsigned long *dimm_populated,
167 unsigned char *iic0_dimm_addr,
168 unsigned long num_dimm_banks);
169 static void program_mode(unsigned long *dimm_populated,
170 unsigned char *iic0_dimm_addr,
171 unsigned long num_dimm_banks,
172 ddr_cas_id_t *selected_cas,
173 int *write_recovery);
174 static void program_tr(unsigned long *dimm_populated,
175 unsigned char *iic0_dimm_addr,
176 unsigned long num_dimm_banks);
177 static void program_rtr(unsigned long *dimm_populated,
178 unsigned char *iic0_dimm_addr,
179 unsigned long num_dimm_banks);
180 static void program_bxcf(unsigned long *dimm_populated,
181 unsigned char *iic0_dimm_addr,
182 unsigned long num_dimm_banks);
183 static void program_copt1(unsigned long *dimm_populated,
184 unsigned char *iic0_dimm_addr,
185 unsigned long num_dimm_banks);
186 static void program_initplr(unsigned long *dimm_populated,
187 unsigned char *iic0_dimm_addr,
188 unsigned long num_dimm_banks,
189 ddr_cas_id_t selected_cas,
191 static unsigned long is_ecc_enabled(void);
192 #ifdef CONFIG_DDR_ECC
193 static void program_ecc(unsigned long *dimm_populated,
194 unsigned char *iic0_dimm_addr,
195 unsigned long num_dimm_banks,
196 unsigned long tlb_word2_i_value);
197 static void program_ecc_addr(unsigned long start_address,
198 unsigned long num_bytes,
199 unsigned long tlb_word2_i_value);
201 static void program_DQS_calibration(unsigned long *dimm_populated,
202 unsigned char *iic0_dimm_addr,
203 unsigned long num_dimm_banks);
204 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
205 static void test(void);
207 static void DQS_calibration_process(void);
210 static void ppc440sp_sdram_register_dump(void);
212 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
213 void dcbz_area(u32 start_address, u32 num_bytes);
216 static u32 mfdcr_any(u32 dcr)
221 case SDRAM_R0BAS + 0:
222 val = mfdcr(SDRAM_R0BAS + 0);
224 case SDRAM_R0BAS + 1:
225 val = mfdcr(SDRAM_R0BAS + 1);
227 case SDRAM_R0BAS + 2:
228 val = mfdcr(SDRAM_R0BAS + 2);
230 case SDRAM_R0BAS + 3:
231 val = mfdcr(SDRAM_R0BAS + 3);
234 printf("DCR %d not defined in case statement!!!\n", dcr);
235 val = 0; /* just to satisfy the compiler */
241 static void mtdcr_any(u32 dcr, u32 val)
244 case SDRAM_R0BAS + 0:
245 mtdcr(SDRAM_R0BAS + 0, val);
247 case SDRAM_R0BAS + 1:
248 mtdcr(SDRAM_R0BAS + 1, val);
250 case SDRAM_R0BAS + 2:
251 mtdcr(SDRAM_R0BAS + 2, val);
253 case SDRAM_R0BAS + 3:
254 mtdcr(SDRAM_R0BAS + 3, val);
257 printf("DCR %d not defined in case statement!!!\n", dcr);
261 static unsigned char spd_read(uchar chip, uint addr)
263 unsigned char data[2];
265 if (i2c_probe(chip) == 0)
266 if (i2c_read(chip, addr, 1, data, 1) == 0)
272 /*-----------------------------------------------------------------------------+
274 *-----------------------------------------------------------------------------*/
275 static unsigned long sdram_memsize(void)
277 unsigned long mem_size;
278 unsigned long mcopt2;
279 unsigned long mcstat;
286 mfsdram(SDRAM_MCOPT2, mcopt2);
287 mfsdram(SDRAM_MCSTAT, mcstat);
289 /* DDR controller must be enabled and not in self-refresh. */
290 /* Otherwise memsize is zero. */
291 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
292 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
293 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
294 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
295 for (i = 0; i < MAXBXCF; i++) {
296 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
298 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
299 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
302 case SDRAM_RXBAS_SDSZ_8:
305 case SDRAM_RXBAS_SDSZ_16:
308 case SDRAM_RXBAS_SDSZ_32:
311 case SDRAM_RXBAS_SDSZ_64:
314 case SDRAM_RXBAS_SDSZ_128:
317 case SDRAM_RXBAS_SDSZ_256:
320 case SDRAM_RXBAS_SDSZ_512:
323 case SDRAM_RXBAS_SDSZ_1024:
326 case SDRAM_RXBAS_SDSZ_2048:
329 case SDRAM_RXBAS_SDSZ_4096:
340 mem_size *= 1024 * 1024;
344 /*-----------------------------------------------------------------------------+
345 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
346 * Note: This routine runs from flash with a stack set up in the chip's
347 * sram space. It is important that the routine does not require .sbss, .bss or
348 * .data sections. It also cannot call routines that require these sections.
349 *-----------------------------------------------------------------------------*/
350 /*-----------------------------------------------------------------------------
352 * Description: Configures SDRAM memory banks for DDR operation.
353 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
354 * via the IIC bus and then configures the DDR SDRAM memory
355 * banks appropriately. If Auto Memory Configuration is
356 * not used, it is assumed that no DIMM is plugged
357 *-----------------------------------------------------------------------------*/
358 long int initdram(int board_type)
360 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
361 unsigned char spd0[MAX_SPD_BYTES];
362 unsigned char spd1[MAX_SPD_BYTES];
363 unsigned char *dimm_spd[MAXDIMMS];
364 unsigned long dimm_populated[MAXDIMMS];
365 unsigned long num_dimm_banks; /* on board dimm banks */
367 ddr_cas_id_t selected_cas;
369 unsigned long dram_size = 0;
371 num_dimm_banks = sizeof(iic0_dimm_addr);
373 /*------------------------------------------------------------------
374 * Set up an array of SPD matrixes.
375 *-----------------------------------------------------------------*/
379 /*------------------------------------------------------------------
380 * Reset the DDR-SDRAM controller.
381 *-----------------------------------------------------------------*/
382 mtsdr(SDR0_SRST, (0x80000000 >> 10));
383 mtsdr(SDR0_SRST, 0x00000000);
386 * Make sure I2C controller is initialized
390 /* switch to correct I2C bus */
391 I2C_SET_BUS(CFG_SPD_BUS_NUM);
392 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
394 /*------------------------------------------------------------------
395 * Clear out the serial presence detect buffers.
396 * Perform IIC reads from the dimm. Fill in the spds.
397 * Check to see if the dimm slots are populated
398 *-----------------------------------------------------------------*/
399 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
401 /*------------------------------------------------------------------
402 * Check the memory type for the dimms plugged.
403 *-----------------------------------------------------------------*/
404 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
406 /*------------------------------------------------------------------
407 * Check the frequency supported for the dimms plugged.
408 *-----------------------------------------------------------------*/
409 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
411 /*------------------------------------------------------------------
412 * Check the total rank number.
413 *-----------------------------------------------------------------*/
414 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
416 /*------------------------------------------------------------------
417 * Check the voltage type for the dimms plugged.
418 *-----------------------------------------------------------------*/
419 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
421 /*------------------------------------------------------------------
422 * Program SDRAM controller options 2 register
423 * Except Enabling of the memory controller.
424 *-----------------------------------------------------------------*/
425 mfsdram(SDRAM_MCOPT2, val);
426 mtsdram(SDRAM_MCOPT2,
428 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
429 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
430 SDRAM_MCOPT2_ISIE_MASK))
431 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
432 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
433 SDRAM_MCOPT2_ISIE_ENABLE));
435 /*------------------------------------------------------------------
436 * Program SDRAM controller options 1 register
437 * Note: Does not enable the memory controller.
438 *-----------------------------------------------------------------*/
439 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
441 /*------------------------------------------------------------------
442 * Set the SDRAM Controller On Die Termination Register
443 *-----------------------------------------------------------------*/
444 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
446 /*------------------------------------------------------------------
447 * Program SDRAM refresh register.
448 *-----------------------------------------------------------------*/
449 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
451 /*------------------------------------------------------------------
452 * Program SDRAM mode register.
453 *-----------------------------------------------------------------*/
454 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
455 &selected_cas, &write_recovery);
457 /*------------------------------------------------------------------
458 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
459 *-----------------------------------------------------------------*/
460 mfsdram(SDRAM_WRDTR, val);
461 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
462 (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
464 /*------------------------------------------------------------------
465 * Set the SDRAM Clock Timing Register
466 *-----------------------------------------------------------------*/
467 mfsdram(SDRAM_CLKTR, val);
468 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
470 /*------------------------------------------------------------------
471 * Program the BxCF registers.
472 *-----------------------------------------------------------------*/
473 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
475 /*------------------------------------------------------------------
476 * Program SDRAM timing registers.
477 *-----------------------------------------------------------------*/
478 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
480 /*------------------------------------------------------------------
481 * Set the Extended Mode register
482 *-----------------------------------------------------------------*/
483 mfsdram(SDRAM_MEMODE, val);
484 mtsdram(SDRAM_MEMODE,
485 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
486 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
487 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
488 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
490 /*------------------------------------------------------------------
491 * Program Initialization preload registers.
492 *-----------------------------------------------------------------*/
493 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
494 selected_cas, write_recovery);
496 /*------------------------------------------------------------------
497 * Delay to ensure 200usec have elapsed since reset.
498 *-----------------------------------------------------------------*/
501 /*------------------------------------------------------------------
502 * Set the memory queue core base addr.
503 *-----------------------------------------------------------------*/
504 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
506 /*------------------------------------------------------------------
507 * Program SDRAM controller options 2 register
508 * Enable the memory controller.
509 *-----------------------------------------------------------------*/
510 mfsdram(SDRAM_MCOPT2, val);
511 mtsdram(SDRAM_MCOPT2,
512 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
513 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
514 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
516 /*------------------------------------------------------------------
517 * Wait for SDRAM_CFG0_DC_EN to complete.
518 *-----------------------------------------------------------------*/
520 mfsdram(SDRAM_MCSTAT, val);
521 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
523 /* get installed memory size */
524 dram_size = sdram_memsize();
526 /* and program tlb entries for this size (dynamic) */
527 program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
529 /*------------------------------------------------------------------
531 *-----------------------------------------------------------------*/
532 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
534 #ifdef CONFIG_DDR_ECC
535 /*------------------------------------------------------------------
536 * If ecc is enabled, initialize the parity bits.
537 *-----------------------------------------------------------------*/
538 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
542 ppc440sp_sdram_register_dump();
548 static void get_spd_info(unsigned long *dimm_populated,
549 unsigned char *iic0_dimm_addr,
550 unsigned long num_dimm_banks)
552 unsigned long dimm_num;
553 unsigned long dimm_found;
554 unsigned char num_of_bytes;
555 unsigned char total_size;
558 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
562 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
563 debug("\nspd_read(0x%x) returned %d\n",
564 iic0_dimm_addr[dimm_num], num_of_bytes);
565 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
566 debug("spd_read(0x%x) returned %d\n",
567 iic0_dimm_addr[dimm_num], total_size);
569 if ((num_of_bytes != 0) && (total_size != 0)) {
570 dimm_populated[dimm_num] = TRUE;
572 debug("DIMM slot %lu: populated\n", dimm_num);
574 dimm_populated[dimm_num] = FALSE;
575 debug("DIMM slot %lu: Not populated\n", dimm_num);
579 if (dimm_found == FALSE) {
580 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
585 #ifdef CONFIG_ADD_RAM_INFO
586 void board_add_ram_info(int use_default)
588 PPC440_SYS_INFO board_cfg;
591 if (is_ecc_enabled())
596 get_sys_info(&board_cfg);
598 mfsdr(SDR0_DDR0, val);
599 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
600 printf(" enabled, %d MHz", (val * 2) / 1000000);
602 mfsdram(SDRAM_MMODE, val);
603 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
604 printf(", CL%d)", val);
608 /*------------------------------------------------------------------
609 * For the memory DIMMs installed, this routine verifies that they
610 * really are DDR specific DIMMs.
611 *-----------------------------------------------------------------*/
612 static void check_mem_type(unsigned long *dimm_populated,
613 unsigned char *iic0_dimm_addr,
614 unsigned long num_dimm_banks)
616 unsigned long dimm_num;
617 unsigned long dimm_type;
619 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
620 if (dimm_populated[dimm_num] == TRUE) {
621 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
624 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
625 "slot %d.\n", (unsigned int)dimm_num);
626 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
627 printf("Replace the DIMM module with a supported DIMM.\n\n");
631 printf("ERROR: EDO DIMM detected in slot %d.\n",
632 (unsigned int)dimm_num);
633 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
634 printf("Replace the DIMM module with a supported DIMM.\n\n");
638 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
639 (unsigned int)dimm_num);
640 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
641 printf("Replace the DIMM module with a supported DIMM.\n\n");
645 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
646 (unsigned int)dimm_num);
647 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
648 printf("Replace the DIMM module with a supported DIMM.\n\n");
652 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
653 (unsigned int)dimm_num);
654 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
655 printf("Replace the DIMM module with a supported DIMM.\n\n");
659 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
660 (unsigned int)dimm_num);
661 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
662 printf("Replace the DIMM module with a supported DIMM.\n\n");
666 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
667 dimm_populated[dimm_num] = SDRAM_DDR1;
670 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
671 dimm_populated[dimm_num] = SDRAM_DDR2;
674 printf("ERROR: Unknown DIMM detected in slot %d.\n",
675 (unsigned int)dimm_num);
676 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
677 printf("Replace the DIMM module with a supported DIMM.\n\n");
683 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
684 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
685 && (dimm_populated[dimm_num] != SDRAM_NONE)
686 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
687 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
693 /*------------------------------------------------------------------
694 * For the memory DIMMs installed, this routine verifies that
695 * frequency previously calculated is supported.
696 *-----------------------------------------------------------------*/
697 static void check_frequency(unsigned long *dimm_populated,
698 unsigned char *iic0_dimm_addr,
699 unsigned long num_dimm_banks)
701 unsigned long dimm_num;
702 unsigned long tcyc_reg;
703 unsigned long cycle_time;
704 unsigned long calc_cycle_time;
705 unsigned long sdram_freq;
706 unsigned long sdr_ddrpll;
707 PPC440_SYS_INFO board_cfg;
709 /*------------------------------------------------------------------
710 * Get the board configuration info.
711 *-----------------------------------------------------------------*/
712 get_sys_info(&board_cfg);
714 mfsdr(SDR0_DDR0, sdr_ddrpll);
715 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
718 * calc_cycle_time is calculated from DDR frequency set by board/chip
719 * and is expressed in multiple of 10 picoseconds
720 * to match the way DIMM cycle time is calculated below.
722 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
724 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
725 if (dimm_populated[dimm_num] != SDRAM_NONE) {
726 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
728 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
729 * the higher order nibble (bits 4-7) designates the cycle time
730 * to a granularity of 1ns;
731 * the value presented by the lower order nibble (bits 0-3)
732 * has a granularity of .1ns and is added to the value designated
733 * by the higher nibble. In addition, four lines of the lower order
734 * nibble are assigned to support +.25,+.33, +.66 and +.75.
736 /* Convert from hex to decimal */
737 if ((tcyc_reg & 0x0F) == 0x0D)
738 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
739 else if ((tcyc_reg & 0x0F) == 0x0C)
740 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
741 else if ((tcyc_reg & 0x0F) == 0x0B)
742 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
743 else if ((tcyc_reg & 0x0F) == 0x0A)
744 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
746 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
747 ((tcyc_reg & 0x0F)*10);
748 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
750 if (cycle_time > (calc_cycle_time + 10)) {
752 * the provided sdram cycle_time is too small
753 * for the available DIMM cycle_time.
754 * The additionnal 100ps is here to accept a small incertainty.
756 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
757 "slot %d \n while calculated cycle time is %d ps.\n",
758 (unsigned int)(cycle_time*10),
759 (unsigned int)dimm_num,
760 (unsigned int)(calc_cycle_time*10));
761 printf("Replace the DIMM, or change DDR frequency via "
762 "strapping bits.\n\n");
769 /*------------------------------------------------------------------
770 * For the memory DIMMs installed, this routine verifies two
771 * ranks/banks maximum are availables.
772 *-----------------------------------------------------------------*/
773 static void check_rank_number(unsigned long *dimm_populated,
774 unsigned char *iic0_dimm_addr,
775 unsigned long num_dimm_banks)
777 unsigned long dimm_num;
778 unsigned long dimm_rank;
779 unsigned long total_rank = 0;
781 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
782 if (dimm_populated[dimm_num] != SDRAM_NONE) {
783 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
784 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
785 dimm_rank = (dimm_rank & 0x0F) +1;
787 dimm_rank = dimm_rank & 0x0F;
790 if (dimm_rank > MAXRANKS) {
791 printf("ERROR: DRAM DIMM detected with %d ranks in "
792 "slot %d is not supported.\n", dimm_rank, dimm_num);
793 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
794 printf("Replace the DIMM module with a supported DIMM.\n\n");
797 total_rank += dimm_rank;
799 if (total_rank > MAXRANKS) {
800 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
801 "for all slots.\n", (unsigned int)total_rank);
802 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
803 printf("Remove one of the DIMM modules.\n\n");
809 /*------------------------------------------------------------------
810 * only support 2.5V modules.
811 * This routine verifies this.
812 *-----------------------------------------------------------------*/
813 static void check_voltage_type(unsigned long *dimm_populated,
814 unsigned char *iic0_dimm_addr,
815 unsigned long num_dimm_banks)
817 unsigned long dimm_num;
818 unsigned long voltage_type;
820 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
821 if (dimm_populated[dimm_num] != SDRAM_NONE) {
822 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
823 switch (voltage_type) {
825 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
826 printf("This DIMM is 5.0 Volt/TTL.\n");
827 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
828 (unsigned int)dimm_num);
832 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
833 printf("This DIMM is LVTTL.\n");
834 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
835 (unsigned int)dimm_num);
839 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
840 printf("This DIMM is 1.5 Volt.\n");
841 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
842 (unsigned int)dimm_num);
846 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
847 printf("This DIMM is 3.3 Volt/TTL.\n");
848 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
849 (unsigned int)dimm_num);
853 /* 2.5 Voltage only for DDR1 */
856 /* 1.8 Voltage only for DDR2 */
859 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
860 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
861 (unsigned int)dimm_num);
869 /*-----------------------------------------------------------------------------+
871 *-----------------------------------------------------------------------------*/
872 static void program_copt1(unsigned long *dimm_populated,
873 unsigned char *iic0_dimm_addr,
874 unsigned long num_dimm_banks)
876 unsigned long dimm_num;
877 unsigned long mcopt1;
878 unsigned long ecc_enabled;
879 unsigned long ecc = 0;
880 unsigned long data_width = 0;
881 unsigned long dimm_32bit;
882 unsigned long dimm_64bit;
883 unsigned long registered = 0;
884 unsigned long attribute = 0;
885 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
886 unsigned long bankcount;
887 unsigned long ddrtype;
890 #ifdef CONFIG_DDR_ECC
900 /*------------------------------------------------------------------
901 * Set memory controller options reg 1, SDRAM_MCOPT1.
902 *-----------------------------------------------------------------*/
903 mfsdram(SDRAM_MCOPT1, val);
904 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
905 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
906 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
907 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
908 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
909 SDRAM_MCOPT1_DREF_MASK);
911 mcopt1 |= SDRAM_MCOPT1_QDEP;
912 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
913 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
914 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
915 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
916 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
918 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
919 if (dimm_populated[dimm_num] != SDRAM_NONE) {
920 /* test ecc support */
921 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
922 if (ecc != 0x02) /* ecc not supported */
925 /* test bank count */
926 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
927 if (bankcount == 0x04) /* bank count = 4 */
928 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
929 else /* bank count = 8 */
930 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
933 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
934 /* test for buffered/unbuffered, registered, differential clocks */
935 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
936 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
938 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
940 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
941 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
942 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
943 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
944 if (registered == 1) { /* DDR2 always buffered */
945 /* TODO: what about above comments ? */
946 mcopt1 |= SDRAM_MCOPT1_RDEN;
949 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
950 if ((attribute & 0x02) == 0x00) {
951 /* buffered not supported */
954 mcopt1 |= SDRAM_MCOPT1_RDEN;
959 else if (dimm_num == 1) {
960 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
961 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
962 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
963 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
964 if (registered == 1) {
965 /* DDR2 always buffered */
966 mcopt1 |= SDRAM_MCOPT1_RDEN;
969 if ((attribute & 0x02) == 0x00) {
970 /* buffered not supported */
973 mcopt1 |= SDRAM_MCOPT1_RDEN;
979 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
980 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
981 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
983 switch (data_width) {
993 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
995 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1001 /* verify matching properties */
1002 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1004 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1009 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1010 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1013 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1014 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1015 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1016 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1018 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1022 if (ecc_enabled == TRUE)
1023 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1025 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1027 mtsdram(SDRAM_MCOPT1, mcopt1);
1030 /*-----------------------------------------------------------------------------+
1032 *-----------------------------------------------------------------------------*/
1033 static void program_codt(unsigned long *dimm_populated,
1034 unsigned char *iic0_dimm_addr,
1035 unsigned long num_dimm_banks)
1038 unsigned long modt0 = 0;
1039 unsigned long modt1 = 0;
1040 unsigned long modt2 = 0;
1041 unsigned long modt3 = 0;
1042 unsigned char dimm_num;
1043 unsigned char dimm_rank;
1044 unsigned char total_rank = 0;
1045 unsigned char total_dimm = 0;
1046 unsigned char dimm_type = 0;
1047 unsigned char firstSlot = 0;
1049 /*------------------------------------------------------------------
1050 * Set the SDRAM Controller On Die Termination Register
1051 *-----------------------------------------------------------------*/
1052 mfsdram(SDRAM_CODT, codt);
1053 codt |= (SDRAM_CODT_IO_NMODE
1054 & (~SDRAM_CODT_DQS_SINGLE_END
1055 & ~SDRAM_CODT_CKSE_SINGLE_END
1056 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1057 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1059 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1060 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1061 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1062 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1063 dimm_rank = (dimm_rank & 0x0F) + 1;
1064 dimm_type = SDRAM_DDR2;
1066 dimm_rank = dimm_rank & 0x0F;
1067 dimm_type = SDRAM_DDR1;
1070 total_rank += dimm_rank;
1072 if ((dimm_num == 0) && (total_dimm == 1))
1078 if (dimm_type == SDRAM_DDR2) {
1079 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1080 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1081 if (total_rank == 1) {
1082 codt |= CALC_ODT_R(0);
1083 modt0 = CALC_ODT_W(0);
1088 if (total_rank == 2) {
1089 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1090 modt0 = CALC_ODT_W(0);
1091 modt1 = CALC_ODT_W(0);
1095 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1096 if (total_rank == 1) {
1097 codt |= CALC_ODT_R(2);
1100 modt2 = CALC_ODT_W(2);
1103 if (total_rank == 2) {
1104 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1107 modt2 = CALC_ODT_W(2);
1108 modt3 = CALC_ODT_W(2);
1111 if (total_dimm == 2) {
1112 if (total_rank == 2) {
1113 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1114 modt0 = CALC_ODT_RW(2);
1116 modt2 = CALC_ODT_RW(0);
1119 if (total_rank == 4) {
1120 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
1121 modt0 = CALC_ODT_RW(2);
1123 modt2 = CALC_ODT_RW(0);
1128 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1134 if (total_dimm == 1) {
1135 if (total_rank == 1)
1137 if (total_rank == 2)
1140 if (total_dimm == 2) {
1141 if (total_rank == 2)
1143 if (total_rank == 4)
1148 debug("nb of dimm %d\n", total_dimm);
1149 debug("nb of rank %d\n", total_rank);
1150 if (total_dimm == 1)
1151 debug("dimm in slot %d\n", firstSlot);
1153 mtsdram(SDRAM_CODT, codt);
1154 mtsdram(SDRAM_MODT0, modt0);
1155 mtsdram(SDRAM_MODT1, modt1);
1156 mtsdram(SDRAM_MODT2, modt2);
1157 mtsdram(SDRAM_MODT3, modt3);
1160 /*-----------------------------------------------------------------------------+
1162 *-----------------------------------------------------------------------------*/
1163 static void program_initplr(unsigned long *dimm_populated,
1164 unsigned char *iic0_dimm_addr,
1165 unsigned long num_dimm_banks,
1166 ddr_cas_id_t selected_cas,
1180 /******************************************************
1181 ** Assumption: if more than one DIMM, all DIMMs are the same
1182 ** as already checked in check_memory_type
1183 ******************************************************/
1185 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1186 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1187 mtsdram(SDRAM_INITPLR1, 0x81900400);
1188 mtsdram(SDRAM_INITPLR2, 0x81810000);
1189 mtsdram(SDRAM_INITPLR3, 0xff800162);
1190 mtsdram(SDRAM_INITPLR4, 0x81900400);
1191 mtsdram(SDRAM_INITPLR5, 0x86080000);
1192 mtsdram(SDRAM_INITPLR6, 0x86080000);
1193 mtsdram(SDRAM_INITPLR7, 0x81000062);
1194 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1195 switch (selected_cas) {
1206 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1213 * ToDo - Still a problem with the write recovery:
1214 * On the Corsair CM2X512-5400C4 module, setting write recovery
1215 * in the INITPLR reg to the value calculated in program_mode()
1216 * results in not correctly working DDR2 memory (crash after
1219 * So for now, set the write recovery to 3. This seems to work
1220 * on the Corair module too.
1224 switch (write_recovery) {
1238 printf("ERROR: write recovery not support (%d)", write_recovery);
1243 wr = WRITE_RECOV_3; /* test-only, see description above */
1246 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1247 if (dimm_populated[dimm_num] != SDRAM_NONE)
1249 if (total_dimm == 1) {
1252 } else if (total_dimm == 2) {
1256 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1260 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1261 emr = CMD_EMR | SELECT_EMR | odt | ods;
1262 emr2 = CMD_EMR | SELECT_EMR2;
1263 emr3 = CMD_EMR | SELECT_EMR3;
1264 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1266 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1267 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1268 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1269 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1270 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1272 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1273 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1274 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1275 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1276 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1277 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1278 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1279 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1281 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1286 /*------------------------------------------------------------------
1287 * This routine programs the SDRAM_MMODE register.
1288 * the selected_cas is an output parameter, that will be passed
1289 * by caller to call the above program_initplr( )
1290 *-----------------------------------------------------------------*/
1291 static void program_mode(unsigned long *dimm_populated,
1292 unsigned char *iic0_dimm_addr,
1293 unsigned long num_dimm_banks,
1294 ddr_cas_id_t *selected_cas,
1295 int *write_recovery)
1297 unsigned long dimm_num;
1298 unsigned long sdram_ddr1;
1299 unsigned long t_wr_ns;
1300 unsigned long t_wr_clk;
1301 unsigned long cas_bit;
1302 unsigned long cas_index;
1303 unsigned long sdram_freq;
1304 unsigned long ddr_check;
1305 unsigned long mmode;
1306 unsigned long tcyc_reg;
1307 unsigned long cycle_2_0_clk;
1308 unsigned long cycle_2_5_clk;
1309 unsigned long cycle_3_0_clk;
1310 unsigned long cycle_4_0_clk;
1311 unsigned long cycle_5_0_clk;
1312 unsigned long max_2_0_tcyc_ns_x_100;
1313 unsigned long max_2_5_tcyc_ns_x_100;
1314 unsigned long max_3_0_tcyc_ns_x_100;
1315 unsigned long max_4_0_tcyc_ns_x_100;
1316 unsigned long max_5_0_tcyc_ns_x_100;
1317 unsigned long cycle_time_ns_x_100[3];
1318 PPC440_SYS_INFO board_cfg;
1319 unsigned char cas_2_0_available;
1320 unsigned char cas_2_5_available;
1321 unsigned char cas_3_0_available;
1322 unsigned char cas_4_0_available;
1323 unsigned char cas_5_0_available;
1324 unsigned long sdr_ddrpll;
1326 /*------------------------------------------------------------------
1327 * Get the board configuration info.
1328 *-----------------------------------------------------------------*/
1329 get_sys_info(&board_cfg);
1331 mfsdr(SDR0_DDR0, sdr_ddrpll);
1332 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1333 debug("sdram_freq=%d\n", sdram_freq);
1335 /*------------------------------------------------------------------
1336 * Handle the timing. We need to find the worst case timing of all
1337 * the dimm modules installed.
1338 *-----------------------------------------------------------------*/
1340 cas_2_0_available = TRUE;
1341 cas_2_5_available = TRUE;
1342 cas_3_0_available = TRUE;
1343 cas_4_0_available = TRUE;
1344 cas_5_0_available = TRUE;
1345 max_2_0_tcyc_ns_x_100 = 10;
1346 max_2_5_tcyc_ns_x_100 = 10;
1347 max_3_0_tcyc_ns_x_100 = 10;
1348 max_4_0_tcyc_ns_x_100 = 10;
1349 max_5_0_tcyc_ns_x_100 = 10;
1352 /* loop through all the DIMM slots on the board */
1353 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1354 /* If a dimm is installed in a particular slot ... */
1355 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1356 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1361 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1362 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1363 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1365 /* For a particular DIMM, grab the three CAS values it supports */
1366 for (cas_index = 0; cas_index < 3; cas_index++) {
1367 switch (cas_index) {
1369 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1372 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1375 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1379 if ((tcyc_reg & 0x0F) >= 10) {
1380 if ((tcyc_reg & 0x0F) == 0x0D) {
1381 /* Convert from hex to decimal */
1382 cycle_time_ns_x_100[cas_index] =
1383 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1385 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1386 "in slot %d\n", (unsigned int)dimm_num);
1390 /* Convert from hex to decimal */
1391 cycle_time_ns_x_100[cas_index] =
1392 (((tcyc_reg & 0xF0) >> 4) * 100) +
1393 ((tcyc_reg & 0x0F)*10);
1395 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1396 cycle_time_ns_x_100[cas_index]);
1399 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1400 /* supported for a particular DIMM. */
1405 * DDR devices use the following bitmask for CAS latency:
1406 * Bit 7 6 5 4 3 2 1 0
1407 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1409 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1410 (cycle_time_ns_x_100[cas_index] != 0)) {
1411 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1412 cycle_time_ns_x_100[cas_index]);
1417 cas_4_0_available = FALSE;
1420 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1421 (cycle_time_ns_x_100[cas_index] != 0)) {
1422 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1423 cycle_time_ns_x_100[cas_index]);
1428 cas_3_0_available = FALSE;
1431 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1432 (cycle_time_ns_x_100[cas_index] != 0)) {
1433 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1434 cycle_time_ns_x_100[cas_index]);
1439 cas_2_5_available = FALSE;
1442 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1443 (cycle_time_ns_x_100[cas_index] != 0)) {
1444 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1445 cycle_time_ns_x_100[cas_index]);
1450 cas_2_0_available = FALSE;
1454 * DDR2 devices use the following bitmask for CAS latency:
1455 * Bit 7 6 5 4 3 2 1 0
1456 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1458 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1459 (cycle_time_ns_x_100[cas_index] != 0)) {
1460 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1461 cycle_time_ns_x_100[cas_index]);
1466 cas_5_0_available = FALSE;
1469 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1470 (cycle_time_ns_x_100[cas_index] != 0)) {
1471 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1472 cycle_time_ns_x_100[cas_index]);
1477 cas_4_0_available = FALSE;
1480 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1481 (cycle_time_ns_x_100[cas_index] != 0)) {
1482 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1483 cycle_time_ns_x_100[cas_index]);
1488 cas_3_0_available = FALSE;
1494 /*------------------------------------------------------------------
1495 * Set the SDRAM mode, SDRAM_MMODE
1496 *-----------------------------------------------------------------*/
1497 mfsdram(SDRAM_MMODE, mmode);
1498 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1500 /* add 10 here because of rounding problems */
1501 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1502 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1503 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1504 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1505 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1506 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1507 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1508 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1510 if (sdram_ddr1 == TRUE) { /* DDR1 */
1511 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1512 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1513 *selected_cas = DDR_CAS_2;
1514 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1515 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1516 *selected_cas = DDR_CAS_2_5;
1517 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1518 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1519 *selected_cas = DDR_CAS_3;
1521 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1522 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1523 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1527 debug("cas_3_0_available=%d\n", cas_3_0_available);
1528 debug("cas_4_0_available=%d\n", cas_4_0_available);
1529 debug("cas_5_0_available=%d\n", cas_5_0_available);
1530 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1531 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1532 *selected_cas = DDR_CAS_3;
1533 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1534 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1535 *selected_cas = DDR_CAS_4;
1536 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1537 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1538 *selected_cas = DDR_CAS_5;
1540 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1541 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1542 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1543 printf("cas3=%d cas4=%d cas5=%d\n",
1544 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1545 printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1546 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1551 if (sdram_ddr1 == TRUE)
1552 mmode |= SDRAM_MMODE_WR_DDR1;
1555 /* loop through all the DIMM slots on the board */
1556 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1557 /* If a dimm is installed in a particular slot ... */
1558 if (dimm_populated[dimm_num] != SDRAM_NONE)
1559 t_wr_ns = max(t_wr_ns,
1560 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1564 * convert from nanoseconds to ddr clocks
1565 * round up if necessary
1567 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1568 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1569 if (sdram_freq != ddr_check)
1577 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1580 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1583 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1586 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1589 *write_recovery = t_wr_clk;
1592 debug("CAS latency = %d\n", *selected_cas);
1593 debug("Write recovery = %d\n", *write_recovery);
1595 mtsdram(SDRAM_MMODE, mmode);
1598 /*-----------------------------------------------------------------------------+
1600 *-----------------------------------------------------------------------------*/
1601 static void program_rtr(unsigned long *dimm_populated,
1602 unsigned char *iic0_dimm_addr,
1603 unsigned long num_dimm_banks)
1605 PPC440_SYS_INFO board_cfg;
1606 unsigned long max_refresh_rate;
1607 unsigned long dimm_num;
1608 unsigned long refresh_rate_type;
1609 unsigned long refresh_rate;
1611 unsigned long sdram_freq;
1612 unsigned long sdr_ddrpll;
1615 /*------------------------------------------------------------------
1616 * Get the board configuration info.
1617 *-----------------------------------------------------------------*/
1618 get_sys_info(&board_cfg);
1620 /*------------------------------------------------------------------
1621 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1622 *-----------------------------------------------------------------*/
1623 mfsdr(SDR0_DDR0, sdr_ddrpll);
1624 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1626 max_refresh_rate = 0;
1627 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1628 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1630 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1631 refresh_rate_type &= 0x7F;
1632 switch (refresh_rate_type) {
1634 refresh_rate = 15625;
1637 refresh_rate = 3906;
1640 refresh_rate = 7812;
1643 refresh_rate = 31250;
1646 refresh_rate = 62500;
1649 refresh_rate = 125000;
1653 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1654 (unsigned int)dimm_num);
1655 printf("Replace the DIMM module with a supported DIMM.\n\n");
1660 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1664 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1665 mfsdram(SDRAM_RTR, val);
1666 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1667 (SDRAM_RTR_RINT_ENCODE(rint)));
1670 /*------------------------------------------------------------------
1671 * This routine programs the SDRAM_TRx registers.
1672 *-----------------------------------------------------------------*/
1673 static void program_tr(unsigned long *dimm_populated,
1674 unsigned char *iic0_dimm_addr,
1675 unsigned long num_dimm_banks)
1677 unsigned long dimm_num;
1678 unsigned long sdram_ddr1;
1679 unsigned long t_rp_ns;
1680 unsigned long t_rcd_ns;
1681 unsigned long t_rrd_ns;
1682 unsigned long t_ras_ns;
1683 unsigned long t_rc_ns;
1684 unsigned long t_rfc_ns;
1685 unsigned long t_wpc_ns;
1686 unsigned long t_wtr_ns;
1687 unsigned long t_rpc_ns;
1688 unsigned long t_rp_clk;
1689 unsigned long t_rcd_clk;
1690 unsigned long t_rrd_clk;
1691 unsigned long t_ras_clk;
1692 unsigned long t_rc_clk;
1693 unsigned long t_rfc_clk;
1694 unsigned long t_wpc_clk;
1695 unsigned long t_wtr_clk;
1696 unsigned long t_rpc_clk;
1697 unsigned long sdtr1, sdtr2, sdtr3;
1698 unsigned long ddr_check;
1699 unsigned long sdram_freq;
1700 unsigned long sdr_ddrpll;
1702 PPC440_SYS_INFO board_cfg;
1704 /*------------------------------------------------------------------
1705 * Get the board configuration info.
1706 *-----------------------------------------------------------------*/
1707 get_sys_info(&board_cfg);
1709 mfsdr(SDR0_DDR0, sdr_ddrpll);
1710 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1712 /*------------------------------------------------------------------
1713 * Handle the timing. We need to find the worst case timing of all
1714 * the dimm modules installed.
1715 *-----------------------------------------------------------------*/
1727 /* loop through all the DIMM slots on the board */
1728 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1729 /* If a dimm is installed in a particular slot ... */
1730 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1731 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1736 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1737 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1738 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1739 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1740 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1741 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1745 /*------------------------------------------------------------------
1746 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1747 *-----------------------------------------------------------------*/
1748 mfsdram(SDRAM_SDTR1, sdtr1);
1749 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1750 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1752 /* default values */
1753 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1754 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1756 /* normal operations */
1757 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1758 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1760 mtsdram(SDRAM_SDTR1, sdtr1);
1762 /*------------------------------------------------------------------
1763 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1764 *-----------------------------------------------------------------*/
1765 mfsdram(SDRAM_SDTR2, sdtr2);
1766 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1767 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1768 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1769 SDRAM_SDTR2_RRD_MASK);
1772 * convert t_rcd from nanoseconds to ddr clocks
1773 * round up if necessary
1775 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1776 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1777 if (sdram_freq != ddr_check)
1780 switch (t_rcd_clk) {
1783 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1786 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1789 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1792 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1795 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1799 if (sdram_ddr1 == TRUE) { /* DDR1 */
1800 if (sdram_freq < 200000000) {
1801 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1802 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1803 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1805 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1806 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1807 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1810 /* loop through all the DIMM slots on the board */
1811 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1812 /* If a dimm is installed in a particular slot ... */
1813 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1814 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1815 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1816 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1821 * convert from nanoseconds to ddr clocks
1822 * round up if necessary
1824 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1825 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1826 if (sdram_freq != ddr_check)
1829 switch (t_wpc_clk) {
1833 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1836 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1839 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1842 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1845 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1850 * convert from nanoseconds to ddr clocks
1851 * round up if necessary
1853 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1854 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1855 if (sdram_freq != ddr_check)
1858 switch (t_wtr_clk) {
1861 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1864 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1867 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1870 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1875 * convert from nanoseconds to ddr clocks
1876 * round up if necessary
1878 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1879 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1880 if (sdram_freq != ddr_check)
1883 switch (t_rpc_clk) {
1887 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1890 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1893 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1899 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1902 * convert t_rrd from nanoseconds to ddr clocks
1903 * round up if necessary
1905 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1906 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1907 if (sdram_freq != ddr_check)
1911 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1913 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1916 * convert t_rp from nanoseconds to ddr clocks
1917 * round up if necessary
1919 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1920 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1921 if (sdram_freq != ddr_check)
1929 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1932 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1935 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1938 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1941 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1945 mtsdram(SDRAM_SDTR2, sdtr2);
1947 /*------------------------------------------------------------------
1948 * Set the SDRAM Timing Reg 3, SDRAM_TR3
1949 *-----------------------------------------------------------------*/
1950 mfsdram(SDRAM_SDTR3, sdtr3);
1951 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
1952 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1955 * convert t_ras from nanoseconds to ddr clocks
1956 * round up if necessary
1958 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1959 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1960 if (sdram_freq != ddr_check)
1963 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
1966 * convert t_rc from nanoseconds to ddr clocks
1967 * round up if necessary
1969 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
1970 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
1971 if (sdram_freq != ddr_check)
1974 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
1976 /* default xcs value */
1977 sdtr3 |= SDRAM_SDTR3_XCS;
1980 * convert t_rfc from nanoseconds to ddr clocks
1981 * round up if necessary
1983 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
1984 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
1985 if (sdram_freq != ddr_check)
1988 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
1990 mtsdram(SDRAM_SDTR3, sdtr3);
1993 /*-----------------------------------------------------------------------------+
1995 *-----------------------------------------------------------------------------*/
1996 static void program_bxcf(unsigned long *dimm_populated,
1997 unsigned char *iic0_dimm_addr,
1998 unsigned long num_dimm_banks)
2000 unsigned long dimm_num;
2001 unsigned long num_col_addr;
2002 unsigned long num_ranks;
2003 unsigned long num_banks;
2005 unsigned long ind_rank;
2007 unsigned long ind_bank;
2008 unsigned long bank_0_populated;
2010 /*------------------------------------------------------------------
2011 * Set the BxCF regs. First, wipe out the bank config registers.
2012 *-----------------------------------------------------------------*/
2013 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
2014 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2015 mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
2016 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2017 mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
2018 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2019 mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
2020 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2022 mode = SDRAM_BXCF_M_BE_ENABLE;
2024 bank_0_populated = 0;
2026 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2027 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2028 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2029 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2030 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2031 num_ranks = (num_ranks & 0x0F) +1;
2033 num_ranks = num_ranks & 0x0F;
2035 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2037 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2042 switch (num_col_addr) {
2044 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2047 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2050 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2053 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2056 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2059 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2060 (unsigned int)dimm_num);
2061 printf("ERROR: Unsupported value for number of "
2062 "column addresses: %d.\n", (unsigned int)num_col_addr);
2063 printf("Replace the DIMM module with a supported DIMM.\n\n");
2068 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2069 bank_0_populated = 1;
2071 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2072 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
2073 mtdcr(SDRAMC_CFGDATA, mode);
2079 /*------------------------------------------------------------------
2080 * program memory queue.
2081 *-----------------------------------------------------------------*/
2082 static void program_memory_queue(unsigned long *dimm_populated,
2083 unsigned char *iic0_dimm_addr,
2084 unsigned long num_dimm_banks)
2086 unsigned long dimm_num;
2087 unsigned long rank_base_addr;
2088 unsigned long rank_reg;
2089 unsigned long rank_size_bytes;
2090 unsigned long rank_size_id;
2091 unsigned long num_ranks;
2092 unsigned long baseadd_size;
2094 unsigned long bank_0_populated = 0;
2096 /*------------------------------------------------------------------
2097 * Reset the rank_base_address.
2098 *-----------------------------------------------------------------*/
2099 rank_reg = SDRAM_R0BAS;
2101 rank_base_addr = 0x00000000;
2103 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2104 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2105 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2106 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2107 num_ranks = (num_ranks & 0x0F) + 1;
2109 num_ranks = num_ranks & 0x0F;
2111 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2113 /*------------------------------------------------------------------
2115 *-----------------------------------------------------------------*/
2117 rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
2118 switch (rank_size_id) {
2120 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2123 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2126 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2129 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2132 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2135 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2138 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2141 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2142 (unsigned int)dimm_num);
2143 printf("ERROR: Unsupported value for the banksize: %d.\n",
2144 (unsigned int)rank_size_id);
2145 printf("Replace the DIMM module with a supported DIMM.\n\n");
2149 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2150 bank_0_populated = 1;
2152 for (i = 0; i < num_ranks; i++) {
2153 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2154 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2156 rank_base_addr += rank_size_bytes;
2162 /*-----------------------------------------------------------------------------+
2164 *-----------------------------------------------------------------------------*/
2165 static unsigned long is_ecc_enabled(void)
2167 unsigned long dimm_num;
2172 /* loop through all the DIMM slots on the board */
2173 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2174 mfsdram(SDRAM_MCOPT1, val);
2175 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2181 static void blank_string(int size)
2185 for (i=0; i<size; i++)
2187 for (i=0; i<size; i++)
2189 for (i=0; i<size; i++)
2193 #ifdef CONFIG_DDR_ECC
2194 /*-----------------------------------------------------------------------------+
2196 *-----------------------------------------------------------------------------*/
2197 static void program_ecc(unsigned long *dimm_populated,
2198 unsigned char *iic0_dimm_addr,
2199 unsigned long num_dimm_banks,
2200 unsigned long tlb_word2_i_value)
2202 unsigned long mcopt1;
2203 unsigned long mcopt2;
2204 unsigned long mcstat;
2205 unsigned long dimm_num;
2209 /* loop through all the DIMM slots on the board */
2210 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2211 /* If a dimm is installed in a particular slot ... */
2212 if (dimm_populated[dimm_num] != SDRAM_NONE)
2213 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2218 mfsdram(SDRAM_MCOPT1, mcopt1);
2219 mfsdram(SDRAM_MCOPT2, mcopt2);
2221 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2222 /* DDR controller must be enabled and not in self-refresh. */
2223 mfsdram(SDRAM_MCSTAT, mcstat);
2224 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2225 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2226 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2227 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2229 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2236 #ifdef CONFIG_ECC_ERROR_RESET
2238 * Check for ECC errors and reset board upon any error here
2240 * On the Katmai 440SPe eval board, from time to time, the first
2241 * lword write access after DDR2 initializazion with ECC checking
2242 * enabled, leads to an ECC error. I couldn't find a configuration
2243 * without this happening. On my board with the current setup it
2244 * happens about 1 from 10 times.
2246 * The ECC modules used for testing are:
2247 * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2249 * This has to get fixed for the Katmai and tested for the other
2250 * board (440SP/440SPe) that will eventually use this code in the
2255 static void check_ecc(void)
2259 mfsdram(SDRAM_ECCCR, val);
2261 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2262 val, mfdcr(0x4c), mfdcr(0x4e));
2263 printf("ECC error occured, resetting board...\n");
2264 do_reset(NULL, 0, 0, NULL);
2269 static void wait_ddr_idle(void)
2274 mfsdram(SDRAM_MCSTAT, val);
2275 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2278 /*-----------------------------------------------------------------------------+
2280 *-----------------------------------------------------------------------------*/
2281 static void program_ecc_addr(unsigned long start_address,
2282 unsigned long num_bytes,
2283 unsigned long tlb_word2_i_value)
2285 unsigned long current_address;
2286 unsigned long end_address;
2287 unsigned long address_increment;
2288 unsigned long mcopt1;
2289 char str[] = "ECC generation -";
2290 char slash[] = "\\|/-\\|/-";
2294 current_address = start_address;
2295 mfsdram(SDRAM_MCOPT1, mcopt1);
2296 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2297 mtsdram(SDRAM_MCOPT1,
2298 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2304 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2305 /* ECC bit set method for non-cached memory */
2306 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2307 address_increment = 4;
2309 address_increment = 8;
2310 end_address = current_address + num_bytes;
2312 while (current_address < end_address) {
2313 *((unsigned long *)current_address) = 0x00000000;
2314 current_address += address_increment;
2316 if ((loop++ % (2 << 20)) == 0) {
2318 putc(slash[loopi++ % 8]);
2323 /* ECC bit set method for cached memory */
2324 dcbz_area(start_address, num_bytes);
2328 blank_string(strlen(str));
2334 /* clear ECC error repoting registers */
2335 mtsdram(SDRAM_ECCCR, 0xffffffff);
2336 mtdcr(0x4c, 0xffffffff);
2338 mtsdram(SDRAM_MCOPT1,
2339 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2344 #ifdef CONFIG_ECC_ERROR_RESET
2346 * One write to 0 is enough to trigger this ECC error
2347 * (see description above)
2349 out_be32(0, 0x12345678);
2356 /*-----------------------------------------------------------------------------+
2357 * program_DQS_calibration.
2358 *-----------------------------------------------------------------------------*/
2359 static void program_DQS_calibration(unsigned long *dimm_populated,
2360 unsigned char *iic0_dimm_addr,
2361 unsigned long num_dimm_banks)
2365 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2366 mtsdram(SDRAM_RQDC, 0x80000037);
2367 mtsdram(SDRAM_RDCC, 0x40000000);
2368 mtsdram(SDRAM_RFDC, 0x000001DF);
2372 /*------------------------------------------------------------------
2373 * Program RDCC register
2374 * Read sample cycle auto-update enable
2375 *-----------------------------------------------------------------*/
2378 * Modified for the Katmai platform: with some DIMMs, the DDR2
2379 * controller automatically selects the T2 read cycle, but this
2380 * proves unreliable. Go ahead and force the DDR2 controller
2381 * to use the T4 sample and disable the automatic update of the
2384 mfsdram(SDRAM_RDCC, val);
2386 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2387 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2389 /*------------------------------------------------------------------
2390 * Program RQDC register
2391 * Internal DQS delay mechanism enable
2392 *-----------------------------------------------------------------*/
2393 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2395 /*------------------------------------------------------------------
2396 * Program RFDC register
2397 * Set Feedback Fractional Oversample
2398 * Auto-detect read sample cycle enable
2399 *-----------------------------------------------------------------*/
2400 mfsdram(SDRAM_RFDC, val);
2402 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2403 SDRAM_RFDC_RFFD_MASK))
2404 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2405 SDRAM_RFDC_RFFD_ENCODE(0)));
2407 DQS_calibration_process();
2411 static int short_mem_test(void)
2418 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2419 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2420 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2421 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2422 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2423 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2424 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2425 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2426 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2427 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2428 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2429 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2430 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2431 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2432 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2433 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2434 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2437 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2438 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2441 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2442 /* Bank is enabled */
2444 /*------------------------------------------------------------------
2445 * Run the short memory test.
2446 *-----------------------------------------------------------------*/
2447 membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2449 for (i = 0; i < NUMMEMTESTS; i++) {
2450 for (j = 0; j < NUMMEMWORDS; j++) {
2451 membase[j] = test[i][j];
2452 ppcDcbf((u32)&(membase[j]));
2455 for (l=0; l<NUMLOOPS; l++) {
2456 for (j = 0; j < NUMMEMWORDS; j++) {
2457 if (membase[j] != test[i][j]) {
2458 ppcDcbf((u32)&(membase[j]));
2461 ppcDcbf((u32)&(membase[j]));
2466 } /* if bank enabled */
2467 } /* for bxcf_num */
2472 #ifndef HARD_CODED_DQS
2473 /*-----------------------------------------------------------------------------+
2474 * DQS_calibration_process.
2475 *-----------------------------------------------------------------------------*/
2476 static void DQS_calibration_process(void)
2478 unsigned long rfdc_reg;
2480 unsigned long rqdc_reg;
2487 unsigned long begin_rqfd[MAXRANKS];
2488 unsigned long begin_rffd[MAXRANKS];
2489 unsigned long end_rqfd[MAXRANKS];
2490 unsigned long end_rffd[MAXRANKS];
2492 unsigned long dlycal;
2493 unsigned long dly_val;
2494 unsigned long max_pass_length;
2495 unsigned long current_pass_length;
2496 unsigned long current_fail_length;
2497 unsigned long current_start;
2499 unsigned char fail_found;
2500 unsigned char pass_found;
2502 char str[] = "Auto calibration -";
2503 char slash[] = "\\|/-\\|/-";
2506 /*------------------------------------------------------------------
2507 * Test to determine the best read clock delay tuning bits.
2509 * Before the DDR controller can be used, the read clock delay needs to be
2510 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2511 * This value cannot be hardcoded into the program because it changes
2512 * depending on the board's setup and environment.
2513 * To do this, all delay values are tested to see if they
2514 * work or not. By doing this, you get groups of fails with groups of
2515 * passing values. The idea is to find the start and end of a passing
2516 * window and take the center of it to use as the read clock delay.
2518 * A failure has to be seen first so that when we hit a pass, we know
2519 * that it is truely the start of the window. If we get passing values
2520 * to start off with, we don't know if we are at the start of the window.
2522 * The code assumes that a failure will always be found.
2523 * If a failure is not found, there is no easy way to get the middle
2524 * of the passing window. I guess we can pretty much pick any value
2525 * but some values will be better than others. Since the lowest speed
2526 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2527 * from experimentation it is safe to say you will always have a failure.
2528 *-----------------------------------------------------------------*/
2530 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2531 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2536 mfsdram(SDRAM_RQDC, rqdc_reg);
2537 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2538 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2550 window_found = FALSE;
2552 max_pass_length = 0;
2555 current_pass_length = 0;
2556 current_fail_length = 0;
2558 window_found = FALSE;
2563 * get the delay line calibration register value
2565 mfsdram(SDRAM_DLCR, dlycal);
2566 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2568 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2569 mfsdram(SDRAM_RFDC, rfdc_reg);
2570 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2572 /*------------------------------------------------------------------
2573 * Set the timing reg for the test.
2574 *-----------------------------------------------------------------*/
2575 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2577 /*------------------------------------------------------------------
2578 * See if the rffd value passed.
2579 *-----------------------------------------------------------------*/
2580 if (short_mem_test()) {
2581 if (fail_found == TRUE) {
2583 if (current_pass_length == 0)
2584 current_start = rffd;
2586 current_fail_length = 0;
2587 current_pass_length++;
2589 if (current_pass_length > max_pass_length) {
2590 max_pass_length = current_pass_length;
2591 max_start = current_start;
2596 current_pass_length = 0;
2597 current_fail_length++;
2599 if (current_fail_length >= (dly_val >> 2)) {
2600 if (fail_found == FALSE) {
2602 } else if (pass_found == TRUE) {
2603 window_found = TRUE;
2610 /*------------------------------------------------------------------
2611 * Set the average RFFD value
2612 *-----------------------------------------------------------------*/
2613 rffd_average = ((max_start + max_end) >> 1);
2615 if (rffd_average < 0)
2618 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2619 rffd_average = SDRAM_RFDC_RFFD_MAX;
2620 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2621 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2623 max_pass_length = 0;
2626 current_pass_length = 0;
2627 current_fail_length = 0;
2629 window_found = FALSE;
2633 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2634 mfsdram(SDRAM_RQDC, rqdc_reg);
2635 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2637 /*------------------------------------------------------------------
2638 * Set the timing reg for the test.
2639 *-----------------------------------------------------------------*/
2640 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2642 /*------------------------------------------------------------------
2643 * See if the rffd value passed.
2644 *-----------------------------------------------------------------*/
2645 if (short_mem_test()) {
2646 if (fail_found == TRUE) {
2648 if (current_pass_length == 0)
2649 current_start = rqfd;
2651 current_fail_length = 0;
2652 current_pass_length++;
2654 if (current_pass_length > max_pass_length) {
2655 max_pass_length = current_pass_length;
2656 max_start = current_start;
2661 current_pass_length = 0;
2662 current_fail_length++;
2664 if (fail_found == FALSE) {
2666 } else if (pass_found == TRUE) {
2667 window_found = TRUE;
2673 rqfd_average = ((max_start + max_end) >> 1);
2675 /*------------------------------------------------------------------
2676 * Make sure we found the valid read passing window. Halt if not
2677 *-----------------------------------------------------------------*/
2678 if (window_found == FALSE) {
2679 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2681 putc(slash[loopi++ % 8]);
2683 /* try again from with a different RQFD start value */
2685 goto calibration_loop;
2688 printf("\nERROR: Cannot determine a common read delay for the "
2689 "DIMM(s) installed.\n");
2690 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2694 blank_string(strlen(str));
2696 if (rqfd_average < 0)
2699 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2700 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2703 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2704 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2706 mfsdram(SDRAM_DLCR, val);
2707 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2708 mfsdram(SDRAM_RQDC, val);
2709 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2710 mfsdram(SDRAM_RFDC, val);
2711 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2713 #else /* calibration test with hardvalues */
2714 /*-----------------------------------------------------------------------------+
2715 * DQS_calibration_process.
2716 *-----------------------------------------------------------------------------*/
2717 static void test(void)
2719 unsigned long dimm_num;
2720 unsigned long ecc_temp;
2722 unsigned long *membase;
2723 unsigned long bxcf[MAXRANKS];
2726 char begin_found[MAXDIMMS];
2727 char end_found[MAXDIMMS];
2728 char search_end[MAXDIMMS];
2729 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2730 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2731 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2732 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2733 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2734 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2735 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2736 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2737 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2738 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2739 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2740 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2741 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2742 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2743 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2744 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2745 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2747 /*------------------------------------------------------------------
2748 * Test to determine the best read clock delay tuning bits.
2750 * Before the DDR controller can be used, the read clock delay needs to be
2751 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2752 * This value cannot be hardcoded into the program because it changes
2753 * depending on the board's setup and environment.
2754 * To do this, all delay values are tested to see if they
2755 * work or not. By doing this, you get groups of fails with groups of
2756 * passing values. The idea is to find the start and end of a passing
2757 * window and take the center of it to use as the read clock delay.
2759 * A failure has to be seen first so that when we hit a pass, we know
2760 * that it is truely the start of the window. If we get passing values
2761 * to start off with, we don't know if we are at the start of the window.
2763 * The code assumes that a failure will always be found.
2764 * If a failure is not found, there is no easy way to get the middle
2765 * of the passing window. I guess we can pretty much pick any value
2766 * but some values will be better than others. Since the lowest speed
2767 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2768 * from experimentation it is safe to say you will always have a failure.
2769 *-----------------------------------------------------------------*/
2770 mfsdram(SDRAM_MCOPT1, ecc_temp);
2771 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2772 mfsdram(SDRAM_MCOPT1, val);
2773 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2774 SDRAM_MCOPT1_MCHK_NON);
2776 window_found = FALSE;
2777 begin_found[0] = FALSE;
2778 end_found[0] = FALSE;
2779 search_end[0] = FALSE;
2780 begin_found[1] = FALSE;
2781 end_found[1] = FALSE;
2782 search_end[1] = FALSE;
2784 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2785 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2788 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2790 /* Bank is enabled */
2792 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2794 /*------------------------------------------------------------------
2795 * Run the short memory test.
2796 *-----------------------------------------------------------------*/
2797 for (i = 0; i < NUMMEMTESTS; i++) {
2798 for (j = 0; j < NUMMEMWORDS; j++) {
2799 membase[j] = test[i][j];
2800 ppcDcbf((u32)&(membase[j]));
2803 for (j = 0; j < NUMMEMWORDS; j++) {
2804 if (membase[j] != test[i][j]) {
2805 ppcDcbf((u32)&(membase[j]));
2808 ppcDcbf((u32)&(membase[j]));
2811 if (j < NUMMEMWORDS)
2815 /*------------------------------------------------------------------
2816 * See if the rffd value passed.
2817 *-----------------------------------------------------------------*/
2818 if (i < NUMMEMTESTS) {
2819 if ((end_found[dimm_num] == FALSE) &&
2820 (search_end[dimm_num] == TRUE)) {
2821 end_found[dimm_num] = TRUE;
2823 if ((end_found[0] == TRUE) &&
2824 (end_found[1] == TRUE))
2827 if (begin_found[dimm_num] == FALSE) {
2828 begin_found[dimm_num] = TRUE;
2829 search_end[dimm_num] = TRUE;
2833 begin_found[dimm_num] = TRUE;
2834 end_found[dimm_num] = TRUE;
2838 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2839 window_found = TRUE;
2841 /*------------------------------------------------------------------
2842 * Make sure we found the valid read passing window. Halt if not
2843 *-----------------------------------------------------------------*/
2844 if (window_found == FALSE) {
2845 printf("ERROR: Cannot determine a common read delay for the "
2846 "DIMM(s) installed.\n");
2850 /*------------------------------------------------------------------
2851 * Restore the ECC variable to what it originally was
2852 *-----------------------------------------------------------------*/
2853 mtsdram(SDRAM_MCOPT1,
2854 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2860 static void ppc440sp_sdram_register_dump(void)
2862 unsigned int sdram_reg;
2863 unsigned int sdram_data;
2864 unsigned int dcr_data;
2866 printf("\n Register Dump:\n");
2867 sdram_reg = SDRAM_MCSTAT;
2868 mfsdram(sdram_reg, sdram_data);
2869 printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
2870 sdram_reg = SDRAM_MCOPT1;
2871 mfsdram(sdram_reg, sdram_data);
2872 printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
2873 sdram_reg = SDRAM_MCOPT2;
2874 mfsdram(sdram_reg, sdram_data);
2875 printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
2876 sdram_reg = SDRAM_MODT0;
2877 mfsdram(sdram_reg, sdram_data);
2878 printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
2879 sdram_reg = SDRAM_MODT1;
2880 mfsdram(sdram_reg, sdram_data);
2881 printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
2882 sdram_reg = SDRAM_MODT2;
2883 mfsdram(sdram_reg, sdram_data);
2884 printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
2885 sdram_reg = SDRAM_MODT3;
2886 mfsdram(sdram_reg, sdram_data);
2887 printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
2888 sdram_reg = SDRAM_CODT;
2889 mfsdram(sdram_reg, sdram_data);
2890 printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
2891 sdram_reg = SDRAM_VVPR;
2892 mfsdram(sdram_reg, sdram_data);
2893 printf(" SDRAM_VVPR = 0x%08X", sdram_data);
2894 sdram_reg = SDRAM_OPARS;
2895 mfsdram(sdram_reg, sdram_data);
2896 printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
2898 * OPAR2 is only used as a trigger register.
2899 * No data is contained in this register, and reading or writing
2900 * to is can cause bad things to happen (hangs). Just skip it
2902 * sdram_reg = SDRAM_OPAR2;
2903 * mfsdram(sdram_reg, sdram_data);
2904 * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
2906 printf(" SDRAM_OPART = N/A ");
2907 sdram_reg = SDRAM_RTR;
2908 mfsdram(sdram_reg, sdram_data);
2909 printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
2910 sdram_reg = SDRAM_MB0CF;
2911 mfsdram(sdram_reg, sdram_data);
2912 printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
2913 sdram_reg = SDRAM_MB1CF;
2914 mfsdram(sdram_reg, sdram_data);
2915 printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
2916 sdram_reg = SDRAM_MB2CF;
2917 mfsdram(sdram_reg, sdram_data);
2918 printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
2919 sdram_reg = SDRAM_MB3CF;
2920 mfsdram(sdram_reg, sdram_data);
2921 printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
2922 sdram_reg = SDRAM_INITPLR0;
2923 mfsdram(sdram_reg, sdram_data);
2924 printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
2925 sdram_reg = SDRAM_INITPLR1;
2926 mfsdram(sdram_reg, sdram_data);
2927 printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
2928 sdram_reg = SDRAM_INITPLR2;
2929 mfsdram(sdram_reg, sdram_data);
2930 printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
2931 sdram_reg = SDRAM_INITPLR3;
2932 mfsdram(sdram_reg, sdram_data);
2933 printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
2934 sdram_reg = SDRAM_INITPLR4;
2935 mfsdram(sdram_reg, sdram_data);
2936 printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
2937 sdram_reg = SDRAM_INITPLR5;
2938 mfsdram(sdram_reg, sdram_data);
2939 printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
2940 sdram_reg = SDRAM_INITPLR6;
2941 mfsdram(sdram_reg, sdram_data);
2942 printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
2943 sdram_reg = SDRAM_INITPLR7;
2944 mfsdram(sdram_reg, sdram_data);
2945 printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
2946 sdram_reg = SDRAM_INITPLR8;
2947 mfsdram(sdram_reg, sdram_data);
2948 printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
2949 sdram_reg = SDRAM_INITPLR9;
2950 mfsdram(sdram_reg, sdram_data);
2951 printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
2952 sdram_reg = SDRAM_INITPLR10;
2953 mfsdram(sdram_reg, sdram_data);
2954 printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
2955 sdram_reg = SDRAM_INITPLR11;
2956 mfsdram(sdram_reg, sdram_data);
2957 printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2958 sdram_reg = SDRAM_INITPLR12;
2959 mfsdram(sdram_reg, sdram_data);
2960 printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
2961 sdram_reg = SDRAM_INITPLR13;
2962 mfsdram(sdram_reg, sdram_data);
2963 printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2964 sdram_reg = SDRAM_INITPLR14;
2965 mfsdram(sdram_reg, sdram_data);
2966 printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
2967 sdram_reg = SDRAM_INITPLR15;
2968 mfsdram(sdram_reg, sdram_data);
2969 printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2970 sdram_reg = SDRAM_RQDC;
2971 mfsdram(sdram_reg, sdram_data);
2972 printf(" SDRAM_RQDC = 0x%08X", sdram_data);
2973 sdram_reg = SDRAM_RFDC;
2974 mfsdram(sdram_reg, sdram_data);
2975 printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
2976 sdram_reg = SDRAM_RDCC;
2977 mfsdram(sdram_reg, sdram_data);
2978 printf(" SDRAM_RDCC = 0x%08X", sdram_data);
2979 sdram_reg = SDRAM_DLCR;
2980 mfsdram(sdram_reg, sdram_data);
2981 printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
2982 sdram_reg = SDRAM_CLKTR;
2983 mfsdram(sdram_reg, sdram_data);
2984 printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
2985 sdram_reg = SDRAM_WRDTR;
2986 mfsdram(sdram_reg, sdram_data);
2987 printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
2988 sdram_reg = SDRAM_SDTR1;
2989 mfsdram(sdram_reg, sdram_data);
2990 printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
2991 sdram_reg = SDRAM_SDTR2;
2992 mfsdram(sdram_reg, sdram_data);
2993 printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
2994 sdram_reg = SDRAM_SDTR3;
2995 mfsdram(sdram_reg, sdram_data);
2996 printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
2997 sdram_reg = SDRAM_MMODE;
2998 mfsdram(sdram_reg, sdram_data);
2999 printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
3000 sdram_reg = SDRAM_MEMODE;
3001 mfsdram(sdram_reg, sdram_data);
3002 printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
3003 sdram_reg = SDRAM_ECCCR;
3004 mfsdram(sdram_reg, sdram_data);
3005 printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
3007 dcr_data = mfdcr(SDRAM_R0BAS);
3008 printf(" MQ0_B0BAS = 0x%08X", dcr_data);
3009 dcr_data = mfdcr(SDRAM_R1BAS);
3010 printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
3011 dcr_data = mfdcr(SDRAM_R2BAS);
3012 printf(" MQ2_B0BAS = 0x%08X", dcr_data);
3013 dcr_data = mfdcr(SDRAM_R3BAS);
3014 printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
3017 #endif /* CONFIG_SPD_EEPROM */