2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* define DEBUG for debugging output (obviously ;-)) */
47 #include <asm/processor.h>
49 #include <asm/cache.h>
53 #if defined(CONFIG_SPD_EEPROM) && \
54 (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
55 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
56 defined(CONFIG_460SX))
58 /*-----------------------------------------------------------------------------+
60 *-----------------------------------------------------------------------------*/
75 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
77 #define ONE_BILLION 1000000000
79 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
81 #define CMD_NOP (7 << 19)
82 #define CMD_PRECHARGE (2 << 19)
83 #define CMD_REFRESH (1 << 19)
84 #define CMD_EMR (0 << 19)
85 #define CMD_READ (5 << 19)
86 #define CMD_WRITE (4 << 19)
88 #define SELECT_MR (0 << 16)
89 #define SELECT_EMR (1 << 16)
90 #define SELECT_EMR2 (2 << 16)
91 #define SELECT_EMR3 (3 << 16)
94 #define DLL_RESET 0x00000100
96 #define WRITE_RECOV_2 (1 << 9)
97 #define WRITE_RECOV_3 (2 << 9)
98 #define WRITE_RECOV_4 (3 << 9)
99 #define WRITE_RECOV_5 (4 << 9)
100 #define WRITE_RECOV_6 (5 << 9)
102 #define BURST_LEN_4 0x00000002
105 #define ODT_0_OHM 0x00000000
106 #define ODT_50_OHM 0x00000044
107 #define ODT_75_OHM 0x00000004
108 #define ODT_150_OHM 0x00000040
110 #define ODS_FULL 0x00000000
111 #define ODS_REDUCED 0x00000002
113 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
114 #define ODT_EB0R (0x80000000 >> 8)
115 #define ODT_EB0W (0x80000000 >> 7)
116 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
117 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
118 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
120 /* Defines for the Read Cycle Delay test */
121 #define NUMMEMTESTS 8
122 #define NUMMEMWORDS 8
123 #define NUMLOOPS 64 /* memory test loops */
126 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
127 * region. Right now the cache should still be disabled in U-Boot because of the
128 * EMAC driver, that need it's buffer descriptor to be located in non cached
131 * If at some time this restriction doesn't apply anymore, just define
132 * CONFIG_4xx_DCACHE in the board config file and this code should setup
133 * everything correctly.
135 #ifdef CONFIG_4xx_DCACHE
136 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
138 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
142 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
143 * To support such configurations, we "only" map the first 2GB via the TLB's. We
144 * need some free virtual address space for the remaining peripherals like, SoC
145 * devices, FLASH etc.
147 * Note that ECC is currently not supported on configurations with more than 2GB
148 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
149 * the ECC parity byte of the remaining area can't be written.
151 #ifndef CONFIG_MAX_MEM_MAPPED
152 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
156 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
158 void __spd_ddr_init_hang (void)
162 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
165 * To provide an interface for board specific config values in this common
166 * DDR setup code, we implement he "weak" default functions here. They return
167 * the default value back to the caller.
169 * Please see include/configs/yucca.h for an example fora board specific
172 u32 __ddr_wrdtr(u32 default_val)
176 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
178 u32 __ddr_clktr(u32 default_val)
182 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
185 /* Private Structure Definitions */
187 /* enum only to ease code for cas latency setting */
188 typedef enum ddr_cas_id {
196 /*-----------------------------------------------------------------------------+
198 *-----------------------------------------------------------------------------*/
199 static phys_size_t sdram_memsize(void);
200 static void get_spd_info(unsigned long *dimm_populated,
201 unsigned char *iic0_dimm_addr,
202 unsigned long num_dimm_banks);
203 static void check_mem_type(unsigned long *dimm_populated,
204 unsigned char *iic0_dimm_addr,
205 unsigned long num_dimm_banks);
206 static void check_frequency(unsigned long *dimm_populated,
207 unsigned char *iic0_dimm_addr,
208 unsigned long num_dimm_banks);
209 static void check_rank_number(unsigned long *dimm_populated,
210 unsigned char *iic0_dimm_addr,
211 unsigned long num_dimm_banks);
212 static void check_voltage_type(unsigned long *dimm_populated,
213 unsigned char *iic0_dimm_addr,
214 unsigned long num_dimm_banks);
215 static void program_memory_queue(unsigned long *dimm_populated,
216 unsigned char *iic0_dimm_addr,
217 unsigned long num_dimm_banks);
218 static void program_codt(unsigned long *dimm_populated,
219 unsigned char *iic0_dimm_addr,
220 unsigned long num_dimm_banks);
221 static void program_mode(unsigned long *dimm_populated,
222 unsigned char *iic0_dimm_addr,
223 unsigned long num_dimm_banks,
224 ddr_cas_id_t *selected_cas,
225 int *write_recovery);
226 static void program_tr(unsigned long *dimm_populated,
227 unsigned char *iic0_dimm_addr,
228 unsigned long num_dimm_banks);
229 static void program_rtr(unsigned long *dimm_populated,
230 unsigned char *iic0_dimm_addr,
231 unsigned long num_dimm_banks);
232 static void program_bxcf(unsigned long *dimm_populated,
233 unsigned char *iic0_dimm_addr,
234 unsigned long num_dimm_banks);
235 static void program_copt1(unsigned long *dimm_populated,
236 unsigned char *iic0_dimm_addr,
237 unsigned long num_dimm_banks);
238 static void program_initplr(unsigned long *dimm_populated,
239 unsigned char *iic0_dimm_addr,
240 unsigned long num_dimm_banks,
241 ddr_cas_id_t selected_cas,
243 static unsigned long is_ecc_enabled(void);
244 #ifdef CONFIG_DDR_ECC
245 static void program_ecc(unsigned long *dimm_populated,
246 unsigned char *iic0_dimm_addr,
247 unsigned long num_dimm_banks,
248 unsigned long tlb_word2_i_value);
249 static void program_ecc_addr(unsigned long start_address,
250 unsigned long num_bytes,
251 unsigned long tlb_word2_i_value);
253 static void program_DQS_calibration(unsigned long *dimm_populated,
254 unsigned char *iic0_dimm_addr,
255 unsigned long num_dimm_banks);
256 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
257 static void test(void);
259 static void DQS_calibration_process(void);
261 static void ppc440sp_sdram_register_dump(void);
262 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
263 void dcbz_area(u32 start_address, u32 num_bytes);
265 static u32 mfdcr_any(u32 dcr)
270 case SDRAM_R0BAS + 0:
271 val = mfdcr(SDRAM_R0BAS + 0);
273 case SDRAM_R0BAS + 1:
274 val = mfdcr(SDRAM_R0BAS + 1);
276 case SDRAM_R0BAS + 2:
277 val = mfdcr(SDRAM_R0BAS + 2);
279 case SDRAM_R0BAS + 3:
280 val = mfdcr(SDRAM_R0BAS + 3);
283 printf("DCR %d not defined in case statement!!!\n", dcr);
284 val = 0; /* just to satisfy the compiler */
290 static void mtdcr_any(u32 dcr, u32 val)
293 case SDRAM_R0BAS + 0:
294 mtdcr(SDRAM_R0BAS + 0, val);
296 case SDRAM_R0BAS + 1:
297 mtdcr(SDRAM_R0BAS + 1, val);
299 case SDRAM_R0BAS + 2:
300 mtdcr(SDRAM_R0BAS + 2, val);
302 case SDRAM_R0BAS + 3:
303 mtdcr(SDRAM_R0BAS + 3, val);
306 printf("DCR %d not defined in case statement!!!\n", dcr);
310 static unsigned char spd_read(uchar chip, uint addr)
312 unsigned char data[2];
314 if (i2c_probe(chip) == 0)
315 if (i2c_read(chip, addr, 1, data, 1) == 0)
321 /*-----------------------------------------------------------------------------+
323 *-----------------------------------------------------------------------------*/
324 static phys_size_t sdram_memsize(void)
326 phys_size_t mem_size;
327 unsigned long mcopt2;
328 unsigned long mcstat;
335 mfsdram(SDRAM_MCOPT2, mcopt2);
336 mfsdram(SDRAM_MCSTAT, mcstat);
338 /* DDR controller must be enabled and not in self-refresh. */
339 /* Otherwise memsize is zero. */
340 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
341 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
342 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
343 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
344 for (i = 0; i < MAXBXCF; i++) {
345 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
347 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
348 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
351 case SDRAM_RXBAS_SDSZ_8:
354 case SDRAM_RXBAS_SDSZ_16:
357 case SDRAM_RXBAS_SDSZ_32:
360 case SDRAM_RXBAS_SDSZ_64:
363 case SDRAM_RXBAS_SDSZ_128:
366 case SDRAM_RXBAS_SDSZ_256:
369 case SDRAM_RXBAS_SDSZ_512:
372 case SDRAM_RXBAS_SDSZ_1024:
375 case SDRAM_RXBAS_SDSZ_2048:
378 case SDRAM_RXBAS_SDSZ_4096:
382 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
391 return mem_size << 20;
394 /*-----------------------------------------------------------------------------+
395 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
396 * Note: This routine runs from flash with a stack set up in the chip's
397 * sram space. It is important that the routine does not require .sbss, .bss or
398 * .data sections. It also cannot call routines that require these sections.
399 *-----------------------------------------------------------------------------*/
400 /*-----------------------------------------------------------------------------
402 * Description: Configures SDRAM memory banks for DDR operation.
403 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
404 * via the IIC bus and then configures the DDR SDRAM memory
405 * banks appropriately. If Auto Memory Configuration is
406 * not used, it is assumed that no DIMM is plugged
407 *-----------------------------------------------------------------------------*/
408 phys_size_t initdram(int board_type)
410 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
411 unsigned char spd0[MAX_SPD_BYTES];
412 unsigned char spd1[MAX_SPD_BYTES];
413 unsigned char *dimm_spd[MAXDIMMS];
414 unsigned long dimm_populated[MAXDIMMS];
415 unsigned long num_dimm_banks; /* on board dimm banks */
417 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
419 phys_size_t dram_size = 0;
421 num_dimm_banks = sizeof(iic0_dimm_addr);
423 /*------------------------------------------------------------------
424 * Set up an array of SPD matrixes.
425 *-----------------------------------------------------------------*/
429 /*------------------------------------------------------------------
430 * Reset the DDR-SDRAM controller.
431 *-----------------------------------------------------------------*/
432 mtsdr(SDR0_SRST, (0x80000000 >> 10));
433 mtsdr(SDR0_SRST, 0x00000000);
436 * Make sure I2C controller is initialized
440 /* switch to correct I2C bus */
441 I2C_SET_BUS(CFG_SPD_BUS_NUM);
442 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
444 /*------------------------------------------------------------------
445 * Clear out the serial presence detect buffers.
446 * Perform IIC reads from the dimm. Fill in the spds.
447 * Check to see if the dimm slots are populated
448 *-----------------------------------------------------------------*/
449 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
451 /*------------------------------------------------------------------
452 * Check the memory type for the dimms plugged.
453 *-----------------------------------------------------------------*/
454 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
456 /*------------------------------------------------------------------
457 * Check the frequency supported for the dimms plugged.
458 *-----------------------------------------------------------------*/
459 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
461 /*------------------------------------------------------------------
462 * Check the total rank number.
463 *-----------------------------------------------------------------*/
464 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
466 /*------------------------------------------------------------------
467 * Check the voltage type for the dimms plugged.
468 *-----------------------------------------------------------------*/
469 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
471 /*------------------------------------------------------------------
472 * Program SDRAM controller options 2 register
473 * Except Enabling of the memory controller.
474 *-----------------------------------------------------------------*/
475 mfsdram(SDRAM_MCOPT2, val);
476 mtsdram(SDRAM_MCOPT2,
478 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
479 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
480 SDRAM_MCOPT2_ISIE_MASK))
481 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
482 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
483 SDRAM_MCOPT2_ISIE_ENABLE));
485 /*------------------------------------------------------------------
486 * Program SDRAM controller options 1 register
487 * Note: Does not enable the memory controller.
488 *-----------------------------------------------------------------*/
489 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
491 /*------------------------------------------------------------------
492 * Set the SDRAM Controller On Die Termination Register
493 *-----------------------------------------------------------------*/
494 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
496 /*------------------------------------------------------------------
497 * Program SDRAM refresh register.
498 *-----------------------------------------------------------------*/
499 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
501 /*------------------------------------------------------------------
502 * Program SDRAM mode register.
503 *-----------------------------------------------------------------*/
504 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
505 &selected_cas, &write_recovery);
507 /*------------------------------------------------------------------
508 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
509 *-----------------------------------------------------------------*/
510 mfsdram(SDRAM_WRDTR, val);
511 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
512 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
514 /*------------------------------------------------------------------
515 * Set the SDRAM Clock Timing Register
516 *-----------------------------------------------------------------*/
517 mfsdram(SDRAM_CLKTR, val);
518 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
519 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
521 /*------------------------------------------------------------------
522 * Program the BxCF registers.
523 *-----------------------------------------------------------------*/
524 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
526 /*------------------------------------------------------------------
527 * Program SDRAM timing registers.
528 *-----------------------------------------------------------------*/
529 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
531 /*------------------------------------------------------------------
532 * Set the Extended Mode register
533 *-----------------------------------------------------------------*/
534 mfsdram(SDRAM_MEMODE, val);
535 mtsdram(SDRAM_MEMODE,
536 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
537 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
538 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
539 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
541 /*------------------------------------------------------------------
542 * Program Initialization preload registers.
543 *-----------------------------------------------------------------*/
544 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
545 selected_cas, write_recovery);
547 /*------------------------------------------------------------------
548 * Delay to ensure 200usec have elapsed since reset.
549 *-----------------------------------------------------------------*/
552 /*------------------------------------------------------------------
553 * Set the memory queue core base addr.
554 *-----------------------------------------------------------------*/
555 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
557 /*------------------------------------------------------------------
558 * Program SDRAM controller options 2 register
559 * Enable the memory controller.
560 *-----------------------------------------------------------------*/
561 mfsdram(SDRAM_MCOPT2, val);
562 mtsdram(SDRAM_MCOPT2,
563 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
564 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
565 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
567 /*------------------------------------------------------------------
568 * Wait for SDRAM_CFG0_DC_EN to complete.
569 *-----------------------------------------------------------------*/
571 mfsdram(SDRAM_MCSTAT, val);
572 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
574 /* get installed memory size */
575 dram_size = sdram_memsize();
580 if (dram_size > CONFIG_MAX_MEM_MAPPED)
581 dram_size = CONFIG_MAX_MEM_MAPPED;
583 /* and program tlb entries for this size (dynamic) */
586 * Program TLB entries with caches enabled, for best performace
587 * while auto-calibrating and ECC generation
589 program_tlb(0, 0, dram_size, 0);
591 /*------------------------------------------------------------------
593 *-----------------------------------------------------------------*/
594 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
596 #ifdef CONFIG_DDR_ECC
597 /*------------------------------------------------------------------
598 * If ecc is enabled, initialize the parity bits.
599 *-----------------------------------------------------------------*/
600 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
604 * Now after initialization (auto-calibration and ECC generation)
605 * remove the TLB entries with caches enabled and program again with
606 * desired cache functionality
608 remove_tlb(0, dram_size);
609 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
611 ppc440sp_sdram_register_dump();
614 * Clear potential errors resulting from auto-calibration.
615 * If not done, then we could get an interrupt later on when
616 * exceptions are enabled.
618 set_mcsr(get_mcsr());
620 return sdram_memsize();
623 static void get_spd_info(unsigned long *dimm_populated,
624 unsigned char *iic0_dimm_addr,
625 unsigned long num_dimm_banks)
627 unsigned long dimm_num;
628 unsigned long dimm_found;
629 unsigned char num_of_bytes;
630 unsigned char total_size;
633 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
637 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
638 debug("\nspd_read(0x%x) returned %d\n",
639 iic0_dimm_addr[dimm_num], num_of_bytes);
640 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
641 debug("spd_read(0x%x) returned %d\n",
642 iic0_dimm_addr[dimm_num], total_size);
644 if ((num_of_bytes != 0) && (total_size != 0)) {
645 dimm_populated[dimm_num] = TRUE;
647 debug("DIMM slot %lu: populated\n", dimm_num);
649 dimm_populated[dimm_num] = FALSE;
650 debug("DIMM slot %lu: Not populated\n", dimm_num);
654 if (dimm_found == FALSE) {
655 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
656 spd_ddr_init_hang ();
660 void board_add_ram_info(int use_default)
662 PPC4xx_SYS_INFO board_cfg;
665 if (is_ecc_enabled())
670 get_sys_info(&board_cfg);
672 mfsdr(SDR0_DDR0, val);
673 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
674 printf(" enabled, %d MHz", (val * 2) / 1000000);
676 mfsdram(SDRAM_MMODE, val);
677 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
678 printf(", CL%d)", val);
681 /*------------------------------------------------------------------
682 * For the memory DIMMs installed, this routine verifies that they
683 * really are DDR specific DIMMs.
684 *-----------------------------------------------------------------*/
685 static void check_mem_type(unsigned long *dimm_populated,
686 unsigned char *iic0_dimm_addr,
687 unsigned long num_dimm_banks)
689 unsigned long dimm_num;
690 unsigned long dimm_type;
692 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
693 if (dimm_populated[dimm_num] == TRUE) {
694 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
697 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
698 "slot %d.\n", (unsigned int)dimm_num);
699 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
700 printf("Replace the DIMM module with a supported DIMM.\n\n");
701 spd_ddr_init_hang ();
704 printf("ERROR: EDO DIMM detected in slot %d.\n",
705 (unsigned int)dimm_num);
706 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
707 printf("Replace the DIMM module with a supported DIMM.\n\n");
708 spd_ddr_init_hang ();
711 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
712 (unsigned int)dimm_num);
713 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
714 printf("Replace the DIMM module with a supported DIMM.\n\n");
715 spd_ddr_init_hang ();
718 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
719 (unsigned int)dimm_num);
720 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
721 printf("Replace the DIMM module with a supported DIMM.\n\n");
722 spd_ddr_init_hang ();
725 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
726 (unsigned int)dimm_num);
727 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
728 printf("Replace the DIMM module with a supported DIMM.\n\n");
729 spd_ddr_init_hang ();
732 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
733 (unsigned int)dimm_num);
734 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
735 printf("Replace the DIMM module with a supported DIMM.\n\n");
736 spd_ddr_init_hang ();
739 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
740 dimm_populated[dimm_num] = SDRAM_DDR1;
743 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
744 dimm_populated[dimm_num] = SDRAM_DDR2;
747 printf("ERROR: Unknown DIMM detected in slot %d.\n",
748 (unsigned int)dimm_num);
749 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
750 printf("Replace the DIMM module with a supported DIMM.\n\n");
751 spd_ddr_init_hang ();
756 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
757 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
758 && (dimm_populated[dimm_num] != SDRAM_NONE)
759 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
760 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
761 spd_ddr_init_hang ();
766 /*------------------------------------------------------------------
767 * For the memory DIMMs installed, this routine verifies that
768 * frequency previously calculated is supported.
769 *-----------------------------------------------------------------*/
770 static void check_frequency(unsigned long *dimm_populated,
771 unsigned char *iic0_dimm_addr,
772 unsigned long num_dimm_banks)
774 unsigned long dimm_num;
775 unsigned long tcyc_reg;
776 unsigned long cycle_time;
777 unsigned long calc_cycle_time;
778 unsigned long sdram_freq;
779 unsigned long sdr_ddrpll;
780 PPC4xx_SYS_INFO board_cfg;
782 /*------------------------------------------------------------------
783 * Get the board configuration info.
784 *-----------------------------------------------------------------*/
785 get_sys_info(&board_cfg);
787 mfsdr(SDR0_DDR0, sdr_ddrpll);
788 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
791 * calc_cycle_time is calculated from DDR frequency set by board/chip
792 * and is expressed in multiple of 10 picoseconds
793 * to match the way DIMM cycle time is calculated below.
795 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
797 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
798 if (dimm_populated[dimm_num] != SDRAM_NONE) {
799 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
801 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
802 * the higher order nibble (bits 4-7) designates the cycle time
803 * to a granularity of 1ns;
804 * the value presented by the lower order nibble (bits 0-3)
805 * has a granularity of .1ns and is added to the value designated
806 * by the higher nibble. In addition, four lines of the lower order
807 * nibble are assigned to support +.25,+.33, +.66 and +.75.
809 /* Convert from hex to decimal */
810 if ((tcyc_reg & 0x0F) == 0x0D)
811 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
812 else if ((tcyc_reg & 0x0F) == 0x0C)
813 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
814 else if ((tcyc_reg & 0x0F) == 0x0B)
815 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
816 else if ((tcyc_reg & 0x0F) == 0x0A)
817 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
819 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
820 ((tcyc_reg & 0x0F)*10);
821 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
823 if (cycle_time > (calc_cycle_time + 10)) {
825 * the provided sdram cycle_time is too small
826 * for the available DIMM cycle_time.
827 * The additionnal 100ps is here to accept a small incertainty.
829 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
830 "slot %d \n while calculated cycle time is %d ps.\n",
831 (unsigned int)(cycle_time*10),
832 (unsigned int)dimm_num,
833 (unsigned int)(calc_cycle_time*10));
834 printf("Replace the DIMM, or change DDR frequency via "
835 "strapping bits.\n\n");
836 spd_ddr_init_hang ();
842 /*------------------------------------------------------------------
843 * For the memory DIMMs installed, this routine verifies two
844 * ranks/banks maximum are availables.
845 *-----------------------------------------------------------------*/
846 static void check_rank_number(unsigned long *dimm_populated,
847 unsigned char *iic0_dimm_addr,
848 unsigned long num_dimm_banks)
850 unsigned long dimm_num;
851 unsigned long dimm_rank;
852 unsigned long total_rank = 0;
854 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
855 if (dimm_populated[dimm_num] != SDRAM_NONE) {
856 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
857 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
858 dimm_rank = (dimm_rank & 0x0F) +1;
860 dimm_rank = dimm_rank & 0x0F;
863 if (dimm_rank > MAXRANKS) {
864 printf("ERROR: DRAM DIMM detected with %lu ranks in "
865 "slot %lu is not supported.\n", dimm_rank, dimm_num);
866 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
867 printf("Replace the DIMM module with a supported DIMM.\n\n");
868 spd_ddr_init_hang ();
870 total_rank += dimm_rank;
872 if (total_rank > MAXRANKS) {
873 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
874 "for all slots.\n", (unsigned int)total_rank);
875 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
876 printf("Remove one of the DIMM modules.\n\n");
877 spd_ddr_init_hang ();
882 /*------------------------------------------------------------------
883 * only support 2.5V modules.
884 * This routine verifies this.
885 *-----------------------------------------------------------------*/
886 static void check_voltage_type(unsigned long *dimm_populated,
887 unsigned char *iic0_dimm_addr,
888 unsigned long num_dimm_banks)
890 unsigned long dimm_num;
891 unsigned long voltage_type;
893 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
894 if (dimm_populated[dimm_num] != SDRAM_NONE) {
895 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
896 switch (voltage_type) {
898 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
899 printf("This DIMM is 5.0 Volt/TTL.\n");
900 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
901 (unsigned int)dimm_num);
902 spd_ddr_init_hang ();
905 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
906 printf("This DIMM is LVTTL.\n");
907 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
908 (unsigned int)dimm_num);
909 spd_ddr_init_hang ();
912 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
913 printf("This DIMM is 1.5 Volt.\n");
914 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
915 (unsigned int)dimm_num);
916 spd_ddr_init_hang ();
919 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
920 printf("This DIMM is 3.3 Volt/TTL.\n");
921 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
922 (unsigned int)dimm_num);
923 spd_ddr_init_hang ();
926 /* 2.5 Voltage only for DDR1 */
929 /* 1.8 Voltage only for DDR2 */
932 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
933 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
934 (unsigned int)dimm_num);
935 spd_ddr_init_hang ();
942 /*-----------------------------------------------------------------------------+
944 *-----------------------------------------------------------------------------*/
945 static void program_copt1(unsigned long *dimm_populated,
946 unsigned char *iic0_dimm_addr,
947 unsigned long num_dimm_banks)
949 unsigned long dimm_num;
950 unsigned long mcopt1;
951 unsigned long ecc_enabled;
952 unsigned long ecc = 0;
953 unsigned long data_width = 0;
954 unsigned long dimm_32bit;
955 unsigned long dimm_64bit;
956 unsigned long registered = 0;
957 unsigned long attribute = 0;
958 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
959 unsigned long bankcount;
960 unsigned long ddrtype;
963 #ifdef CONFIG_DDR_ECC
973 /*------------------------------------------------------------------
974 * Set memory controller options reg 1, SDRAM_MCOPT1.
975 *-----------------------------------------------------------------*/
976 mfsdram(SDRAM_MCOPT1, val);
977 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
978 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
979 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
980 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
981 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
982 SDRAM_MCOPT1_DREF_MASK);
984 mcopt1 |= SDRAM_MCOPT1_QDEP;
985 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
986 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
987 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
988 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
989 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
991 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
992 if (dimm_populated[dimm_num] != SDRAM_NONE) {
993 /* test ecc support */
994 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
995 if (ecc != 0x02) /* ecc not supported */
998 /* test bank count */
999 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1000 if (bankcount == 0x04) /* bank count = 4 */
1001 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1002 else /* bank count = 8 */
1003 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1006 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1007 /* test for buffered/unbuffered, registered, differential clocks */
1008 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1009 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1011 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1012 if (dimm_num == 0) {
1013 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1014 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1015 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1016 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1017 if (registered == 1) { /* DDR2 always buffered */
1018 /* TODO: what about above comments ? */
1019 mcopt1 |= SDRAM_MCOPT1_RDEN;
1022 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1023 if ((attribute & 0x02) == 0x00) {
1024 /* buffered not supported */
1027 mcopt1 |= SDRAM_MCOPT1_RDEN;
1032 else if (dimm_num == 1) {
1033 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1034 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1035 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1036 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1037 if (registered == 1) {
1038 /* DDR2 always buffered */
1039 mcopt1 |= SDRAM_MCOPT1_RDEN;
1042 if ((attribute & 0x02) == 0x00) {
1043 /* buffered not supported */
1046 mcopt1 |= SDRAM_MCOPT1_RDEN;
1052 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1053 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1054 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1056 switch (data_width) {
1066 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1068 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1074 /* verify matching properties */
1075 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1077 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1078 spd_ddr_init_hang ();
1082 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1083 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1084 spd_ddr_init_hang ();
1086 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1087 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1088 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1089 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1091 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1092 spd_ddr_init_hang ();
1095 if (ecc_enabled == TRUE)
1096 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1098 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1100 mtsdram(SDRAM_MCOPT1, mcopt1);
1103 /*-----------------------------------------------------------------------------+
1105 *-----------------------------------------------------------------------------*/
1106 static void program_codt(unsigned long *dimm_populated,
1107 unsigned char *iic0_dimm_addr,
1108 unsigned long num_dimm_banks)
1111 unsigned long modt0 = 0;
1112 unsigned long modt1 = 0;
1113 unsigned long modt2 = 0;
1114 unsigned long modt3 = 0;
1115 unsigned char dimm_num;
1116 unsigned char dimm_rank;
1117 unsigned char total_rank = 0;
1118 unsigned char total_dimm = 0;
1119 unsigned char dimm_type = 0;
1120 unsigned char firstSlot = 0;
1122 /*------------------------------------------------------------------
1123 * Set the SDRAM Controller On Die Termination Register
1124 *-----------------------------------------------------------------*/
1125 mfsdram(SDRAM_CODT, codt);
1126 codt |= (SDRAM_CODT_IO_NMODE
1127 & (~SDRAM_CODT_DQS_SINGLE_END
1128 & ~SDRAM_CODT_CKSE_SINGLE_END
1129 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1130 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1132 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1133 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1134 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1135 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1136 dimm_rank = (dimm_rank & 0x0F) + 1;
1137 dimm_type = SDRAM_DDR2;
1139 dimm_rank = dimm_rank & 0x0F;
1140 dimm_type = SDRAM_DDR1;
1143 total_rank += dimm_rank;
1145 if ((dimm_num == 0) && (total_dimm == 1))
1151 if (dimm_type == SDRAM_DDR2) {
1152 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1153 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1154 if (total_rank == 1) {
1155 codt |= CALC_ODT_R(0);
1156 modt0 = CALC_ODT_W(0);
1161 if (total_rank == 2) {
1162 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1163 modt0 = CALC_ODT_W(0);
1164 modt1 = CALC_ODT_W(0);
1168 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1169 if (total_rank == 1) {
1170 codt |= CALC_ODT_R(2);
1173 modt2 = CALC_ODT_W(2);
1176 if (total_rank == 2) {
1177 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1180 modt2 = CALC_ODT_W(2);
1181 modt3 = CALC_ODT_W(2);
1184 if (total_dimm == 2) {
1185 if (total_rank == 2) {
1186 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1187 modt0 = CALC_ODT_RW(2);
1189 modt2 = CALC_ODT_RW(0);
1192 if (total_rank == 4) {
1193 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1194 CALC_ODT_R(2) | CALC_ODT_R(3);
1195 modt0 = CALC_ODT_RW(2);
1197 modt2 = CALC_ODT_RW(0);
1202 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1208 if (total_dimm == 1) {
1209 if (total_rank == 1)
1211 if (total_rank == 2)
1214 if (total_dimm == 2) {
1215 if (total_rank == 2)
1217 if (total_rank == 4)
1222 debug("nb of dimm %d\n", total_dimm);
1223 debug("nb of rank %d\n", total_rank);
1224 if (total_dimm == 1)
1225 debug("dimm in slot %d\n", firstSlot);
1227 mtsdram(SDRAM_CODT, codt);
1228 mtsdram(SDRAM_MODT0, modt0);
1229 mtsdram(SDRAM_MODT1, modt1);
1230 mtsdram(SDRAM_MODT2, modt2);
1231 mtsdram(SDRAM_MODT3, modt3);
1234 /*-----------------------------------------------------------------------------+
1236 *-----------------------------------------------------------------------------*/
1237 static void program_initplr(unsigned long *dimm_populated,
1238 unsigned char *iic0_dimm_addr,
1239 unsigned long num_dimm_banks,
1240 ddr_cas_id_t selected_cas,
1254 /******************************************************
1255 ** Assumption: if more than one DIMM, all DIMMs are the same
1256 ** as already checked in check_memory_type
1257 ******************************************************/
1259 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1260 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1261 mtsdram(SDRAM_INITPLR1, 0x81900400);
1262 mtsdram(SDRAM_INITPLR2, 0x81810000);
1263 mtsdram(SDRAM_INITPLR3, 0xff800162);
1264 mtsdram(SDRAM_INITPLR4, 0x81900400);
1265 mtsdram(SDRAM_INITPLR5, 0x86080000);
1266 mtsdram(SDRAM_INITPLR6, 0x86080000);
1267 mtsdram(SDRAM_INITPLR7, 0x81000062);
1268 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1269 switch (selected_cas) {
1280 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1281 spd_ddr_init_hang ();
1287 * ToDo - Still a problem with the write recovery:
1288 * On the Corsair CM2X512-5400C4 module, setting write recovery
1289 * in the INITPLR reg to the value calculated in program_mode()
1290 * results in not correctly working DDR2 memory (crash after
1293 * So for now, set the write recovery to 3. This seems to work
1294 * on the Corair module too.
1298 switch (write_recovery) {
1312 printf("ERROR: write recovery not support (%d)", write_recovery);
1313 spd_ddr_init_hang ();
1317 wr = WRITE_RECOV_3; /* test-only, see description above */
1320 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1321 if (dimm_populated[dimm_num] != SDRAM_NONE)
1323 if (total_dimm == 1) {
1326 } else if (total_dimm == 2) {
1330 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1331 spd_ddr_init_hang ();
1334 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1335 emr = CMD_EMR | SELECT_EMR | odt | ods;
1336 emr2 = CMD_EMR | SELECT_EMR2;
1337 emr3 = CMD_EMR | SELECT_EMR3;
1338 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1340 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1341 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1342 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1343 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1344 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1346 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1347 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1348 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1349 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1350 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1351 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1352 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1353 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1355 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1356 spd_ddr_init_hang ();
1360 /*------------------------------------------------------------------
1361 * This routine programs the SDRAM_MMODE register.
1362 * the selected_cas is an output parameter, that will be passed
1363 * by caller to call the above program_initplr( )
1364 *-----------------------------------------------------------------*/
1365 static void program_mode(unsigned long *dimm_populated,
1366 unsigned char *iic0_dimm_addr,
1367 unsigned long num_dimm_banks,
1368 ddr_cas_id_t *selected_cas,
1369 int *write_recovery)
1371 unsigned long dimm_num;
1372 unsigned long sdram_ddr1;
1373 unsigned long t_wr_ns;
1374 unsigned long t_wr_clk;
1375 unsigned long cas_bit;
1376 unsigned long cas_index;
1377 unsigned long sdram_freq;
1378 unsigned long ddr_check;
1379 unsigned long mmode;
1380 unsigned long tcyc_reg;
1381 unsigned long cycle_2_0_clk;
1382 unsigned long cycle_2_5_clk;
1383 unsigned long cycle_3_0_clk;
1384 unsigned long cycle_4_0_clk;
1385 unsigned long cycle_5_0_clk;
1386 unsigned long max_2_0_tcyc_ns_x_100;
1387 unsigned long max_2_5_tcyc_ns_x_100;
1388 unsigned long max_3_0_tcyc_ns_x_100;
1389 unsigned long max_4_0_tcyc_ns_x_100;
1390 unsigned long max_5_0_tcyc_ns_x_100;
1391 unsigned long cycle_time_ns_x_100[3];
1392 PPC4xx_SYS_INFO board_cfg;
1393 unsigned char cas_2_0_available;
1394 unsigned char cas_2_5_available;
1395 unsigned char cas_3_0_available;
1396 unsigned char cas_4_0_available;
1397 unsigned char cas_5_0_available;
1398 unsigned long sdr_ddrpll;
1400 /*------------------------------------------------------------------
1401 * Get the board configuration info.
1402 *-----------------------------------------------------------------*/
1403 get_sys_info(&board_cfg);
1405 mfsdr(SDR0_DDR0, sdr_ddrpll);
1406 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1407 debug("sdram_freq=%d\n", sdram_freq);
1409 /*------------------------------------------------------------------
1410 * Handle the timing. We need to find the worst case timing of all
1411 * the dimm modules installed.
1412 *-----------------------------------------------------------------*/
1414 cas_2_0_available = TRUE;
1415 cas_2_5_available = TRUE;
1416 cas_3_0_available = TRUE;
1417 cas_4_0_available = TRUE;
1418 cas_5_0_available = TRUE;
1419 max_2_0_tcyc_ns_x_100 = 10;
1420 max_2_5_tcyc_ns_x_100 = 10;
1421 max_3_0_tcyc_ns_x_100 = 10;
1422 max_4_0_tcyc_ns_x_100 = 10;
1423 max_5_0_tcyc_ns_x_100 = 10;
1426 /* loop through all the DIMM slots on the board */
1427 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1428 /* If a dimm is installed in a particular slot ... */
1429 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1430 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1435 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1436 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1437 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1439 /* For a particular DIMM, grab the three CAS values it supports */
1440 for (cas_index = 0; cas_index < 3; cas_index++) {
1441 switch (cas_index) {
1443 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1446 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1449 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1453 if ((tcyc_reg & 0x0F) >= 10) {
1454 if ((tcyc_reg & 0x0F) == 0x0D) {
1455 /* Convert from hex to decimal */
1456 cycle_time_ns_x_100[cas_index] =
1457 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1459 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1460 "in slot %d\n", (unsigned int)dimm_num);
1461 spd_ddr_init_hang ();
1464 /* Convert from hex to decimal */
1465 cycle_time_ns_x_100[cas_index] =
1466 (((tcyc_reg & 0xF0) >> 4) * 100) +
1467 ((tcyc_reg & 0x0F)*10);
1469 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1470 cycle_time_ns_x_100[cas_index]);
1473 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1474 /* supported for a particular DIMM. */
1479 * DDR devices use the following bitmask for CAS latency:
1480 * Bit 7 6 5 4 3 2 1 0
1481 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1483 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1484 (cycle_time_ns_x_100[cas_index] != 0)) {
1485 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1486 cycle_time_ns_x_100[cas_index]);
1491 cas_4_0_available = FALSE;
1494 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1495 (cycle_time_ns_x_100[cas_index] != 0)) {
1496 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1497 cycle_time_ns_x_100[cas_index]);
1502 cas_3_0_available = FALSE;
1505 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1506 (cycle_time_ns_x_100[cas_index] != 0)) {
1507 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1508 cycle_time_ns_x_100[cas_index]);
1513 cas_2_5_available = FALSE;
1516 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1517 (cycle_time_ns_x_100[cas_index] != 0)) {
1518 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1519 cycle_time_ns_x_100[cas_index]);
1524 cas_2_0_available = FALSE;
1528 * DDR2 devices use the following bitmask for CAS latency:
1529 * Bit 7 6 5 4 3 2 1 0
1530 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1532 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1533 (cycle_time_ns_x_100[cas_index] != 0)) {
1534 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1535 cycle_time_ns_x_100[cas_index]);
1540 cas_5_0_available = FALSE;
1543 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1544 (cycle_time_ns_x_100[cas_index] != 0)) {
1545 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1546 cycle_time_ns_x_100[cas_index]);
1551 cas_4_0_available = FALSE;
1554 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1555 (cycle_time_ns_x_100[cas_index] != 0)) {
1556 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1557 cycle_time_ns_x_100[cas_index]);
1562 cas_3_0_available = FALSE;
1568 /*------------------------------------------------------------------
1569 * Set the SDRAM mode, SDRAM_MMODE
1570 *-----------------------------------------------------------------*/
1571 mfsdram(SDRAM_MMODE, mmode);
1572 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1574 /* add 10 here because of rounding problems */
1575 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1576 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1577 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1578 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1579 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1580 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1581 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1582 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1584 if (sdram_ddr1 == TRUE) { /* DDR1 */
1585 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1586 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1587 *selected_cas = DDR_CAS_2;
1588 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1589 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1590 *selected_cas = DDR_CAS_2_5;
1591 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1592 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1593 *selected_cas = DDR_CAS_3;
1595 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1596 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1597 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1598 spd_ddr_init_hang ();
1601 debug("cas_3_0_available=%d\n", cas_3_0_available);
1602 debug("cas_4_0_available=%d\n", cas_4_0_available);
1603 debug("cas_5_0_available=%d\n", cas_5_0_available);
1604 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1605 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1606 *selected_cas = DDR_CAS_3;
1607 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1608 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1609 *selected_cas = DDR_CAS_4;
1610 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1611 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1612 *selected_cas = DDR_CAS_5;
1614 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1615 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1616 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1617 printf("cas3=%d cas4=%d cas5=%d\n",
1618 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1619 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1620 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1621 spd_ddr_init_hang ();
1625 if (sdram_ddr1 == TRUE)
1626 mmode |= SDRAM_MMODE_WR_DDR1;
1629 /* loop through all the DIMM slots on the board */
1630 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1631 /* If a dimm is installed in a particular slot ... */
1632 if (dimm_populated[dimm_num] != SDRAM_NONE)
1633 t_wr_ns = max(t_wr_ns,
1634 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1638 * convert from nanoseconds to ddr clocks
1639 * round up if necessary
1641 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1642 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1643 if (sdram_freq != ddr_check)
1651 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1654 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1657 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1660 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1663 *write_recovery = t_wr_clk;
1666 debug("CAS latency = %d\n", *selected_cas);
1667 debug("Write recovery = %d\n", *write_recovery);
1669 mtsdram(SDRAM_MMODE, mmode);
1672 /*-----------------------------------------------------------------------------+
1674 *-----------------------------------------------------------------------------*/
1675 static void program_rtr(unsigned long *dimm_populated,
1676 unsigned char *iic0_dimm_addr,
1677 unsigned long num_dimm_banks)
1679 PPC4xx_SYS_INFO board_cfg;
1680 unsigned long max_refresh_rate;
1681 unsigned long dimm_num;
1682 unsigned long refresh_rate_type;
1683 unsigned long refresh_rate;
1685 unsigned long sdram_freq;
1686 unsigned long sdr_ddrpll;
1689 /*------------------------------------------------------------------
1690 * Get the board configuration info.
1691 *-----------------------------------------------------------------*/
1692 get_sys_info(&board_cfg);
1694 /*------------------------------------------------------------------
1695 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1696 *-----------------------------------------------------------------*/
1697 mfsdr(SDR0_DDR0, sdr_ddrpll);
1698 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1700 max_refresh_rate = 0;
1701 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1702 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1704 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1705 refresh_rate_type &= 0x7F;
1706 switch (refresh_rate_type) {
1708 refresh_rate = 15625;
1711 refresh_rate = 3906;
1714 refresh_rate = 7812;
1717 refresh_rate = 31250;
1720 refresh_rate = 62500;
1723 refresh_rate = 125000;
1727 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1728 (unsigned int)dimm_num);
1729 printf("Replace the DIMM module with a supported DIMM.\n\n");
1730 spd_ddr_init_hang ();
1734 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1738 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1739 mfsdram(SDRAM_RTR, val);
1740 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1741 (SDRAM_RTR_RINT_ENCODE(rint)));
1744 /*------------------------------------------------------------------
1745 * This routine programs the SDRAM_TRx registers.
1746 *-----------------------------------------------------------------*/
1747 static void program_tr(unsigned long *dimm_populated,
1748 unsigned char *iic0_dimm_addr,
1749 unsigned long num_dimm_banks)
1751 unsigned long dimm_num;
1752 unsigned long sdram_ddr1;
1753 unsigned long t_rp_ns;
1754 unsigned long t_rcd_ns;
1755 unsigned long t_rrd_ns;
1756 unsigned long t_ras_ns;
1757 unsigned long t_rc_ns;
1758 unsigned long t_rfc_ns;
1759 unsigned long t_wpc_ns;
1760 unsigned long t_wtr_ns;
1761 unsigned long t_rpc_ns;
1762 unsigned long t_rp_clk;
1763 unsigned long t_rcd_clk;
1764 unsigned long t_rrd_clk;
1765 unsigned long t_ras_clk;
1766 unsigned long t_rc_clk;
1767 unsigned long t_rfc_clk;
1768 unsigned long t_wpc_clk;
1769 unsigned long t_wtr_clk;
1770 unsigned long t_rpc_clk;
1771 unsigned long sdtr1, sdtr2, sdtr3;
1772 unsigned long ddr_check;
1773 unsigned long sdram_freq;
1774 unsigned long sdr_ddrpll;
1776 PPC4xx_SYS_INFO board_cfg;
1778 /*------------------------------------------------------------------
1779 * Get the board configuration info.
1780 *-----------------------------------------------------------------*/
1781 get_sys_info(&board_cfg);
1783 mfsdr(SDR0_DDR0, sdr_ddrpll);
1784 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1786 /*------------------------------------------------------------------
1787 * Handle the timing. We need to find the worst case timing of all
1788 * the dimm modules installed.
1789 *-----------------------------------------------------------------*/
1801 /* loop through all the DIMM slots on the board */
1802 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1803 /* If a dimm is installed in a particular slot ... */
1804 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1805 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1810 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1811 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1812 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1813 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1814 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1815 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1819 /*------------------------------------------------------------------
1820 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1821 *-----------------------------------------------------------------*/
1822 mfsdram(SDRAM_SDTR1, sdtr1);
1823 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1824 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1826 /* default values */
1827 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1828 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1830 /* normal operations */
1831 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1832 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1834 mtsdram(SDRAM_SDTR1, sdtr1);
1836 /*------------------------------------------------------------------
1837 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1838 *-----------------------------------------------------------------*/
1839 mfsdram(SDRAM_SDTR2, sdtr2);
1840 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1841 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1842 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1843 SDRAM_SDTR2_RRD_MASK);
1846 * convert t_rcd from nanoseconds to ddr clocks
1847 * round up if necessary
1849 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1850 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1851 if (sdram_freq != ddr_check)
1854 switch (t_rcd_clk) {
1857 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1860 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1863 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1866 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1869 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1873 if (sdram_ddr1 == TRUE) { /* DDR1 */
1874 if (sdram_freq < 200000000) {
1875 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1876 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1877 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1879 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1880 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1881 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1884 /* loop through all the DIMM slots on the board */
1885 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1886 /* If a dimm is installed in a particular slot ... */
1887 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1888 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1889 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1890 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1895 * convert from nanoseconds to ddr clocks
1896 * round up if necessary
1898 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1899 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1900 if (sdram_freq != ddr_check)
1903 switch (t_wpc_clk) {
1907 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1910 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1913 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1916 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1919 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1924 * convert from nanoseconds to ddr clocks
1925 * round up if necessary
1927 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1928 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1929 if (sdram_freq != ddr_check)
1932 switch (t_wtr_clk) {
1935 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1938 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1941 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1944 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1949 * convert from nanoseconds to ddr clocks
1950 * round up if necessary
1952 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1953 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1954 if (sdram_freq != ddr_check)
1957 switch (t_rpc_clk) {
1961 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1964 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1967 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1973 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1976 * convert t_rrd from nanoseconds to ddr clocks
1977 * round up if necessary
1979 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1980 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1981 if (sdram_freq != ddr_check)
1985 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1987 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1990 * convert t_rp from nanoseconds to ddr clocks
1991 * round up if necessary
1993 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1994 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1995 if (sdram_freq != ddr_check)
2003 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2006 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2009 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2012 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2015 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2019 mtsdram(SDRAM_SDTR2, sdtr2);
2021 /*------------------------------------------------------------------
2022 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2023 *-----------------------------------------------------------------*/
2024 mfsdram(SDRAM_SDTR3, sdtr3);
2025 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2026 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2029 * convert t_ras from nanoseconds to ddr clocks
2030 * round up if necessary
2032 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2033 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2034 if (sdram_freq != ddr_check)
2037 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2040 * convert t_rc from nanoseconds to ddr clocks
2041 * round up if necessary
2043 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2044 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2045 if (sdram_freq != ddr_check)
2048 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2050 /* default xcs value */
2051 sdtr3 |= SDRAM_SDTR3_XCS;
2054 * convert t_rfc from nanoseconds to ddr clocks
2055 * round up if necessary
2057 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2058 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2059 if (sdram_freq != ddr_check)
2062 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2064 mtsdram(SDRAM_SDTR3, sdtr3);
2067 /*-----------------------------------------------------------------------------+
2069 *-----------------------------------------------------------------------------*/
2070 static void program_bxcf(unsigned long *dimm_populated,
2071 unsigned char *iic0_dimm_addr,
2072 unsigned long num_dimm_banks)
2074 unsigned long dimm_num;
2075 unsigned long num_col_addr;
2076 unsigned long num_ranks;
2077 unsigned long num_banks;
2079 unsigned long ind_rank;
2081 unsigned long ind_bank;
2082 unsigned long bank_0_populated;
2084 /*------------------------------------------------------------------
2085 * Set the BxCF regs. First, wipe out the bank config registers.
2086 *-----------------------------------------------------------------*/
2087 mtsdram(SDRAM_MB0CF, 0x00000000);
2088 mtsdram(SDRAM_MB1CF, 0x00000000);
2089 mtsdram(SDRAM_MB2CF, 0x00000000);
2090 mtsdram(SDRAM_MB3CF, 0x00000000);
2092 mode = SDRAM_BXCF_M_BE_ENABLE;
2094 bank_0_populated = 0;
2096 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2097 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2098 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2099 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2100 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2101 num_ranks = (num_ranks & 0x0F) +1;
2103 num_ranks = num_ranks & 0x0F;
2105 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2107 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2112 switch (num_col_addr) {
2114 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2117 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2120 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2123 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2126 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2129 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2130 (unsigned int)dimm_num);
2131 printf("ERROR: Unsupported value for number of "
2132 "column addresses: %d.\n", (unsigned int)num_col_addr);
2133 printf("Replace the DIMM module with a supported DIMM.\n\n");
2134 spd_ddr_init_hang ();
2138 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2139 bank_0_populated = 1;
2141 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2142 mtsdram(SDRAM_MB0CF +
2143 ((dimm_num + bank_0_populated + ind_rank) << 2),
2150 /*------------------------------------------------------------------
2151 * program memory queue.
2152 *-----------------------------------------------------------------*/
2153 static void program_memory_queue(unsigned long *dimm_populated,
2154 unsigned char *iic0_dimm_addr,
2155 unsigned long num_dimm_banks)
2157 unsigned long dimm_num;
2158 phys_size_t rank_base_addr;
2159 unsigned long rank_reg;
2160 phys_size_t rank_size_bytes;
2161 unsigned long rank_size_id;
2162 unsigned long num_ranks;
2163 unsigned long baseadd_size;
2165 unsigned long bank_0_populated = 0;
2166 phys_size_t total_size = 0;
2168 /*------------------------------------------------------------------
2169 * Reset the rank_base_address.
2170 *-----------------------------------------------------------------*/
2171 rank_reg = SDRAM_R0BAS;
2173 rank_base_addr = 0x00000000;
2175 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2176 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2177 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2178 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2179 num_ranks = (num_ranks & 0x0F) + 1;
2181 num_ranks = num_ranks & 0x0F;
2183 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2185 /*------------------------------------------------------------------
2187 *-----------------------------------------------------------------*/
2189 switch (rank_size_id) {
2191 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2195 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2199 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2203 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2207 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2211 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2215 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2219 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2223 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2224 (unsigned int)dimm_num);
2225 printf("ERROR: Unsupported value for the banksize: %d.\n",
2226 (unsigned int)rank_size_id);
2227 printf("Replace the DIMM module with a supported DIMM.\n\n");
2228 spd_ddr_init_hang ();
2230 rank_size_bytes = total_size << 20;
2232 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2233 bank_0_populated = 1;
2235 for (i = 0; i < num_ranks; i++) {
2236 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2237 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2239 rank_base_addr += rank_size_bytes;
2244 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2246 * Enable high bandwidth access on 460EX/GT.
2247 * This should/could probably be done on other
2248 * PPC's too, like 440SPe.
2249 * This is currently not used, but with this setup
2250 * it is possible to use it later on in e.g. the Linux
2251 * EMAC driver for performance gain.
2253 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2254 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2258 /*-----------------------------------------------------------------------------+
2260 *-----------------------------------------------------------------------------*/
2261 static unsigned long is_ecc_enabled(void)
2263 unsigned long dimm_num;
2268 /* loop through all the DIMM slots on the board */
2269 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2270 mfsdram(SDRAM_MCOPT1, val);
2271 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2277 static void blank_string(int size)
2281 for (i=0; i<size; i++)
2283 for (i=0; i<size; i++)
2285 for (i=0; i<size; i++)
2289 #ifdef CONFIG_DDR_ECC
2290 /*-----------------------------------------------------------------------------+
2292 *-----------------------------------------------------------------------------*/
2293 static void program_ecc(unsigned long *dimm_populated,
2294 unsigned char *iic0_dimm_addr,
2295 unsigned long num_dimm_banks,
2296 unsigned long tlb_word2_i_value)
2298 unsigned long mcopt1;
2299 unsigned long mcopt2;
2300 unsigned long mcstat;
2301 unsigned long dimm_num;
2305 /* loop through all the DIMM slots on the board */
2306 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2307 /* If a dimm is installed in a particular slot ... */
2308 if (dimm_populated[dimm_num] != SDRAM_NONE)
2309 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2314 if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2315 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2319 mfsdram(SDRAM_MCOPT1, mcopt1);
2320 mfsdram(SDRAM_MCOPT2, mcopt2);
2322 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2323 /* DDR controller must be enabled and not in self-refresh. */
2324 mfsdram(SDRAM_MCSTAT, mcstat);
2325 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2326 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2327 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2328 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2330 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2337 static void wait_ddr_idle(void)
2342 mfsdram(SDRAM_MCSTAT, val);
2343 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2346 /*-----------------------------------------------------------------------------+
2348 *-----------------------------------------------------------------------------*/
2349 static void program_ecc_addr(unsigned long start_address,
2350 unsigned long num_bytes,
2351 unsigned long tlb_word2_i_value)
2353 unsigned long current_address;
2354 unsigned long end_address;
2355 unsigned long address_increment;
2356 unsigned long mcopt1;
2357 char str[] = "ECC generation -";
2358 char slash[] = "\\|/-\\|/-";
2362 current_address = start_address;
2363 mfsdram(SDRAM_MCOPT1, mcopt1);
2364 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2365 mtsdram(SDRAM_MCOPT1,
2366 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2372 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2373 /* ECC bit set method for non-cached memory */
2374 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2375 address_increment = 4;
2377 address_increment = 8;
2378 end_address = current_address + num_bytes;
2380 while (current_address < end_address) {
2381 *((unsigned long *)current_address) = 0x00000000;
2382 current_address += address_increment;
2384 if ((loop++ % (2 << 20)) == 0) {
2386 putc(slash[loopi++ % 8]);
2391 /* ECC bit set method for cached memory */
2392 dcbz_area(start_address, num_bytes);
2393 /* Write modified dcache lines back to memory */
2394 clean_dcache_range(start_address, start_address + num_bytes);
2397 blank_string(strlen(str));
2403 /* clear ECC error repoting registers */
2404 mtsdram(SDRAM_ECCCR, 0xffffffff);
2405 mtdcr(0x4c, 0xffffffff);
2407 mtsdram(SDRAM_MCOPT1,
2408 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2416 /*-----------------------------------------------------------------------------+
2417 * program_DQS_calibration.
2418 *-----------------------------------------------------------------------------*/
2419 static void program_DQS_calibration(unsigned long *dimm_populated,
2420 unsigned char *iic0_dimm_addr,
2421 unsigned long num_dimm_banks)
2425 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2426 mtsdram(SDRAM_RQDC, 0x80000037);
2427 mtsdram(SDRAM_RDCC, 0x40000000);
2428 mtsdram(SDRAM_RFDC, 0x000001DF);
2432 /*------------------------------------------------------------------
2433 * Program RDCC register
2434 * Read sample cycle auto-update enable
2435 *-----------------------------------------------------------------*/
2437 mfsdram(SDRAM_RDCC, val);
2439 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2440 | SDRAM_RDCC_RSAE_ENABLE);
2442 /*------------------------------------------------------------------
2443 * Program RQDC register
2444 * Internal DQS delay mechanism enable
2445 *-----------------------------------------------------------------*/
2446 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2448 /*------------------------------------------------------------------
2449 * Program RFDC register
2450 * Set Feedback Fractional Oversample
2451 * Auto-detect read sample cycle enable
2452 *-----------------------------------------------------------------*/
2453 mfsdram(SDRAM_RFDC, val);
2455 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2456 SDRAM_RFDC_RFFD_MASK))
2457 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2458 SDRAM_RFDC_RFFD_ENCODE(0)));
2460 DQS_calibration_process();
2464 static int short_mem_test(void)
2471 phys_size_t base_addr;
2472 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2473 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2474 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2475 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2476 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2477 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2478 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2479 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2480 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2481 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2482 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2483 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2484 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2485 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2486 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2487 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2488 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2491 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2492 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2495 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2496 /* Bank is enabled */
2499 * Only run test on accessable memory (below 2GB)
2501 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2502 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2505 /*------------------------------------------------------------------
2506 * Run the short memory test.
2507 *-----------------------------------------------------------------*/
2508 membase = (u32 *)(u32)base_addr;
2510 for (i = 0; i < NUMMEMTESTS; i++) {
2511 for (j = 0; j < NUMMEMWORDS; j++) {
2512 membase[j] = test[i][j];
2513 ppcDcbf((u32)&(membase[j]));
2516 for (l=0; l<NUMLOOPS; l++) {
2517 for (j = 0; j < NUMMEMWORDS; j++) {
2518 if (membase[j] != test[i][j]) {
2519 ppcDcbf((u32)&(membase[j]));
2522 ppcDcbf((u32)&(membase[j]));
2527 } /* if bank enabled */
2528 } /* for bxcf_num */
2533 #ifndef HARD_CODED_DQS
2534 /*-----------------------------------------------------------------------------+
2535 * DQS_calibration_process.
2536 *-----------------------------------------------------------------------------*/
2537 static void DQS_calibration_process(void)
2539 unsigned long rfdc_reg;
2545 unsigned long begin_rqfd[MAXRANKS];
2546 unsigned long begin_rffd[MAXRANKS];
2547 unsigned long end_rqfd[MAXRANKS];
2548 unsigned long end_rffd[MAXRANKS];
2550 unsigned long dlycal;
2551 unsigned long dly_val;
2552 unsigned long max_pass_length;
2553 unsigned long current_pass_length;
2554 unsigned long current_fail_length;
2555 unsigned long current_start;
2557 unsigned char fail_found;
2558 unsigned char pass_found;
2559 #if !defined(CONFIG_DDR_RQDC_FIXED)
2565 char str[] = "Auto calibration -";
2566 char slash[] = "\\|/-\\|/-";
2568 /*------------------------------------------------------------------
2569 * Test to determine the best read clock delay tuning bits.
2571 * Before the DDR controller can be used, the read clock delay needs to be
2572 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2573 * This value cannot be hardcoded into the program because it changes
2574 * depending on the board's setup and environment.
2575 * To do this, all delay values are tested to see if they
2576 * work or not. By doing this, you get groups of fails with groups of
2577 * passing values. The idea is to find the start and end of a passing
2578 * window and take the center of it to use as the read clock delay.
2580 * A failure has to be seen first so that when we hit a pass, we know
2581 * that it is truely the start of the window. If we get passing values
2582 * to start off with, we don't know if we are at the start of the window.
2584 * The code assumes that a failure will always be found.
2585 * If a failure is not found, there is no easy way to get the middle
2586 * of the passing window. I guess we can pretty much pick any value
2587 * but some values will be better than others. Since the lowest speed
2588 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2589 * from experimentation it is safe to say you will always have a failure.
2590 *-----------------------------------------------------------------*/
2592 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2593 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2598 mfsdram(SDRAM_RQDC, rqdc_reg);
2599 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2600 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2601 #else /* CONFIG_DDR_RQDC_FIXED */
2603 * On Katmai the complete auto-calibration somehow doesn't seem to
2604 * produce the best results, meaning optimal values for RQFD/RFFD.
2605 * This was discovered by GDA using a high bandwidth scope,
2606 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2607 * so now on Katmai "only" RFFD is auto-calibrated.
2609 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2610 #endif /* CONFIG_DDR_RQDC_FIXED */
2622 window_found = FALSE;
2624 max_pass_length = 0;
2627 current_pass_length = 0;
2628 current_fail_length = 0;
2630 window_found = FALSE;
2635 * get the delay line calibration register value
2637 mfsdram(SDRAM_DLCR, dlycal);
2638 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2640 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2641 mfsdram(SDRAM_RFDC, rfdc_reg);
2642 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2644 /*------------------------------------------------------------------
2645 * Set the timing reg for the test.
2646 *-----------------------------------------------------------------*/
2647 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2649 /*------------------------------------------------------------------
2650 * See if the rffd value passed.
2651 *-----------------------------------------------------------------*/
2652 if (short_mem_test()) {
2653 if (fail_found == TRUE) {
2655 if (current_pass_length == 0)
2656 current_start = rffd;
2658 current_fail_length = 0;
2659 current_pass_length++;
2661 if (current_pass_length > max_pass_length) {
2662 max_pass_length = current_pass_length;
2663 max_start = current_start;
2668 current_pass_length = 0;
2669 current_fail_length++;
2671 if (current_fail_length >= (dly_val >> 2)) {
2672 if (fail_found == FALSE) {
2674 } else if (pass_found == TRUE) {
2675 window_found = TRUE;
2682 /*------------------------------------------------------------------
2683 * Set the average RFFD value
2684 *-----------------------------------------------------------------*/
2685 rffd_average = ((max_start + max_end) >> 1);
2687 if (rffd_average < 0)
2690 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2691 rffd_average = SDRAM_RFDC_RFFD_MAX;
2692 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2693 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2695 #if !defined(CONFIG_DDR_RQDC_FIXED)
2696 max_pass_length = 0;
2699 current_pass_length = 0;
2700 current_fail_length = 0;
2702 window_found = FALSE;
2706 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2707 mfsdram(SDRAM_RQDC, rqdc_reg);
2708 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2710 /*------------------------------------------------------------------
2711 * Set the timing reg for the test.
2712 *-----------------------------------------------------------------*/
2713 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2715 /*------------------------------------------------------------------
2716 * See if the rffd value passed.
2717 *-----------------------------------------------------------------*/
2718 if (short_mem_test()) {
2719 if (fail_found == TRUE) {
2721 if (current_pass_length == 0)
2722 current_start = rqfd;
2724 current_fail_length = 0;
2725 current_pass_length++;
2727 if (current_pass_length > max_pass_length) {
2728 max_pass_length = current_pass_length;
2729 max_start = current_start;
2734 current_pass_length = 0;
2735 current_fail_length++;
2737 if (fail_found == FALSE) {
2739 } else if (pass_found == TRUE) {
2740 window_found = TRUE;
2746 rqfd_average = ((max_start + max_end) >> 1);
2748 /*------------------------------------------------------------------
2749 * Make sure we found the valid read passing window. Halt if not
2750 *-----------------------------------------------------------------*/
2751 if (window_found == FALSE) {
2752 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2754 putc(slash[loopi++ % 8]);
2756 /* try again from with a different RQFD start value */
2758 goto calibration_loop;
2761 printf("\nERROR: Cannot determine a common read delay for the "
2762 "DIMM(s) installed.\n");
2763 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2764 ppc440sp_sdram_register_dump();
2765 spd_ddr_init_hang ();
2768 if (rqfd_average < 0)
2771 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2772 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2775 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2776 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2778 blank_string(strlen(str));
2779 #endif /* CONFIG_DDR_RQDC_FIXED */
2782 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2783 * PowerPC440SP/SPe DDR2 application note:
2784 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2786 mfsdram(SDRAM_RTSR, val);
2787 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2788 mfsdram(SDRAM_RDCC, val);
2789 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2791 mtsdram(SDRAM_RDCC, val);
2795 mfsdram(SDRAM_DLCR, val);
2796 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2797 mfsdram(SDRAM_RQDC, val);
2798 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2799 mfsdram(SDRAM_RFDC, val);
2800 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2801 mfsdram(SDRAM_RDCC, val);
2802 debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2804 #else /* calibration test with hardvalues */
2805 /*-----------------------------------------------------------------------------+
2806 * DQS_calibration_process.
2807 *-----------------------------------------------------------------------------*/
2808 static void test(void)
2810 unsigned long dimm_num;
2811 unsigned long ecc_temp;
2813 unsigned long *membase;
2814 unsigned long bxcf[MAXRANKS];
2817 char begin_found[MAXDIMMS];
2818 char end_found[MAXDIMMS];
2819 char search_end[MAXDIMMS];
2820 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2821 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2822 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2823 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2824 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2825 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2826 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2827 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2828 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2829 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2830 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2831 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2832 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2833 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2834 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2835 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2836 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2838 /*------------------------------------------------------------------
2839 * Test to determine the best read clock delay tuning bits.
2841 * Before the DDR controller can be used, the read clock delay needs to be
2842 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2843 * This value cannot be hardcoded into the program because it changes
2844 * depending on the board's setup and environment.
2845 * To do this, all delay values are tested to see if they
2846 * work or not. By doing this, you get groups of fails with groups of
2847 * passing values. The idea is to find the start and end of a passing
2848 * window and take the center of it to use as the read clock delay.
2850 * A failure has to be seen first so that when we hit a pass, we know
2851 * that it is truely the start of the window. If we get passing values
2852 * to start off with, we don't know if we are at the start of the window.
2854 * The code assumes that a failure will always be found.
2855 * If a failure is not found, there is no easy way to get the middle
2856 * of the passing window. I guess we can pretty much pick any value
2857 * but some values will be better than others. Since the lowest speed
2858 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2859 * from experimentation it is safe to say you will always have a failure.
2860 *-----------------------------------------------------------------*/
2861 mfsdram(SDRAM_MCOPT1, ecc_temp);
2862 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2863 mfsdram(SDRAM_MCOPT1, val);
2864 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2865 SDRAM_MCOPT1_MCHK_NON);
2867 window_found = FALSE;
2868 begin_found[0] = FALSE;
2869 end_found[0] = FALSE;
2870 search_end[0] = FALSE;
2871 begin_found[1] = FALSE;
2872 end_found[1] = FALSE;
2873 search_end[1] = FALSE;
2875 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2876 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2879 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2881 /* Bank is enabled */
2883 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2885 /*------------------------------------------------------------------
2886 * Run the short memory test.
2887 *-----------------------------------------------------------------*/
2888 for (i = 0; i < NUMMEMTESTS; i++) {
2889 for (j = 0; j < NUMMEMWORDS; j++) {
2890 membase[j] = test[i][j];
2891 ppcDcbf((u32)&(membase[j]));
2894 for (j = 0; j < NUMMEMWORDS; j++) {
2895 if (membase[j] != test[i][j]) {
2896 ppcDcbf((u32)&(membase[j]));
2899 ppcDcbf((u32)&(membase[j]));
2902 if (j < NUMMEMWORDS)
2906 /*------------------------------------------------------------------
2907 * See if the rffd value passed.
2908 *-----------------------------------------------------------------*/
2909 if (i < NUMMEMTESTS) {
2910 if ((end_found[dimm_num] == FALSE) &&
2911 (search_end[dimm_num] == TRUE)) {
2912 end_found[dimm_num] = TRUE;
2914 if ((end_found[0] == TRUE) &&
2915 (end_found[1] == TRUE))
2918 if (begin_found[dimm_num] == FALSE) {
2919 begin_found[dimm_num] = TRUE;
2920 search_end[dimm_num] = TRUE;
2924 begin_found[dimm_num] = TRUE;
2925 end_found[dimm_num] = TRUE;
2929 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2930 window_found = TRUE;
2932 /*------------------------------------------------------------------
2933 * Make sure we found the valid read passing window. Halt if not
2934 *-----------------------------------------------------------------*/
2935 if (window_found == FALSE) {
2936 printf("ERROR: Cannot determine a common read delay for the "
2937 "DIMM(s) installed.\n");
2938 spd_ddr_init_hang ();
2941 /*------------------------------------------------------------------
2942 * Restore the ECC variable to what it originally was
2943 *-----------------------------------------------------------------*/
2944 mtsdram(SDRAM_MCOPT1,
2945 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2951 static void ppc440sp_sdram_register_dump(void)
2953 unsigned int sdram_reg;
2954 unsigned int sdram_data;
2955 unsigned int dcr_data;
2957 printf("\n Register Dump:\n");
2958 sdram_reg = SDRAM_MCSTAT;
2959 mfsdram(sdram_reg, sdram_data);
2960 printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
2961 sdram_reg = SDRAM_MCOPT1;
2962 mfsdram(sdram_reg, sdram_data);
2963 printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
2964 sdram_reg = SDRAM_MCOPT2;
2965 mfsdram(sdram_reg, sdram_data);
2966 printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
2967 sdram_reg = SDRAM_MODT0;
2968 mfsdram(sdram_reg, sdram_data);
2969 printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
2970 sdram_reg = SDRAM_MODT1;
2971 mfsdram(sdram_reg, sdram_data);
2972 printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
2973 sdram_reg = SDRAM_MODT2;
2974 mfsdram(sdram_reg, sdram_data);
2975 printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
2976 sdram_reg = SDRAM_MODT3;
2977 mfsdram(sdram_reg, sdram_data);
2978 printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
2979 sdram_reg = SDRAM_CODT;
2980 mfsdram(sdram_reg, sdram_data);
2981 printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
2982 sdram_reg = SDRAM_VVPR;
2983 mfsdram(sdram_reg, sdram_data);
2984 printf(" SDRAM_VVPR = 0x%08X", sdram_data);
2985 sdram_reg = SDRAM_OPARS;
2986 mfsdram(sdram_reg, sdram_data);
2987 printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
2989 * OPAR2 is only used as a trigger register.
2990 * No data is contained in this register, and reading or writing
2991 * to is can cause bad things to happen (hangs). Just skip it
2993 * sdram_reg = SDRAM_OPAR2;
2994 * mfsdram(sdram_reg, sdram_data);
2995 * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
2997 printf(" SDRAM_OPART = N/A ");
2998 sdram_reg = SDRAM_RTR;
2999 mfsdram(sdram_reg, sdram_data);
3000 printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
3001 sdram_reg = SDRAM_MB0CF;
3002 mfsdram(sdram_reg, sdram_data);
3003 printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
3004 sdram_reg = SDRAM_MB1CF;
3005 mfsdram(sdram_reg, sdram_data);
3006 printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
3007 sdram_reg = SDRAM_MB2CF;
3008 mfsdram(sdram_reg, sdram_data);
3009 printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
3010 sdram_reg = SDRAM_MB3CF;
3011 mfsdram(sdram_reg, sdram_data);
3012 printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
3013 sdram_reg = SDRAM_INITPLR0;
3014 mfsdram(sdram_reg, sdram_data);
3015 printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
3016 sdram_reg = SDRAM_INITPLR1;
3017 mfsdram(sdram_reg, sdram_data);
3018 printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
3019 sdram_reg = SDRAM_INITPLR2;
3020 mfsdram(sdram_reg, sdram_data);
3021 printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
3022 sdram_reg = SDRAM_INITPLR3;
3023 mfsdram(sdram_reg, sdram_data);
3024 printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
3025 sdram_reg = SDRAM_INITPLR4;
3026 mfsdram(sdram_reg, sdram_data);
3027 printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
3028 sdram_reg = SDRAM_INITPLR5;
3029 mfsdram(sdram_reg, sdram_data);
3030 printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
3031 sdram_reg = SDRAM_INITPLR6;
3032 mfsdram(sdram_reg, sdram_data);
3033 printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
3034 sdram_reg = SDRAM_INITPLR7;
3035 mfsdram(sdram_reg, sdram_data);
3036 printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
3037 sdram_reg = SDRAM_INITPLR8;
3038 mfsdram(sdram_reg, sdram_data);
3039 printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
3040 sdram_reg = SDRAM_INITPLR9;
3041 mfsdram(sdram_reg, sdram_data);
3042 printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
3043 sdram_reg = SDRAM_INITPLR10;
3044 mfsdram(sdram_reg, sdram_data);
3045 printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
3046 sdram_reg = SDRAM_INITPLR11;
3047 mfsdram(sdram_reg, sdram_data);
3048 printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
3049 sdram_reg = SDRAM_INITPLR12;
3050 mfsdram(sdram_reg, sdram_data);
3051 printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
3052 sdram_reg = SDRAM_INITPLR13;
3053 mfsdram(sdram_reg, sdram_data);
3054 printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
3055 sdram_reg = SDRAM_INITPLR14;
3056 mfsdram(sdram_reg, sdram_data);
3057 printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
3058 sdram_reg = SDRAM_INITPLR15;
3059 mfsdram(sdram_reg, sdram_data);
3060 printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
3061 sdram_reg = SDRAM_RQDC;
3062 mfsdram(sdram_reg, sdram_data);
3063 printf(" SDRAM_RQDC = 0x%08X", sdram_data);
3064 sdram_reg = SDRAM_RFDC;
3065 mfsdram(sdram_reg, sdram_data);
3066 printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
3067 sdram_reg = SDRAM_RDCC;
3068 mfsdram(sdram_reg, sdram_data);
3069 printf(" SDRAM_RDCC = 0x%08X", sdram_data);
3070 sdram_reg = SDRAM_DLCR;
3071 mfsdram(sdram_reg, sdram_data);
3072 printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
3073 sdram_reg = SDRAM_CLKTR;
3074 mfsdram(sdram_reg, sdram_data);
3075 printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
3076 sdram_reg = SDRAM_WRDTR;
3077 mfsdram(sdram_reg, sdram_data);
3078 printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
3079 sdram_reg = SDRAM_SDTR1;
3080 mfsdram(sdram_reg, sdram_data);
3081 printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
3082 sdram_reg = SDRAM_SDTR2;
3083 mfsdram(sdram_reg, sdram_data);
3084 printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
3085 sdram_reg = SDRAM_SDTR3;
3086 mfsdram(sdram_reg, sdram_data);
3087 printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
3088 sdram_reg = SDRAM_MMODE;
3089 mfsdram(sdram_reg, sdram_data);
3090 printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
3091 sdram_reg = SDRAM_MEMODE;
3092 mfsdram(sdram_reg, sdram_data);
3093 printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
3094 sdram_reg = SDRAM_ECCCR;
3095 mfsdram(sdram_reg, sdram_data);
3096 printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
3098 dcr_data = mfdcr(SDRAM_R0BAS);
3099 printf(" MQ0_B0BAS = 0x%08X", dcr_data);
3100 dcr_data = mfdcr(SDRAM_R1BAS);
3101 printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
3102 dcr_data = mfdcr(SDRAM_R2BAS);
3103 printf(" MQ2_B0BAS = 0x%08X", dcr_data);
3104 dcr_data = mfdcr(SDRAM_R3BAS);
3105 printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
3107 #else /* !defined(DEBUG) */
3108 static void ppc440sp_sdram_register_dump(void)
3111 #endif /* defined(DEBUG) */
3112 #elif defined(CONFIG_405EX)
3113 /*-----------------------------------------------------------------------------
3114 * Function: initdram
3115 * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
3116 * banks. The configuration is performed using static, compile-
3118 *---------------------------------------------------------------------------*/
3119 phys_size_t initdram(int board_type)
3122 * Only run this SDRAM init code once. For NAND booting
3123 * targets like Kilauea, we call initdram() early from the
3124 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
3125 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
3126 * which calls initdram() again. This time the controller
3127 * mustn't be reconfigured again since we're already running
3130 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
3133 /* Set Memory Bank Configuration Registers */
3135 mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
3136 mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
3137 mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
3138 mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
3140 /* Set Memory Clock Timing Register */
3142 mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
3144 /* Set Refresh Time Register */
3146 mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
3148 /* Set SDRAM Timing Registers */
3150 mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
3151 mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
3152 mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
3154 /* Set Mode and Extended Mode Registers */
3156 mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
3157 mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
3159 /* Set Memory Controller Options 1 Register */
3161 mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3163 /* Set Manual Initialization Control Registers */
3165 mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3166 mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3167 mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3168 mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3169 mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3170 mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3171 mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3172 mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3173 mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3174 mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3175 mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3176 mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3177 mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3178 mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3179 mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3180 mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3182 /* Set On-Die Termination Registers */
3184 mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3185 mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3186 mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3188 /* Set Write Timing Register */
3190 mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3193 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3194 * SDRAM0_MCOPT2[IPTR] = 1
3197 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3198 SDRAM_MCOPT2_IPTR_EXECUTE));
3201 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3202 * completion of initialization.
3206 mfsdram(SDRAM_MCSTAT, val);
3207 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3209 /* Set Delay Control Registers */
3211 mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3212 mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3213 mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3214 mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3217 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3220 mfsdram(SDRAM_MCOPT2, val);
3221 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3223 #if defined(CONFIG_DDR_ECC)
3224 ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3225 #endif /* defined(CONFIG_DDR_ECC) */
3226 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3228 return (CFG_MBYTES_SDRAM << 20);
3230 #endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */