2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those are 440SP/SPe.
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * COPYRIGHT AMCC CORPORATION 2004
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* define DEBUG for debugging output (obviously ;-)) */
41 #include <asm/processor.h>
44 #if defined(CONFIG_SPD_EEPROM) && \
45 (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
47 /*-----------------------------------------------------------------------------+
49 *-----------------------------------------------------------------------------*/
64 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
66 #define ONE_BILLION 1000000000
68 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
70 #define CMD_NOP (7 << 19)
71 #define CMD_PRECHARGE (2 << 19)
72 #define CMD_REFRESH (1 << 19)
73 #define CMD_EMR (0 << 19)
74 #define CMD_READ (5 << 19)
75 #define CMD_WRITE (4 << 19)
77 #define SELECT_MR (0 << 16)
78 #define SELECT_EMR (1 << 16)
79 #define SELECT_EMR2 (2 << 16)
80 #define SELECT_EMR3 (3 << 16)
83 #define DLL_RESET 0x00000100
85 #define WRITE_RECOV_2 (1 << 9)
86 #define WRITE_RECOV_3 (2 << 9)
87 #define WRITE_RECOV_4 (3 << 9)
88 #define WRITE_RECOV_5 (4 << 9)
89 #define WRITE_RECOV_6 (5 << 9)
91 #define BURST_LEN_4 0x00000002
94 #define ODT_0_OHM 0x00000000
95 #define ODT_50_OHM 0x00000044
96 #define ODT_75_OHM 0x00000004
97 #define ODT_150_OHM 0x00000040
99 #define ODS_FULL 0x00000000
100 #define ODS_REDUCED 0x00000002
102 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
103 #define ODT_EB0R (0x80000000 >> 8)
104 #define ODT_EB0W (0x80000000 >> 7)
105 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
106 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
107 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
109 /* Defines for the Read Cycle Delay test */
110 #define NUMMEMTESTS 8
111 #define NUMMEMWORDS 8
112 #define NUMLOOPS 256 /* memory test loops */
114 #undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
117 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
118 * region. Right now the cache should still be disabled in U-Boot because of the
119 * EMAC driver, that need it's buffer descriptor to be located in non cached
122 * If at some time this restriction doesn't apply anymore, just define
123 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
124 * everything correctly.
126 #ifdef CFG_ENABLE_SDRAM_CACHE
127 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
129 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
132 /* Private Structure Definitions */
134 /* enum only to ease code for cas latency setting */
135 typedef enum ddr_cas_id {
143 /*-----------------------------------------------------------------------------+
145 *-----------------------------------------------------------------------------*/
146 static unsigned long sdram_memsize(void);
147 void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
148 static void get_spd_info(unsigned long *dimm_populated,
149 unsigned char *iic0_dimm_addr,
150 unsigned long num_dimm_banks);
151 static void check_mem_type(unsigned long *dimm_populated,
152 unsigned char *iic0_dimm_addr,
153 unsigned long num_dimm_banks);
154 static void check_frequency(unsigned long *dimm_populated,
155 unsigned char *iic0_dimm_addr,
156 unsigned long num_dimm_banks);
157 static void check_rank_number(unsigned long *dimm_populated,
158 unsigned char *iic0_dimm_addr,
159 unsigned long num_dimm_banks);
160 static void check_voltage_type(unsigned long *dimm_populated,
161 unsigned char *iic0_dimm_addr,
162 unsigned long num_dimm_banks);
163 static void program_memory_queue(unsigned long *dimm_populated,
164 unsigned char *iic0_dimm_addr,
165 unsigned long num_dimm_banks);
166 static void program_codt(unsigned long *dimm_populated,
167 unsigned char *iic0_dimm_addr,
168 unsigned long num_dimm_banks);
169 static void program_mode(unsigned long *dimm_populated,
170 unsigned char *iic0_dimm_addr,
171 unsigned long num_dimm_banks,
172 ddr_cas_id_t *selected_cas,
173 int *write_recovery);
174 static void program_tr(unsigned long *dimm_populated,
175 unsigned char *iic0_dimm_addr,
176 unsigned long num_dimm_banks);
177 static void program_rtr(unsigned long *dimm_populated,
178 unsigned char *iic0_dimm_addr,
179 unsigned long num_dimm_banks);
180 static void program_bxcf(unsigned long *dimm_populated,
181 unsigned char *iic0_dimm_addr,
182 unsigned long num_dimm_banks);
183 static void program_copt1(unsigned long *dimm_populated,
184 unsigned char *iic0_dimm_addr,
185 unsigned long num_dimm_banks);
186 static void program_initplr(unsigned long *dimm_populated,
187 unsigned char *iic0_dimm_addr,
188 unsigned long num_dimm_banks,
189 ddr_cas_id_t selected_cas,
191 static unsigned long is_ecc_enabled(void);
192 #ifdef CONFIG_DDR_ECC
193 static void program_ecc(unsigned long *dimm_populated,
194 unsigned char *iic0_dimm_addr,
195 unsigned long num_dimm_banks,
196 unsigned long tlb_word2_i_value);
197 static void program_ecc_addr(unsigned long start_address,
198 unsigned long num_bytes,
199 unsigned long tlb_word2_i_value);
201 static void program_DQS_calibration(unsigned long *dimm_populated,
202 unsigned char *iic0_dimm_addr,
203 unsigned long num_dimm_banks);
204 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
205 static void test(void);
207 static void DQS_calibration_process(void);
210 static void ppc440sp_sdram_register_dump(void);
212 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
213 void dcbz_area(u32 start_address, u32 num_bytes);
216 static u32 mfdcr_any(u32 dcr)
221 case SDRAM_R0BAS + 0:
222 val = mfdcr(SDRAM_R0BAS + 0);
224 case SDRAM_R0BAS + 1:
225 val = mfdcr(SDRAM_R0BAS + 1);
227 case SDRAM_R0BAS + 2:
228 val = mfdcr(SDRAM_R0BAS + 2);
230 case SDRAM_R0BAS + 3:
231 val = mfdcr(SDRAM_R0BAS + 3);
234 printf("DCR %d not defined in case statement!!!\n", dcr);
235 val = 0; /* just to satisfy the compiler */
241 static void mtdcr_any(u32 dcr, u32 val)
244 case SDRAM_R0BAS + 0:
245 mtdcr(SDRAM_R0BAS + 0, val);
247 case SDRAM_R0BAS + 1:
248 mtdcr(SDRAM_R0BAS + 1, val);
250 case SDRAM_R0BAS + 2:
251 mtdcr(SDRAM_R0BAS + 2, val);
253 case SDRAM_R0BAS + 3:
254 mtdcr(SDRAM_R0BAS + 3, val);
257 printf("DCR %d not defined in case statement!!!\n", dcr);
261 static unsigned char spd_read(uchar chip, uint addr)
263 unsigned char data[2];
265 if (i2c_probe(chip) == 0)
266 if (i2c_read(chip, addr, 1, data, 1) == 0)
272 /*-----------------------------------------------------------------------------+
274 *-----------------------------------------------------------------------------*/
275 static unsigned long sdram_memsize(void)
277 unsigned long mem_size;
278 unsigned long mcopt2;
279 unsigned long mcstat;
286 mfsdram(SDRAM_MCOPT2, mcopt2);
287 mfsdram(SDRAM_MCSTAT, mcstat);
289 /* DDR controller must be enabled and not in self-refresh. */
290 /* Otherwise memsize is zero. */
291 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
292 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
293 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
294 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
295 for (i = 0; i < MAXBXCF; i++) {
296 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
298 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
299 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
302 case SDRAM_RXBAS_SDSZ_8:
305 case SDRAM_RXBAS_SDSZ_16:
308 case SDRAM_RXBAS_SDSZ_32:
311 case SDRAM_RXBAS_SDSZ_64:
314 case SDRAM_RXBAS_SDSZ_128:
317 case SDRAM_RXBAS_SDSZ_256:
320 case SDRAM_RXBAS_SDSZ_512:
323 case SDRAM_RXBAS_SDSZ_1024:
326 case SDRAM_RXBAS_SDSZ_2048:
329 case SDRAM_RXBAS_SDSZ_4096:
340 mem_size *= 1024 * 1024;
344 /*-----------------------------------------------------------------------------+
345 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
346 * Note: This routine runs from flash with a stack set up in the chip's
347 * sram space. It is important that the routine does not require .sbss, .bss or
348 * .data sections. It also cannot call routines that require these sections.
349 *-----------------------------------------------------------------------------*/
350 /*-----------------------------------------------------------------------------
352 * Description: Configures SDRAM memory banks for DDR operation.
353 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
354 * via the IIC bus and then configures the DDR SDRAM memory
355 * banks appropriately. If Auto Memory Configuration is
356 * not used, it is assumed that no DIMM is plugged
357 *-----------------------------------------------------------------------------*/
358 long int initdram(int board_type)
360 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
361 unsigned char spd0[MAX_SPD_BYTES];
362 unsigned char spd1[MAX_SPD_BYTES];
363 unsigned char *dimm_spd[MAXDIMMS];
364 unsigned long dimm_populated[MAXDIMMS];
365 unsigned long num_dimm_banks; /* on board dimm banks */
367 ddr_cas_id_t selected_cas;
369 unsigned long dram_size = 0;
371 num_dimm_banks = sizeof(iic0_dimm_addr);
373 /*------------------------------------------------------------------
374 * Set up an array of SPD matrixes.
375 *-----------------------------------------------------------------*/
379 /*------------------------------------------------------------------
380 * Reset the DDR-SDRAM controller.
381 *-----------------------------------------------------------------*/
382 mtsdr(SDR0_SRST, (0x80000000 >> 10));
383 mtsdr(SDR0_SRST, 0x00000000);
386 * Make sure I2C controller is initialized
390 /* switch to correct I2C bus */
391 I2C_SET_BUS(CFG_SPD_BUS_NUM);
392 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
394 /*------------------------------------------------------------------
395 * Clear out the serial presence detect buffers.
396 * Perform IIC reads from the dimm. Fill in the spds.
397 * Check to see if the dimm slots are populated
398 *-----------------------------------------------------------------*/
399 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
401 /*------------------------------------------------------------------
402 * Check the memory type for the dimms plugged.
403 *-----------------------------------------------------------------*/
404 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
406 /*------------------------------------------------------------------
407 * Check the frequency supported for the dimms plugged.
408 *-----------------------------------------------------------------*/
409 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
411 /*------------------------------------------------------------------
412 * Check the total rank number.
413 *-----------------------------------------------------------------*/
414 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
416 /*------------------------------------------------------------------
417 * Check the voltage type for the dimms plugged.
418 *-----------------------------------------------------------------*/
419 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
421 /*------------------------------------------------------------------
422 * Program SDRAM controller options 2 register
423 * Except Enabling of the memory controller.
424 *-----------------------------------------------------------------*/
425 mfsdram(SDRAM_MCOPT2, val);
426 mtsdram(SDRAM_MCOPT2,
428 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
429 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
430 SDRAM_MCOPT2_ISIE_MASK))
431 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
432 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
433 SDRAM_MCOPT2_ISIE_ENABLE));
435 /*------------------------------------------------------------------
436 * Program SDRAM controller options 1 register
437 * Note: Does not enable the memory controller.
438 *-----------------------------------------------------------------*/
439 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
441 /*------------------------------------------------------------------
442 * Set the SDRAM Controller On Die Termination Register
443 *-----------------------------------------------------------------*/
444 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
446 /*------------------------------------------------------------------
447 * Program SDRAM refresh register.
448 *-----------------------------------------------------------------*/
449 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
451 /*------------------------------------------------------------------
452 * Program SDRAM mode register.
453 *-----------------------------------------------------------------*/
454 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
455 &selected_cas, &write_recovery);
457 /*------------------------------------------------------------------
458 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
459 *-----------------------------------------------------------------*/
460 mfsdram(SDRAM_WRDTR, val);
461 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
462 (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
464 /*------------------------------------------------------------------
465 * Set the SDRAM Clock Timing Register
466 *-----------------------------------------------------------------*/
467 mfsdram(SDRAM_CLKTR, val);
468 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
470 /*------------------------------------------------------------------
471 * Program the BxCF registers.
472 *-----------------------------------------------------------------*/
473 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
475 /*------------------------------------------------------------------
476 * Program SDRAM timing registers.
477 *-----------------------------------------------------------------*/
478 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
480 /*------------------------------------------------------------------
481 * Set the Extended Mode register
482 *-----------------------------------------------------------------*/
483 mfsdram(SDRAM_MEMODE, val);
484 mtsdram(SDRAM_MEMODE,
485 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
486 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
487 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
488 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
490 /*------------------------------------------------------------------
491 * Program Initialization preload registers.
492 *-----------------------------------------------------------------*/
493 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
494 selected_cas, write_recovery);
496 /*------------------------------------------------------------------
497 * Delay to ensure 200usec have elapsed since reset.
498 *-----------------------------------------------------------------*/
501 /*------------------------------------------------------------------
502 * Set the memory queue core base addr.
503 *-----------------------------------------------------------------*/
504 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
506 /*------------------------------------------------------------------
507 * Program SDRAM controller options 2 register
508 * Enable the memory controller.
509 *-----------------------------------------------------------------*/
510 mfsdram(SDRAM_MCOPT2, val);
511 mtsdram(SDRAM_MCOPT2,
512 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
513 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
514 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
516 /*------------------------------------------------------------------
517 * Wait for SDRAM_CFG0_DC_EN to complete.
518 *-----------------------------------------------------------------*/
520 mfsdram(SDRAM_MCSTAT, val);
521 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
523 /* get installed memory size */
524 dram_size = sdram_memsize();
526 /* and program tlb entries for this size (dynamic) */
527 program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
529 /*------------------------------------------------------------------
531 *-----------------------------------------------------------------*/
532 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
534 #ifdef CONFIG_DDR_ECC
535 /*------------------------------------------------------------------
536 * If ecc is enabled, initialize the parity bits.
537 *-----------------------------------------------------------------*/
538 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
542 ppc440sp_sdram_register_dump();
548 static void get_spd_info(unsigned long *dimm_populated,
549 unsigned char *iic0_dimm_addr,
550 unsigned long num_dimm_banks)
552 unsigned long dimm_num;
553 unsigned long dimm_found;
554 unsigned char num_of_bytes;
555 unsigned char total_size;
558 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
562 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
563 debug("\nspd_read(0x%x) returned %d\n",
564 iic0_dimm_addr[dimm_num], num_of_bytes);
565 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
566 debug("spd_read(0x%x) returned %d\n",
567 iic0_dimm_addr[dimm_num], total_size);
569 if ((num_of_bytes != 0) && (total_size != 0)) {
570 dimm_populated[dimm_num] = TRUE;
572 debug("DIMM slot %lu: populated\n", dimm_num);
574 dimm_populated[dimm_num] = FALSE;
575 debug("DIMM slot %lu: Not populated\n", dimm_num);
579 if (dimm_found == FALSE) {
580 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
585 #ifdef CONFIG_ADD_RAM_INFO
586 void board_add_ram_info(int use_default)
590 if (is_ecc_enabled())
591 puts(" (ECC enabled, ");
593 puts(" (ECC not enabled, ");
595 mfsdram(SDRAM_MMODE, val);
596 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
597 printf("CL=%d)", val);
601 /*------------------------------------------------------------------
602 * For the memory DIMMs installed, this routine verifies that they
603 * really are DDR specific DIMMs.
604 *-----------------------------------------------------------------*/
605 static void check_mem_type(unsigned long *dimm_populated,
606 unsigned char *iic0_dimm_addr,
607 unsigned long num_dimm_banks)
609 unsigned long dimm_num;
610 unsigned long dimm_type;
612 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
613 if (dimm_populated[dimm_num] == TRUE) {
614 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
617 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
618 "slot %d.\n", (unsigned int)dimm_num);
619 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
620 printf("Replace the DIMM module with a supported DIMM.\n\n");
624 printf("ERROR: EDO DIMM detected in slot %d.\n",
625 (unsigned int)dimm_num);
626 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
627 printf("Replace the DIMM module with a supported DIMM.\n\n");
631 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
632 (unsigned int)dimm_num);
633 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
634 printf("Replace the DIMM module with a supported DIMM.\n\n");
638 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
639 (unsigned int)dimm_num);
640 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
641 printf("Replace the DIMM module with a supported DIMM.\n\n");
645 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
646 (unsigned int)dimm_num);
647 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
648 printf("Replace the DIMM module with a supported DIMM.\n\n");
652 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
653 (unsigned int)dimm_num);
654 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
655 printf("Replace the DIMM module with a supported DIMM.\n\n");
659 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
660 dimm_populated[dimm_num] = SDRAM_DDR1;
663 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
664 dimm_populated[dimm_num] = SDRAM_DDR2;
667 printf("ERROR: Unknown DIMM detected in slot %d.\n",
668 (unsigned int)dimm_num);
669 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
670 printf("Replace the DIMM module with a supported DIMM.\n\n");
676 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
677 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
678 && (dimm_populated[dimm_num] != SDRAM_NONE)
679 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
680 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
686 /*------------------------------------------------------------------
687 * For the memory DIMMs installed, this routine verifies that
688 * frequency previously calculated is supported.
689 *-----------------------------------------------------------------*/
690 static void check_frequency(unsigned long *dimm_populated,
691 unsigned char *iic0_dimm_addr,
692 unsigned long num_dimm_banks)
694 unsigned long dimm_num;
695 unsigned long tcyc_reg;
696 unsigned long cycle_time;
697 unsigned long calc_cycle_time;
698 unsigned long sdram_freq;
699 unsigned long sdr_ddrpll;
700 PPC440_SYS_INFO board_cfg;
702 /*------------------------------------------------------------------
703 * Get the board configuration info.
704 *-----------------------------------------------------------------*/
705 get_sys_info(&board_cfg);
707 mfsdr(SDR0_DDR0, sdr_ddrpll);
708 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
711 * calc_cycle_time is calculated from DDR frequency set by board/chip
712 * and is expressed in multiple of 10 picoseconds
713 * to match the way DIMM cycle time is calculated below.
715 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
717 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
718 if (dimm_populated[dimm_num] != SDRAM_NONE) {
719 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
721 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
722 * the higher order nibble (bits 4-7) designates the cycle time
723 * to a granularity of 1ns;
724 * the value presented by the lower order nibble (bits 0-3)
725 * has a granularity of .1ns and is added to the value designated
726 * by the higher nibble. In addition, four lines of the lower order
727 * nibble are assigned to support +.25,+.33, +.66 and +.75.
729 /* Convert from hex to decimal */
730 if ((tcyc_reg & 0x0F) == 0x0D)
731 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
732 else if ((tcyc_reg & 0x0F) == 0x0C)
733 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
734 else if ((tcyc_reg & 0x0F) == 0x0B)
735 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
736 else if ((tcyc_reg & 0x0F) == 0x0A)
737 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
739 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
740 ((tcyc_reg & 0x0F)*10);
741 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
743 if (cycle_time > (calc_cycle_time + 10)) {
745 * the provided sdram cycle_time is too small
746 * for the available DIMM cycle_time.
747 * The additionnal 100ps is here to accept a small incertainty.
749 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
750 "slot %d \n while calculated cycle time is %d ps.\n",
751 (unsigned int)(cycle_time*10),
752 (unsigned int)dimm_num,
753 (unsigned int)(calc_cycle_time*10));
754 printf("Replace the DIMM, or change DDR frequency via "
755 "strapping bits.\n\n");
762 /*------------------------------------------------------------------
763 * For the memory DIMMs installed, this routine verifies two
764 * ranks/banks maximum are availables.
765 *-----------------------------------------------------------------*/
766 static void check_rank_number(unsigned long *dimm_populated,
767 unsigned char *iic0_dimm_addr,
768 unsigned long num_dimm_banks)
770 unsigned long dimm_num;
771 unsigned long dimm_rank;
772 unsigned long total_rank = 0;
774 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
775 if (dimm_populated[dimm_num] != SDRAM_NONE) {
776 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
777 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
778 dimm_rank = (dimm_rank & 0x0F) +1;
780 dimm_rank = dimm_rank & 0x0F;
783 if (dimm_rank > MAXRANKS) {
784 printf("ERROR: DRAM DIMM detected with %d ranks in "
785 "slot %d is not supported.\n", dimm_rank, dimm_num);
786 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
787 printf("Replace the DIMM module with a supported DIMM.\n\n");
790 total_rank += dimm_rank;
792 if (total_rank > MAXRANKS) {
793 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
794 "for all slots.\n", (unsigned int)total_rank);
795 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
796 printf("Remove one of the DIMM modules.\n\n");
802 /*------------------------------------------------------------------
803 * only support 2.5V modules.
804 * This routine verifies this.
805 *-----------------------------------------------------------------*/
806 static void check_voltage_type(unsigned long *dimm_populated,
807 unsigned char *iic0_dimm_addr,
808 unsigned long num_dimm_banks)
810 unsigned long dimm_num;
811 unsigned long voltage_type;
813 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
814 if (dimm_populated[dimm_num] != SDRAM_NONE) {
815 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
816 switch (voltage_type) {
818 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
819 printf("This DIMM is 5.0 Volt/TTL.\n");
820 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
821 (unsigned int)dimm_num);
825 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
826 printf("This DIMM is LVTTL.\n");
827 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
828 (unsigned int)dimm_num);
832 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
833 printf("This DIMM is 1.5 Volt.\n");
834 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
835 (unsigned int)dimm_num);
839 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
840 printf("This DIMM is 3.3 Volt/TTL.\n");
841 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
842 (unsigned int)dimm_num);
846 /* 2.5 Voltage only for DDR1 */
849 /* 1.8 Voltage only for DDR2 */
852 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
853 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
854 (unsigned int)dimm_num);
862 /*-----------------------------------------------------------------------------+
864 *-----------------------------------------------------------------------------*/
865 static void program_copt1(unsigned long *dimm_populated,
866 unsigned char *iic0_dimm_addr,
867 unsigned long num_dimm_banks)
869 unsigned long dimm_num;
870 unsigned long mcopt1;
871 unsigned long ecc_enabled;
872 unsigned long ecc = 0;
873 unsigned long data_width = 0;
874 unsigned long dimm_32bit;
875 unsigned long dimm_64bit;
876 unsigned long registered = 0;
877 unsigned long attribute = 0;
878 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
879 unsigned long bankcount;
880 unsigned long ddrtype;
883 #ifdef CONFIG_DDR_ECC
893 /*------------------------------------------------------------------
894 * Set memory controller options reg 1, SDRAM_MCOPT1.
895 *-----------------------------------------------------------------*/
896 mfsdram(SDRAM_MCOPT1, val);
897 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
898 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
899 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
900 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
901 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
902 SDRAM_MCOPT1_DREF_MASK);
904 mcopt1 |= SDRAM_MCOPT1_QDEP;
905 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
906 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
907 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
908 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
909 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
911 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
912 if (dimm_populated[dimm_num] != SDRAM_NONE) {
913 /* test ecc support */
914 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
915 if (ecc != 0x02) /* ecc not supported */
918 /* test bank count */
919 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
920 if (bankcount == 0x04) /* bank count = 4 */
921 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
922 else /* bank count = 8 */
923 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
926 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
927 /* test for buffered/unbuffered, registered, differential clocks */
928 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
929 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
931 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
933 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
934 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
935 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
936 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
937 if (registered == 1) { /* DDR2 always buffered */
938 /* TODO: what about above comments ? */
939 mcopt1 |= SDRAM_MCOPT1_RDEN;
942 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
943 if ((attribute & 0x02) == 0x00) {
944 /* buffered not supported */
947 mcopt1 |= SDRAM_MCOPT1_RDEN;
952 else if (dimm_num == 1) {
953 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
954 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
955 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
956 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
957 if (registered == 1) {
958 /* DDR2 always buffered */
959 mcopt1 |= SDRAM_MCOPT1_RDEN;
962 if ((attribute & 0x02) == 0x00) {
963 /* buffered not supported */
966 mcopt1 |= SDRAM_MCOPT1_RDEN;
972 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
973 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
974 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
976 switch (data_width) {
986 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
988 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
994 /* verify matching properties */
995 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
997 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1002 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1003 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1006 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1007 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1008 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1009 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1011 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1015 if (ecc_enabled == TRUE)
1016 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1018 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1020 mtsdram(SDRAM_MCOPT1, mcopt1);
1023 /*-----------------------------------------------------------------------------+
1025 *-----------------------------------------------------------------------------*/
1026 static void program_codt(unsigned long *dimm_populated,
1027 unsigned char *iic0_dimm_addr,
1028 unsigned long num_dimm_banks)
1031 unsigned long modt0 = 0;
1032 unsigned long modt1 = 0;
1033 unsigned long modt2 = 0;
1034 unsigned long modt3 = 0;
1035 unsigned char dimm_num;
1036 unsigned char dimm_rank;
1037 unsigned char total_rank = 0;
1038 unsigned char total_dimm = 0;
1039 unsigned char dimm_type = 0;
1040 unsigned char firstSlot = 0;
1042 /*------------------------------------------------------------------
1043 * Set the SDRAM Controller On Die Termination Register
1044 *-----------------------------------------------------------------*/
1045 mfsdram(SDRAM_CODT, codt);
1046 codt |= (SDRAM_CODT_IO_NMODE
1047 & (~SDRAM_CODT_DQS_SINGLE_END
1048 & ~SDRAM_CODT_CKSE_SINGLE_END
1049 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1050 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1052 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1053 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1054 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1055 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1056 dimm_rank = (dimm_rank & 0x0F) + 1;
1057 dimm_type = SDRAM_DDR2;
1059 dimm_rank = dimm_rank & 0x0F;
1060 dimm_type = SDRAM_DDR1;
1063 total_rank += dimm_rank;
1065 if ((dimm_num == 0) && (total_dimm == 1))
1071 if (dimm_type == SDRAM_DDR2) {
1072 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1073 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1074 if (total_rank == 1) {
1075 codt |= CALC_ODT_R(0);
1076 modt0 = CALC_ODT_W(0);
1081 if (total_rank == 2) {
1082 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1083 modt0 = CALC_ODT_W(0);
1084 modt1 = CALC_ODT_W(0);
1088 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1089 if (total_rank == 1) {
1090 codt |= CALC_ODT_R(2);
1093 modt2 = CALC_ODT_W(2);
1096 if (total_rank == 2) {
1097 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1100 modt2 = CALC_ODT_W(2);
1101 modt3 = CALC_ODT_W(2);
1104 if (total_dimm == 2) {
1105 if (total_rank == 2) {
1106 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1107 modt0 = CALC_ODT_RW(2);
1109 modt2 = CALC_ODT_RW(0);
1112 if (total_rank == 4) {
1113 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
1114 modt0 = CALC_ODT_RW(2);
1116 modt2 = CALC_ODT_RW(0);
1121 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1127 if (total_dimm == 1) {
1128 if (total_rank == 1)
1130 if (total_rank == 2)
1133 if (total_dimm == 2) {
1134 if (total_rank == 2)
1136 if (total_rank == 4)
1141 debug("nb of dimm %d\n", total_dimm);
1142 debug("nb of rank %d\n", total_rank);
1143 if (total_dimm == 1)
1144 debug("dimm in slot %d\n", firstSlot);
1146 mtsdram(SDRAM_CODT, codt);
1147 mtsdram(SDRAM_MODT0, modt0);
1148 mtsdram(SDRAM_MODT1, modt1);
1149 mtsdram(SDRAM_MODT2, modt2);
1150 mtsdram(SDRAM_MODT3, modt3);
1153 /*-----------------------------------------------------------------------------+
1155 *-----------------------------------------------------------------------------*/
1156 static void program_initplr(unsigned long *dimm_populated,
1157 unsigned char *iic0_dimm_addr,
1158 unsigned long num_dimm_banks,
1159 ddr_cas_id_t selected_cas,
1173 /******************************************************
1174 ** Assumption: if more than one DIMM, all DIMMs are the same
1175 ** as already checked in check_memory_type
1176 ******************************************************/
1178 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1179 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1180 mtsdram(SDRAM_INITPLR1, 0x81900400);
1181 mtsdram(SDRAM_INITPLR2, 0x81810000);
1182 mtsdram(SDRAM_INITPLR3, 0xff800162);
1183 mtsdram(SDRAM_INITPLR4, 0x81900400);
1184 mtsdram(SDRAM_INITPLR5, 0x86080000);
1185 mtsdram(SDRAM_INITPLR6, 0x86080000);
1186 mtsdram(SDRAM_INITPLR7, 0x81000062);
1187 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1188 switch (selected_cas) {
1199 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1206 * ToDo - Still a problem with the write recovery:
1207 * On the Corsair CM2X512-5400C4 module, setting write recovery
1208 * in the INITPLR reg to the value calculated in program_mode()
1209 * results in not correctly working DDR2 memory (crash after
1212 * So for now, set the write recovery to 3. This seems to work
1213 * on the Corair module too.
1217 switch (write_recovery) {
1231 printf("ERROR: write recovery not support (%d)", write_recovery);
1236 wr = WRITE_RECOV_3; /* test-only, see description above */
1239 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1240 if (dimm_populated[dimm_num] != SDRAM_NONE)
1242 if (total_dimm == 1) {
1245 } else if (total_dimm == 2) {
1249 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1253 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1254 emr = CMD_EMR | SELECT_EMR | odt | ods;
1255 emr2 = CMD_EMR | SELECT_EMR2;
1256 emr3 = CMD_EMR | SELECT_EMR3;
1257 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1259 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1260 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1261 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1262 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1263 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1265 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1266 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1267 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1268 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1269 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1270 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1271 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1272 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1274 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1279 /*------------------------------------------------------------------
1280 * This routine programs the SDRAM_MMODE register.
1281 * the selected_cas is an output parameter, that will be passed
1282 * by caller to call the above program_initplr( )
1283 *-----------------------------------------------------------------*/
1284 static void program_mode(unsigned long *dimm_populated,
1285 unsigned char *iic0_dimm_addr,
1286 unsigned long num_dimm_banks,
1287 ddr_cas_id_t *selected_cas,
1288 int *write_recovery)
1290 unsigned long dimm_num;
1291 unsigned long sdram_ddr1;
1292 unsigned long t_wr_ns;
1293 unsigned long t_wr_clk;
1294 unsigned long cas_bit;
1295 unsigned long cas_index;
1296 unsigned long sdram_freq;
1297 unsigned long ddr_check;
1298 unsigned long mmode;
1299 unsigned long tcyc_reg;
1300 unsigned long cycle_2_0_clk;
1301 unsigned long cycle_2_5_clk;
1302 unsigned long cycle_3_0_clk;
1303 unsigned long cycle_4_0_clk;
1304 unsigned long cycle_5_0_clk;
1305 unsigned long max_2_0_tcyc_ns_x_100;
1306 unsigned long max_2_5_tcyc_ns_x_100;
1307 unsigned long max_3_0_tcyc_ns_x_100;
1308 unsigned long max_4_0_tcyc_ns_x_100;
1309 unsigned long max_5_0_tcyc_ns_x_100;
1310 unsigned long cycle_time_ns_x_100[3];
1311 PPC440_SYS_INFO board_cfg;
1312 unsigned char cas_2_0_available;
1313 unsigned char cas_2_5_available;
1314 unsigned char cas_3_0_available;
1315 unsigned char cas_4_0_available;
1316 unsigned char cas_5_0_available;
1317 unsigned long sdr_ddrpll;
1319 /*------------------------------------------------------------------
1320 * Get the board configuration info.
1321 *-----------------------------------------------------------------*/
1322 get_sys_info(&board_cfg);
1324 mfsdr(SDR0_DDR0, sdr_ddrpll);
1325 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1327 /*------------------------------------------------------------------
1328 * Handle the timing. We need to find the worst case timing of all
1329 * the dimm modules installed.
1330 *-----------------------------------------------------------------*/
1332 cas_2_0_available = TRUE;
1333 cas_2_5_available = TRUE;
1334 cas_3_0_available = TRUE;
1335 cas_4_0_available = TRUE;
1336 cas_5_0_available = TRUE;
1337 max_2_0_tcyc_ns_x_100 = 10;
1338 max_2_5_tcyc_ns_x_100 = 10;
1339 max_3_0_tcyc_ns_x_100 = 10;
1340 max_4_0_tcyc_ns_x_100 = 10;
1341 max_5_0_tcyc_ns_x_100 = 10;
1344 /* loop through all the DIMM slots on the board */
1345 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1346 /* If a dimm is installed in a particular slot ... */
1347 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1348 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1353 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1354 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1356 /* For a particular DIMM, grab the three CAS values it supports */
1357 for (cas_index = 0; cas_index < 3; cas_index++) {
1358 switch (cas_index) {
1360 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1363 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1366 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1370 if ((tcyc_reg & 0x0F) >= 10) {
1371 if ((tcyc_reg & 0x0F) == 0x0D) {
1372 /* Convert from hex to decimal */
1373 cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1375 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1376 "in slot %d\n", (unsigned int)dimm_num);
1380 /* Convert from hex to decimal */
1381 cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) +
1382 ((tcyc_reg & 0x0F)*10);
1386 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1387 /* supported for a particular DIMM. */
1392 * DDR devices use the following bitmask for CAS latency:
1393 * Bit 7 6 5 4 3 2 1 0
1394 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1396 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1397 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1402 cas_4_0_available = FALSE;
1405 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1406 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1411 cas_3_0_available = FALSE;
1414 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1415 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1420 cas_2_5_available = FALSE;
1423 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1424 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1429 cas_2_0_available = FALSE;
1433 * DDR2 devices use the following bitmask for CAS latency:
1434 * Bit 7 6 5 4 3 2 1 0
1435 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1437 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1438 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1443 cas_5_0_available = FALSE;
1446 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1447 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1452 cas_4_0_available = FALSE;
1455 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1456 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1461 cas_3_0_available = FALSE;
1467 /*------------------------------------------------------------------
1468 * Set the SDRAM mode, SDRAM_MMODE
1469 *-----------------------------------------------------------------*/
1470 mfsdram(SDRAM_MMODE, mmode);
1471 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1473 /* add 10 here because of rounding problems */
1474 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1475 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1476 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1477 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1478 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1480 if (sdram_ddr1 == TRUE) { /* DDR1 */
1481 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1482 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1483 *selected_cas = DDR_CAS_2;
1484 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1485 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1486 *selected_cas = DDR_CAS_2_5;
1487 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1488 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1489 *selected_cas = DDR_CAS_3;
1491 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1492 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1493 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1497 debug("cas_3_0_available=%d\n", cas_3_0_available);
1498 debug("cas_4_0_available=%d\n", cas_4_0_available);
1499 debug("cas_5_0_available=%d\n", cas_5_0_available);
1500 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1501 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1502 *selected_cas = DDR_CAS_3;
1503 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1504 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1505 *selected_cas = DDR_CAS_4;
1506 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1507 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1508 *selected_cas = DDR_CAS_5;
1510 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1511 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1512 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1513 printf("cas3=%d cas4=%d cas5=%d\n",
1514 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1515 printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1516 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1521 if (sdram_ddr1 == TRUE)
1522 mmode |= SDRAM_MMODE_WR_DDR1;
1525 /* loop through all the DIMM slots on the board */
1526 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1527 /* If a dimm is installed in a particular slot ... */
1528 if (dimm_populated[dimm_num] != SDRAM_NONE)
1529 t_wr_ns = max(t_wr_ns,
1530 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1534 * convert from nanoseconds to ddr clocks
1535 * round up if necessary
1537 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1538 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1539 if (sdram_freq != ddr_check)
1547 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1550 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1553 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1556 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1559 *write_recovery = t_wr_clk;
1562 debug("CAS latency = %d\n", *selected_cas);
1563 debug("Write recovery = %d\n", *write_recovery);
1565 mtsdram(SDRAM_MMODE, mmode);
1568 /*-----------------------------------------------------------------------------+
1570 *-----------------------------------------------------------------------------*/
1571 static void program_rtr(unsigned long *dimm_populated,
1572 unsigned char *iic0_dimm_addr,
1573 unsigned long num_dimm_banks)
1575 PPC440_SYS_INFO board_cfg;
1576 unsigned long max_refresh_rate;
1577 unsigned long dimm_num;
1578 unsigned long refresh_rate_type;
1579 unsigned long refresh_rate;
1581 unsigned long sdram_freq;
1582 unsigned long sdr_ddrpll;
1585 /*------------------------------------------------------------------
1586 * Get the board configuration info.
1587 *-----------------------------------------------------------------*/
1588 get_sys_info(&board_cfg);
1590 /*------------------------------------------------------------------
1591 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1592 *-----------------------------------------------------------------*/
1593 mfsdr(SDR0_DDR0, sdr_ddrpll);
1594 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1596 max_refresh_rate = 0;
1597 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1598 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1600 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1601 refresh_rate_type &= 0x7F;
1602 switch (refresh_rate_type) {
1604 refresh_rate = 15625;
1607 refresh_rate = 3906;
1610 refresh_rate = 7812;
1613 refresh_rate = 31250;
1616 refresh_rate = 62500;
1619 refresh_rate = 125000;
1623 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1624 (unsigned int)dimm_num);
1625 printf("Replace the DIMM module with a supported DIMM.\n\n");
1630 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1634 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1635 mfsdram(SDRAM_RTR, val);
1636 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1637 (SDRAM_RTR_RINT_ENCODE(rint)));
1640 /*------------------------------------------------------------------
1641 * This routine programs the SDRAM_TRx registers.
1642 *-----------------------------------------------------------------*/
1643 static void program_tr(unsigned long *dimm_populated,
1644 unsigned char *iic0_dimm_addr,
1645 unsigned long num_dimm_banks)
1647 unsigned long dimm_num;
1648 unsigned long sdram_ddr1;
1649 unsigned long t_rp_ns;
1650 unsigned long t_rcd_ns;
1651 unsigned long t_rrd_ns;
1652 unsigned long t_ras_ns;
1653 unsigned long t_rc_ns;
1654 unsigned long t_rfc_ns;
1655 unsigned long t_wpc_ns;
1656 unsigned long t_wtr_ns;
1657 unsigned long t_rpc_ns;
1658 unsigned long t_rp_clk;
1659 unsigned long t_rcd_clk;
1660 unsigned long t_rrd_clk;
1661 unsigned long t_ras_clk;
1662 unsigned long t_rc_clk;
1663 unsigned long t_rfc_clk;
1664 unsigned long t_wpc_clk;
1665 unsigned long t_wtr_clk;
1666 unsigned long t_rpc_clk;
1667 unsigned long sdtr1, sdtr2, sdtr3;
1668 unsigned long ddr_check;
1669 unsigned long sdram_freq;
1670 unsigned long sdr_ddrpll;
1672 PPC440_SYS_INFO board_cfg;
1674 /*------------------------------------------------------------------
1675 * Get the board configuration info.
1676 *-----------------------------------------------------------------*/
1677 get_sys_info(&board_cfg);
1679 mfsdr(SDR0_DDR0, sdr_ddrpll);
1680 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1682 /*------------------------------------------------------------------
1683 * Handle the timing. We need to find the worst case timing of all
1684 * the dimm modules installed.
1685 *-----------------------------------------------------------------*/
1697 /* loop through all the DIMM slots on the board */
1698 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1699 /* If a dimm is installed in a particular slot ... */
1700 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1701 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1706 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1707 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1708 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1709 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1710 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1711 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1715 /*------------------------------------------------------------------
1716 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1717 *-----------------------------------------------------------------*/
1718 mfsdram(SDRAM_SDTR1, sdtr1);
1719 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1720 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1722 /* default values */
1723 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1724 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1726 /* normal operations */
1727 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1728 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1730 mtsdram(SDRAM_SDTR1, sdtr1);
1732 /*------------------------------------------------------------------
1733 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1734 *-----------------------------------------------------------------*/
1735 mfsdram(SDRAM_SDTR2, sdtr2);
1736 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1737 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1738 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1739 SDRAM_SDTR2_RRD_MASK);
1742 * convert t_rcd from nanoseconds to ddr clocks
1743 * round up if necessary
1745 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1746 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1747 if (sdram_freq != ddr_check)
1750 switch (t_rcd_clk) {
1753 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1756 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1759 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1762 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1765 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1769 if (sdram_ddr1 == TRUE) { /* DDR1 */
1770 if (sdram_freq < 200000000) {
1771 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1772 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1773 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1775 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1776 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1777 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1780 /* loop through all the DIMM slots on the board */
1781 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1782 /* If a dimm is installed in a particular slot ... */
1783 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1784 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1785 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1786 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1791 * convert from nanoseconds to ddr clocks
1792 * round up if necessary
1794 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1795 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1796 if (sdram_freq != ddr_check)
1799 switch (t_wpc_clk) {
1803 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1806 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1809 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1812 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1815 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1820 * convert from nanoseconds to ddr clocks
1821 * round up if necessary
1823 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1824 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1825 if (sdram_freq != ddr_check)
1828 switch (t_wtr_clk) {
1831 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1834 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1837 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1840 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1845 * convert from nanoseconds to ddr clocks
1846 * round up if necessary
1848 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1849 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1850 if (sdram_freq != ddr_check)
1853 switch (t_rpc_clk) {
1857 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1860 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1863 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1869 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1872 * convert t_rrd from nanoseconds to ddr clocks
1873 * round up if necessary
1875 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1876 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1877 if (sdram_freq != ddr_check)
1881 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1883 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1886 * convert t_rp from nanoseconds to ddr clocks
1887 * round up if necessary
1889 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1890 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1891 if (sdram_freq != ddr_check)
1899 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1902 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1905 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1908 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1911 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1915 mtsdram(SDRAM_SDTR2, sdtr2);
1917 /*------------------------------------------------------------------
1918 * Set the SDRAM Timing Reg 3, SDRAM_TR3
1919 *-----------------------------------------------------------------*/
1920 mfsdram(SDRAM_SDTR3, sdtr3);
1921 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
1922 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1925 * convert t_ras from nanoseconds to ddr clocks
1926 * round up if necessary
1928 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1929 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1930 if (sdram_freq != ddr_check)
1933 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
1936 * convert t_rc from nanoseconds to ddr clocks
1937 * round up if necessary
1939 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
1940 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
1941 if (sdram_freq != ddr_check)
1944 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
1946 /* default xcs value */
1947 sdtr3 |= SDRAM_SDTR3_XCS;
1950 * convert t_rfc from nanoseconds to ddr clocks
1951 * round up if necessary
1953 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
1954 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
1955 if (sdram_freq != ddr_check)
1958 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
1960 mtsdram(SDRAM_SDTR3, sdtr3);
1963 /*-----------------------------------------------------------------------------+
1965 *-----------------------------------------------------------------------------*/
1966 static void program_bxcf(unsigned long *dimm_populated,
1967 unsigned char *iic0_dimm_addr,
1968 unsigned long num_dimm_banks)
1970 unsigned long dimm_num;
1971 unsigned long num_col_addr;
1972 unsigned long num_ranks;
1973 unsigned long num_banks;
1975 unsigned long ind_rank;
1977 unsigned long ind_bank;
1978 unsigned long bank_0_populated;
1980 /*------------------------------------------------------------------
1981 * Set the BxCF regs. First, wipe out the bank config registers.
1982 *-----------------------------------------------------------------*/
1983 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
1984 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1985 mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
1986 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1987 mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
1988 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1989 mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
1990 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1992 mode = SDRAM_BXCF_M_BE_ENABLE;
1994 bank_0_populated = 0;
1996 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1997 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1998 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1999 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2000 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2001 num_ranks = (num_ranks & 0x0F) +1;
2003 num_ranks = num_ranks & 0x0F;
2005 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2007 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2012 switch (num_col_addr) {
2014 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2017 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2020 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2023 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2026 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2029 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2030 (unsigned int)dimm_num);
2031 printf("ERROR: Unsupported value for number of "
2032 "column addresses: %d.\n", (unsigned int)num_col_addr);
2033 printf("Replace the DIMM module with a supported DIMM.\n\n");
2038 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2039 bank_0_populated = 1;
2041 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2042 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
2043 mtdcr(SDRAMC_CFGDATA, mode);
2049 /*------------------------------------------------------------------
2050 * program memory queue.
2051 *-----------------------------------------------------------------*/
2052 static void program_memory_queue(unsigned long *dimm_populated,
2053 unsigned char *iic0_dimm_addr,
2054 unsigned long num_dimm_banks)
2056 unsigned long dimm_num;
2057 unsigned long rank_base_addr;
2058 unsigned long rank_reg;
2059 unsigned long rank_size_bytes;
2060 unsigned long rank_size_id;
2061 unsigned long num_ranks;
2062 unsigned long baseadd_size;
2064 unsigned long bank_0_populated = 0;
2066 /*------------------------------------------------------------------
2067 * Reset the rank_base_address.
2068 *-----------------------------------------------------------------*/
2069 rank_reg = SDRAM_R0BAS;
2071 rank_base_addr = 0x00000000;
2073 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2074 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2075 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2076 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2077 num_ranks = (num_ranks & 0x0F) + 1;
2079 num_ranks = num_ranks & 0x0F;
2081 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2083 /*------------------------------------------------------------------
2085 *-----------------------------------------------------------------*/
2087 rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
2088 switch (rank_size_id) {
2090 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2093 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2096 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2099 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2102 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2105 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2108 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2111 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2112 (unsigned int)dimm_num);
2113 printf("ERROR: Unsupported value for the banksize: %d.\n",
2114 (unsigned int)rank_size_id);
2115 printf("Replace the DIMM module with a supported DIMM.\n\n");
2119 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2120 bank_0_populated = 1;
2122 for (i = 0; i < num_ranks; i++) {
2123 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2124 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2126 rank_base_addr += rank_size_bytes;
2132 /*-----------------------------------------------------------------------------+
2134 *-----------------------------------------------------------------------------*/
2135 static unsigned long is_ecc_enabled(void)
2137 unsigned long dimm_num;
2142 /* loop through all the DIMM slots on the board */
2143 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2144 mfsdram(SDRAM_MCOPT1, val);
2145 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2151 static void blank_string(int size)
2155 for (i=0; i<size; i++)
2157 for (i=0; i<size; i++)
2159 for (i=0; i<size; i++)
2163 #ifdef CONFIG_DDR_ECC
2164 /*-----------------------------------------------------------------------------+
2166 *-----------------------------------------------------------------------------*/
2167 static void program_ecc(unsigned long *dimm_populated,
2168 unsigned char *iic0_dimm_addr,
2169 unsigned long num_dimm_banks,
2170 unsigned long tlb_word2_i_value)
2172 unsigned long mcopt1;
2173 unsigned long mcopt2;
2174 unsigned long mcstat;
2175 unsigned long dimm_num;
2179 /* loop through all the DIMM slots on the board */
2180 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2181 /* If a dimm is installed in a particular slot ... */
2182 if (dimm_populated[dimm_num] != SDRAM_NONE)
2183 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2188 mfsdram(SDRAM_MCOPT1, mcopt1);
2189 mfsdram(SDRAM_MCOPT2, mcopt2);
2191 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2192 /* DDR controller must be enabled and not in self-refresh. */
2193 mfsdram(SDRAM_MCSTAT, mcstat);
2194 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2195 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2196 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2197 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2199 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2206 #ifdef CONFIG_ECC_ERROR_RESET
2208 * Check for ECC errors and reset board upon any error here
2210 * On the Katmai 440SPe eval board, from time to time, the first
2211 * lword write access after DDR2 initializazion with ECC checking
2212 * enabled, leads to an ECC error. I couldn't find a configuration
2213 * without this happening. On my board with the current setup it
2214 * happens about 1 from 10 times.
2216 * The ECC modules used for testing are:
2217 * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2219 * This has to get fixed for the Katmai and tested for the other
2220 * board (440SP/440SPe) that will eventually use this code in the
2225 static void check_ecc(void)
2229 mfsdram(SDRAM_ECCCR, val);
2231 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2232 val, mfdcr(0x4c), mfdcr(0x4e));
2233 printf("ECC error occured, resetting board...\n");
2234 do_reset(NULL, 0, 0, NULL);
2239 static void wait_ddr_idle(void)
2244 mfsdram(SDRAM_MCSTAT, val);
2245 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2248 /*-----------------------------------------------------------------------------+
2250 *-----------------------------------------------------------------------------*/
2251 static void program_ecc_addr(unsigned long start_address,
2252 unsigned long num_bytes,
2253 unsigned long tlb_word2_i_value)
2255 unsigned long current_address;
2256 unsigned long end_address;
2257 unsigned long address_increment;
2258 unsigned long mcopt1;
2259 char str[] = "ECC generation -";
2260 char slash[] = "\\|/-\\|/-";
2264 current_address = start_address;
2265 mfsdram(SDRAM_MCOPT1, mcopt1);
2266 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2267 mtsdram(SDRAM_MCOPT1,
2268 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2274 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2275 /* ECC bit set method for non-cached memory */
2276 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2277 address_increment = 4;
2279 address_increment = 8;
2280 end_address = current_address + num_bytes;
2282 while (current_address < end_address) {
2283 *((unsigned long *)current_address) = 0x00000000;
2284 current_address += address_increment;
2286 if ((loop++ % (2 << 20)) == 0) {
2288 putc(slash[loopi++ % 8]);
2293 /* ECC bit set method for cached memory */
2294 dcbz_area(start_address, num_bytes);
2298 blank_string(strlen(str));
2304 /* clear ECC error repoting registers */
2305 mtsdram(SDRAM_ECCCR, 0xffffffff);
2306 mtdcr(0x4c, 0xffffffff);
2308 mtsdram(SDRAM_MCOPT1,
2309 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2314 #ifdef CONFIG_ECC_ERROR_RESET
2316 * One write to 0 is enough to trigger this ECC error
2317 * (see description above)
2319 out_be32(0, 0x12345678);
2326 /*-----------------------------------------------------------------------------+
2327 * program_DQS_calibration.
2328 *-----------------------------------------------------------------------------*/
2329 static void program_DQS_calibration(unsigned long *dimm_populated,
2330 unsigned char *iic0_dimm_addr,
2331 unsigned long num_dimm_banks)
2335 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2336 mtsdram(SDRAM_RQDC, 0x80000037);
2337 mtsdram(SDRAM_RDCC, 0x40000000);
2338 mtsdram(SDRAM_RFDC, 0x000001DF);
2342 /*------------------------------------------------------------------
2343 * Program RDCC register
2344 * Read sample cycle auto-update enable
2345 *-----------------------------------------------------------------*/
2348 * Modified for the Katmai platform: with some DIMMs, the DDR2
2349 * controller automatically selects the T2 read cycle, but this
2350 * proves unreliable. Go ahead and force the DDR2 controller
2351 * to use the T4 sample and disable the automatic update of the
2354 mfsdram(SDRAM_RDCC, val);
2356 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2357 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2359 /*------------------------------------------------------------------
2360 * Program RQDC register
2361 * Internal DQS delay mechanism enable
2362 *-----------------------------------------------------------------*/
2363 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2365 /*------------------------------------------------------------------
2366 * Program RFDC register
2367 * Set Feedback Fractional Oversample
2368 * Auto-detect read sample cycle enable
2369 *-----------------------------------------------------------------*/
2370 mfsdram(SDRAM_RFDC, val);
2372 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2373 SDRAM_RFDC_RFFD_MASK))
2374 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2375 SDRAM_RFDC_RFFD_ENCODE(0)));
2377 DQS_calibration_process();
2381 static int short_mem_test(void)
2388 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2389 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2390 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2391 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2392 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2393 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2394 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2395 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2396 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2397 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2398 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2399 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2400 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2401 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2402 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2403 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2404 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2407 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2408 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2411 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2412 /* Bank is enabled */
2414 /*------------------------------------------------------------------
2415 * Run the short memory test.
2416 *-----------------------------------------------------------------*/
2417 membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2419 for (i = 0; i < NUMMEMTESTS; i++) {
2420 for (j = 0; j < NUMMEMWORDS; j++) {
2421 membase[j] = test[i][j];
2422 ppcDcbf((u32)&(membase[j]));
2425 for (l=0; l<NUMLOOPS; l++) {
2426 for (j = 0; j < NUMMEMWORDS; j++) {
2427 if (membase[j] != test[i][j]) {
2428 ppcDcbf((u32)&(membase[j]));
2431 ppcDcbf((u32)&(membase[j]));
2436 } /* if bank enabled */
2437 } /* for bxcf_num */
2442 #ifndef HARD_CODED_DQS
2443 /*-----------------------------------------------------------------------------+
2444 * DQS_calibration_process.
2445 *-----------------------------------------------------------------------------*/
2446 static void DQS_calibration_process(void)
2448 unsigned long rfdc_reg;
2450 unsigned long rqdc_reg;
2457 unsigned long begin_rqfd[MAXRANKS];
2458 unsigned long begin_rffd[MAXRANKS];
2459 unsigned long end_rqfd[MAXRANKS];
2460 unsigned long end_rffd[MAXRANKS];
2462 unsigned long dlycal;
2463 unsigned long dly_val;
2464 unsigned long max_pass_length;
2465 unsigned long current_pass_length;
2466 unsigned long current_fail_length;
2467 unsigned long current_start;
2469 unsigned char fail_found;
2470 unsigned char pass_found;
2472 char str[] = "Auto calibration -";
2473 char slash[] = "\\|/-\\|/-";
2476 /*------------------------------------------------------------------
2477 * Test to determine the best read clock delay tuning bits.
2479 * Before the DDR controller can be used, the read clock delay needs to be
2480 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2481 * This value cannot be hardcoded into the program because it changes
2482 * depending on the board's setup and environment.
2483 * To do this, all delay values are tested to see if they
2484 * work or not. By doing this, you get groups of fails with groups of
2485 * passing values. The idea is to find the start and end of a passing
2486 * window and take the center of it to use as the read clock delay.
2488 * A failure has to be seen first so that when we hit a pass, we know
2489 * that it is truely the start of the window. If we get passing values
2490 * to start off with, we don't know if we are at the start of the window.
2492 * The code assumes that a failure will always be found.
2493 * If a failure is not found, there is no easy way to get the middle
2494 * of the passing window. I guess we can pretty much pick any value
2495 * but some values will be better than others. Since the lowest speed
2496 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2497 * from experimentation it is safe to say you will always have a failure.
2498 *-----------------------------------------------------------------*/
2500 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2501 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2506 mfsdram(SDRAM_RQDC, rqdc_reg);
2507 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2508 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2520 window_found = FALSE;
2522 max_pass_length = 0;
2525 current_pass_length = 0;
2526 current_fail_length = 0;
2528 window_found = FALSE;
2533 * get the delay line calibration register value
2535 mfsdram(SDRAM_DLCR, dlycal);
2536 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2538 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2539 mfsdram(SDRAM_RFDC, rfdc_reg);
2540 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2542 /*------------------------------------------------------------------
2543 * Set the timing reg for the test.
2544 *-----------------------------------------------------------------*/
2545 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2547 /*------------------------------------------------------------------
2548 * See if the rffd value passed.
2549 *-----------------------------------------------------------------*/
2550 if (short_mem_test()) {
2551 if (fail_found == TRUE) {
2553 if (current_pass_length == 0)
2554 current_start = rffd;
2556 current_fail_length = 0;
2557 current_pass_length++;
2559 if (current_pass_length > max_pass_length) {
2560 max_pass_length = current_pass_length;
2561 max_start = current_start;
2566 current_pass_length = 0;
2567 current_fail_length++;
2569 if (current_fail_length >= (dly_val >> 2)) {
2570 if (fail_found == FALSE) {
2572 } else if (pass_found == TRUE) {
2573 window_found = TRUE;
2580 /*------------------------------------------------------------------
2581 * Set the average RFFD value
2582 *-----------------------------------------------------------------*/
2583 rffd_average = ((max_start + max_end) >> 1);
2585 if (rffd_average < 0)
2588 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2589 rffd_average = SDRAM_RFDC_RFFD_MAX;
2590 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2591 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2593 max_pass_length = 0;
2596 current_pass_length = 0;
2597 current_fail_length = 0;
2599 window_found = FALSE;
2603 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2604 mfsdram(SDRAM_RQDC, rqdc_reg);
2605 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2607 /*------------------------------------------------------------------
2608 * Set the timing reg for the test.
2609 *-----------------------------------------------------------------*/
2610 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2612 /*------------------------------------------------------------------
2613 * See if the rffd value passed.
2614 *-----------------------------------------------------------------*/
2615 if (short_mem_test()) {
2616 if (fail_found == TRUE) {
2618 if (current_pass_length == 0)
2619 current_start = rqfd;
2621 current_fail_length = 0;
2622 current_pass_length++;
2624 if (current_pass_length > max_pass_length) {
2625 max_pass_length = current_pass_length;
2626 max_start = current_start;
2631 current_pass_length = 0;
2632 current_fail_length++;
2634 if (fail_found == FALSE) {
2636 } else if (pass_found == TRUE) {
2637 window_found = TRUE;
2643 rqfd_average = ((max_start + max_end) >> 1);
2645 /*------------------------------------------------------------------
2646 * Make sure we found the valid read passing window. Halt if not
2647 *-----------------------------------------------------------------*/
2648 if (window_found == FALSE) {
2649 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2651 putc(slash[loopi++ % 8]);
2653 /* try again from with a different RQFD start value */
2655 goto calibration_loop;
2658 printf("\nERROR: Cannot determine a common read delay for the "
2659 "DIMM(s) installed.\n");
2660 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2664 blank_string(strlen(str));
2666 if (rqfd_average < 0)
2669 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2670 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2673 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2674 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2676 mfsdram(SDRAM_DLCR, val);
2677 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2678 mfsdram(SDRAM_RQDC, val);
2679 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2680 mfsdram(SDRAM_RFDC, val);
2681 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2683 #else /* calibration test with hardvalues */
2684 /*-----------------------------------------------------------------------------+
2685 * DQS_calibration_process.
2686 *-----------------------------------------------------------------------------*/
2687 static void test(void)
2689 unsigned long dimm_num;
2690 unsigned long ecc_temp;
2692 unsigned long *membase;
2693 unsigned long bxcf[MAXRANKS];
2696 char begin_found[MAXDIMMS];
2697 char end_found[MAXDIMMS];
2698 char search_end[MAXDIMMS];
2699 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2700 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2701 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2702 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2703 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2704 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2705 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2706 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2707 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2708 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2709 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2710 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2711 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2712 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2713 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2714 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2715 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2717 /*------------------------------------------------------------------
2718 * Test to determine the best read clock delay tuning bits.
2720 * Before the DDR controller can be used, the read clock delay needs to be
2721 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2722 * This value cannot be hardcoded into the program because it changes
2723 * depending on the board's setup and environment.
2724 * To do this, all delay values are tested to see if they
2725 * work or not. By doing this, you get groups of fails with groups of
2726 * passing values. The idea is to find the start and end of a passing
2727 * window and take the center of it to use as the read clock delay.
2729 * A failure has to be seen first so that when we hit a pass, we know
2730 * that it is truely the start of the window. If we get passing values
2731 * to start off with, we don't know if we are at the start of the window.
2733 * The code assumes that a failure will always be found.
2734 * If a failure is not found, there is no easy way to get the middle
2735 * of the passing window. I guess we can pretty much pick any value
2736 * but some values will be better than others. Since the lowest speed
2737 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2738 * from experimentation it is safe to say you will always have a failure.
2739 *-----------------------------------------------------------------*/
2740 mfsdram(SDRAM_MCOPT1, ecc_temp);
2741 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2742 mfsdram(SDRAM_MCOPT1, val);
2743 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2744 SDRAM_MCOPT1_MCHK_NON);
2746 window_found = FALSE;
2747 begin_found[0] = FALSE;
2748 end_found[0] = FALSE;
2749 search_end[0] = FALSE;
2750 begin_found[1] = FALSE;
2751 end_found[1] = FALSE;
2752 search_end[1] = FALSE;
2754 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2755 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2758 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2760 /* Bank is enabled */
2762 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2764 /*------------------------------------------------------------------
2765 * Run the short memory test.
2766 *-----------------------------------------------------------------*/
2767 for (i = 0; i < NUMMEMTESTS; i++) {
2768 for (j = 0; j < NUMMEMWORDS; j++) {
2769 membase[j] = test[i][j];
2770 ppcDcbf((u32)&(membase[j]));
2773 for (j = 0; j < NUMMEMWORDS; j++) {
2774 if (membase[j] != test[i][j]) {
2775 ppcDcbf((u32)&(membase[j]));
2778 ppcDcbf((u32)&(membase[j]));
2781 if (j < NUMMEMWORDS)
2785 /*------------------------------------------------------------------
2786 * See if the rffd value passed.
2787 *-----------------------------------------------------------------*/
2788 if (i < NUMMEMTESTS) {
2789 if ((end_found[dimm_num] == FALSE) &&
2790 (search_end[dimm_num] == TRUE)) {
2791 end_found[dimm_num] = TRUE;
2793 if ((end_found[0] == TRUE) &&
2794 (end_found[1] == TRUE))
2797 if (begin_found[dimm_num] == FALSE) {
2798 begin_found[dimm_num] = TRUE;
2799 search_end[dimm_num] = TRUE;
2803 begin_found[dimm_num] = TRUE;
2804 end_found[dimm_num] = TRUE;
2808 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2809 window_found = TRUE;
2811 /*------------------------------------------------------------------
2812 * Make sure we found the valid read passing window. Halt if not
2813 *-----------------------------------------------------------------*/
2814 if (window_found == FALSE) {
2815 printf("ERROR: Cannot determine a common read delay for the "
2816 "DIMM(s) installed.\n");
2820 /*------------------------------------------------------------------
2821 * Restore the ECC variable to what it originally was
2822 *-----------------------------------------------------------------*/
2823 mtsdram(SDRAM_MCOPT1,
2824 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2830 static void ppc440sp_sdram_register_dump(void)
2832 unsigned int sdram_reg;
2833 unsigned int sdram_data;
2834 unsigned int dcr_data;
2836 printf("\n Register Dump:\n");
2837 sdram_reg = SDRAM_MCSTAT;
2838 mfsdram(sdram_reg, sdram_data);
2839 printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
2840 sdram_reg = SDRAM_MCOPT1;
2841 mfsdram(sdram_reg, sdram_data);
2842 printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
2843 sdram_reg = SDRAM_MCOPT2;
2844 mfsdram(sdram_reg, sdram_data);
2845 printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
2846 sdram_reg = SDRAM_MODT0;
2847 mfsdram(sdram_reg, sdram_data);
2848 printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
2849 sdram_reg = SDRAM_MODT1;
2850 mfsdram(sdram_reg, sdram_data);
2851 printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
2852 sdram_reg = SDRAM_MODT2;
2853 mfsdram(sdram_reg, sdram_data);
2854 printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
2855 sdram_reg = SDRAM_MODT3;
2856 mfsdram(sdram_reg, sdram_data);
2857 printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
2858 sdram_reg = SDRAM_CODT;
2859 mfsdram(sdram_reg, sdram_data);
2860 printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
2861 sdram_reg = SDRAM_VVPR;
2862 mfsdram(sdram_reg, sdram_data);
2863 printf(" SDRAM_VVPR = 0x%08X", sdram_data);
2864 sdram_reg = SDRAM_OPARS;
2865 mfsdram(sdram_reg, sdram_data);
2866 printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
2868 * OPAR2 is only used as a trigger register.
2869 * No data is contained in this register, and reading or writing
2870 * to is can cause bad things to happen (hangs). Just skip it
2872 * sdram_reg = SDRAM_OPAR2;
2873 * mfsdram(sdram_reg, sdram_data);
2874 * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
2876 printf(" SDRAM_OPART = N/A ");
2877 sdram_reg = SDRAM_RTR;
2878 mfsdram(sdram_reg, sdram_data);
2879 printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
2880 sdram_reg = SDRAM_MB0CF;
2881 mfsdram(sdram_reg, sdram_data);
2882 printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
2883 sdram_reg = SDRAM_MB1CF;
2884 mfsdram(sdram_reg, sdram_data);
2885 printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
2886 sdram_reg = SDRAM_MB2CF;
2887 mfsdram(sdram_reg, sdram_data);
2888 printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
2889 sdram_reg = SDRAM_MB3CF;
2890 mfsdram(sdram_reg, sdram_data);
2891 printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
2892 sdram_reg = SDRAM_INITPLR0;
2893 mfsdram(sdram_reg, sdram_data);
2894 printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
2895 sdram_reg = SDRAM_INITPLR1;
2896 mfsdram(sdram_reg, sdram_data);
2897 printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
2898 sdram_reg = SDRAM_INITPLR2;
2899 mfsdram(sdram_reg, sdram_data);
2900 printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
2901 sdram_reg = SDRAM_INITPLR3;
2902 mfsdram(sdram_reg, sdram_data);
2903 printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
2904 sdram_reg = SDRAM_INITPLR4;
2905 mfsdram(sdram_reg, sdram_data);
2906 printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
2907 sdram_reg = SDRAM_INITPLR5;
2908 mfsdram(sdram_reg, sdram_data);
2909 printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
2910 sdram_reg = SDRAM_INITPLR6;
2911 mfsdram(sdram_reg, sdram_data);
2912 printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
2913 sdram_reg = SDRAM_INITPLR7;
2914 mfsdram(sdram_reg, sdram_data);
2915 printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
2916 sdram_reg = SDRAM_INITPLR8;
2917 mfsdram(sdram_reg, sdram_data);
2918 printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
2919 sdram_reg = SDRAM_INITPLR9;
2920 mfsdram(sdram_reg, sdram_data);
2921 printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
2922 sdram_reg = SDRAM_INITPLR10;
2923 mfsdram(sdram_reg, sdram_data);
2924 printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
2925 sdram_reg = SDRAM_INITPLR11;
2926 mfsdram(sdram_reg, sdram_data);
2927 printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2928 sdram_reg = SDRAM_INITPLR12;
2929 mfsdram(sdram_reg, sdram_data);
2930 printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
2931 sdram_reg = SDRAM_INITPLR13;
2932 mfsdram(sdram_reg, sdram_data);
2933 printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2934 sdram_reg = SDRAM_INITPLR14;
2935 mfsdram(sdram_reg, sdram_data);
2936 printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
2937 sdram_reg = SDRAM_INITPLR15;
2938 mfsdram(sdram_reg, sdram_data);
2939 printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2940 sdram_reg = SDRAM_RQDC;
2941 mfsdram(sdram_reg, sdram_data);
2942 printf(" SDRAM_RQDC = 0x%08X", sdram_data);
2943 sdram_reg = SDRAM_RFDC;
2944 mfsdram(sdram_reg, sdram_data);
2945 printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
2946 sdram_reg = SDRAM_RDCC;
2947 mfsdram(sdram_reg, sdram_data);
2948 printf(" SDRAM_RDCC = 0x%08X", sdram_data);
2949 sdram_reg = SDRAM_DLCR;
2950 mfsdram(sdram_reg, sdram_data);
2951 printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
2952 sdram_reg = SDRAM_CLKTR;
2953 mfsdram(sdram_reg, sdram_data);
2954 printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
2955 sdram_reg = SDRAM_WRDTR;
2956 mfsdram(sdram_reg, sdram_data);
2957 printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
2958 sdram_reg = SDRAM_SDTR1;
2959 mfsdram(sdram_reg, sdram_data);
2960 printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
2961 sdram_reg = SDRAM_SDTR2;
2962 mfsdram(sdram_reg, sdram_data);
2963 printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
2964 sdram_reg = SDRAM_SDTR3;
2965 mfsdram(sdram_reg, sdram_data);
2966 printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
2967 sdram_reg = SDRAM_MMODE;
2968 mfsdram(sdram_reg, sdram_data);
2969 printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
2970 sdram_reg = SDRAM_MEMODE;
2971 mfsdram(sdram_reg, sdram_data);
2972 printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
2973 sdram_reg = SDRAM_ECCCR;
2974 mfsdram(sdram_reg, sdram_data);
2975 printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
2977 dcr_data = mfdcr(SDRAM_R0BAS);
2978 printf(" MQ0_B0BAS = 0x%08X", dcr_data);
2979 dcr_data = mfdcr(SDRAM_R1BAS);
2980 printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
2981 dcr_data = mfdcr(SDRAM_R2BAS);
2982 printf(" MQ2_B0BAS = 0x%08X", dcr_data);
2983 dcr_data = mfdcr(SDRAM_R3BAS);
2984 printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
2987 #endif /* CONFIG_SPD_EEPROM */