3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
39 #include <asm/cache.h>
43 #if defined(CONFIG_440)
44 static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
47 /* ------------------------------------------------------------------------- */
51 #if defined(CONFIG_405GP) || \
52 defined(CONFIG_405CR) || \
53 defined(CONFIG_IOP480) || \
54 defined(CONFIG_440) || \
58 #if defined(CONFIG_405GP) || \
59 defined(CONFIG_405CR) || \
60 defined(CONFIG_IOP480) || \
62 DECLARE_GLOBAL_DATA_PTR;
64 ulong clock = gd->cpu_clk;
68 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
69 PPC405_SYS_INFO sys_info;
73 get_sys_info(&sys_info);
76 puts("IBM PowerPC 405GP");
77 if (pvr == PVR_405GPR_RB) {
83 puts("IBM PowerPC 405CR Rev. ");
86 puts("IBM PowerPC 405EP Rev. ");
115 printf("? (PVR=%08x)", pvr);
119 printf(" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
120 sys_info.freqPLB / 1000000,
121 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
122 sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
124 #if defined(CONFIG_405GP)
125 if (mfdcr(strap) & PSR_PCI_ASYNC_EN)
126 printf(" PCI async ext clock used, ");
128 printf(" PCI sync clock at %lu MHz, ",
129 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
130 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
131 printf("internal PCI arbiter enabled\n");
133 printf("external PCI arbiter enabled\n");
134 #elif defined(CONFIG_405EP)
135 if (mfdcr(cpc0_boot) & CPC0_BOOT_SEP)
136 printf(" IIC Boot EEPROM enabled\n");
138 printf(" IIC Boot EEPROM disabled\n");
139 printf(" PCI async ext clock used, ");
140 if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
141 printf("internal PCI arbiter enabled\n");
143 printf("external PCI arbiter enabled\n");
146 #if defined(CONFIG_405EP)
147 printf(" 16 kB I-Cache 16 kB D-Cache");
149 if ((pvr | 0x00000001) == PVR_405GPR_RB) {
150 printf(" 16 kB I-Cache 16 kB D-Cache");
152 printf(" 16 kB I-Cache 8 kB D-Cache");
155 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
158 printf("PLX IOP480 (PVR=%08x)", pvr);
159 printf(" at %s MHz:", strmhz(buf, clock));
160 printf(" %u kB I-Cache", 4);
161 printf(" %u kB D-Cache", 2);
164 #if defined(CONFIG_440)
165 puts("IBM PowerPC 440 Rev. ");
170 /* See errata 1.12: CHIP_4 */
171 if( ( mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0) )
172 ||( mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1) ) ){
173 puts("\n\t CPC0_SYSx DCRs corrupted. Resetting chip ...\n");
174 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
175 do_chip_reset( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) );
182 printf("UNKNOWN (PVR=%08x)", pvr);
193 /* ------------------------------------------------------------------------- */
195 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
198 * Initiate system reset in debug control register DBCR
200 __asm__ __volatile__("lis 3, 0x3000" ::: "r3");
201 #if defined(CONFIG_440)
202 __asm__ __volatile__("mtspr 0x134, 3");
204 __asm__ __volatile__("mtspr 0x3f2, 3");
209 #if defined(CONFIG_440)
211 int do_chip_reset( unsigned long sys0, unsigned long sys1 )
213 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
216 mtdcr( cntrl0, mfdcr(cntrl0) | 0x80000000 ); /* Set SWE */
217 mtdcr( cpc0_sys0, sys0 );
218 mtdcr( cpc0_sys1, sys1 );
219 mtdcr( cntrl0, mfdcr(cntrl0) & ~0x80000000 ); /* Clr SWE */
220 mtspr( dbcr0, 0x20000000); /* Reset the chip */
228 * Get timebase clock frequency
230 unsigned long get_tbclk (void)
232 #if defined(CONFIG_440)
236 get_sys_info(&sys_info);
237 return (sys_info.freqProcessor);
239 #elif defined(CONFIG_405GP) || \
240 defined(CONFIG_405CR) || \
241 defined(CONFIG_405) || \
242 defined(CONFIG_405EP)
244 PPC405_SYS_INFO sys_info;
246 get_sys_info(&sys_info);
247 return (sys_info.freqProcessor);
249 #elif defined(CONFIG_IOP480)
255 # error get_tbclk() not implemented
262 #if defined(CONFIG_WATCHDOG)
266 int re_enable = disable_interrupts();
267 reset_4xx_watchdog();
268 if (re_enable) enable_interrupts();
272 reset_4xx_watchdog(void)
277 mtspr(tsr, 0x40000000);
279 #endif /* CONFIG_WATCHDOG */