2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 #if !defined(CONFIG_405)
41 DECLARE_GLOBAL_DATA_PTR;
44 #if defined(CONFIG_BOARD_RESET)
45 void board_reset(void);
48 #if defined(CONFIG_440)
49 #define FREQ_EBC (sys_info.freqEPB)
50 #elif defined(CONFIG_405EZ)
51 #define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
52 sys_info.pllExtBusDiv)
54 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
57 #if defined(CONFIG_405GP) || \
58 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
59 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
63 int pci_async_enabled(void)
65 #if defined(CONFIG_405GP)
66 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
69 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
70 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
73 mfsdr(sdr_sdstp1, val);
74 return (val & SDR0_SDSTP1_PAME_MASK);
79 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
80 int pci_arbiter_enabled(void)
82 #if defined(CONFIG_405GP)
83 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
86 #if defined(CONFIG_405EP)
87 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
90 #if defined(CONFIG_440GP)
91 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
94 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
98 return (val & 0x80000000);
100 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
101 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
104 mfsdr(sdr_pci0, val);
105 return (val & 0x80000000);
110 #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
111 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
112 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
113 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
117 int i2c_bootrom_enabled(void)
119 #if defined(CONFIG_405EP)
120 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
124 mfsdr(sdr_sdcs, val);
125 return (val & SDR0_SDCS_SDD);
130 #if defined(CONFIG_440GX)
131 #define SDR0_PINSTP_SHIFT 29
132 static char *bootstrap_str[] = {
142 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
145 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
146 #define SDR0_PINSTP_SHIFT 30
147 static char *bootstrap_str[] = {
153 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
156 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
157 #define SDR0_PINSTP_SHIFT 29
158 static char *bootstrap_str[] = {
168 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
171 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
172 #define SDR0_PINSTP_SHIFT 29
173 static char *bootstrap_str[] = {
183 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
186 #if defined(CONFIG_405EZ)
187 #define SDR0_PINSTP_SHIFT 28
188 static char *bootstrap_str[] = {
191 "NAND (512 page, 4 addr cycle)",
195 "NAND (2K page, 5 addr cycle)",
199 "NAND (2K page, 4 addr cycle)",
201 "NAND (512 page, 3 addr cycle)",
206 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
207 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
210 #if defined(SDR0_PINSTP_SHIFT)
211 static int bootstrap_option(void)
215 mfsdr(SDR_PINSTP, val);
216 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
218 #endif /* SDR0_PINSTP_SHIFT */
221 #if defined(CONFIG_440)
222 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
228 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
229 uint pvr = get_pvr();
230 ulong clock = gd->cpu_clk;
233 #if !defined(CONFIG_IOP480)
234 char addstr[64] = "";
239 get_sys_info(&sys_info);
241 puts("AMCC PowerPC 4");
243 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
244 defined(CONFIG_405EP) || defined(CONFIG_405EZ)
247 #if defined(CONFIG_440)
265 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
279 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
296 #if defined(CONFIG_440)
299 /* See errata 1.12: CHIP_4 */
300 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
301 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
302 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
303 "Resetting chip ...\n");
304 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
305 do_chip_reset ( mfdcr(cpc0_strp0),
335 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
339 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
342 #endif /* CONFIG_440EP */
345 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
349 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
352 #endif /* CONFIG_440GR */
353 #endif /* CONFIG_440 */
356 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
358 strcpy(addstr, "Security/Kasumi support");
361 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
363 strcpy(addstr, "No Security/Kasumi support");
365 #endif /* CONFIG_440EPX */
368 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
370 strcpy(addstr, "Security/Kasumi support");
373 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
375 strcpy(addstr, "No Security/Kasumi support");
377 #endif /* CONFIG_440GRX */
379 case PVR_440SP_6_RAB:
381 strcpy(addstr, "RAID 6 support");
386 strcpy(addstr, "No RAID 6 support");
391 strcpy(addstr, "RAID 6 support");
396 strcpy(addstr, "No RAID 6 support");
399 case PVR_440SPe_6_RA:
401 strcpy(addstr, "RAID 6 support");
406 strcpy(addstr, "No RAID 6 support");
409 case PVR_440SPe_6_RB:
411 strcpy(addstr, "RAID 6 support");
416 strcpy(addstr, "No RAID 6 support");
420 printf (" UNKNOWN (PVR=%08x)", pvr);
424 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
425 sys_info.freqPLB / 1000000,
426 get_OPB_freq() / 1000000,
430 printf(" %s\n", addstr);
432 #if defined(I2C_BOOTROM)
433 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
434 #endif /* I2C_BOOTROM */
435 #if defined(SDR0_PINSTP_SHIFT)
436 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
437 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
438 #endif /* SDR0_PINSTP_SHIFT */
440 #if defined(CONFIG_PCI)
441 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
444 #if defined(PCI_ASYNC)
445 if (pci_async_enabled()) {
446 printf (", PCI async ext clock used");
448 printf (", PCI sync clock at %lu MHz",
449 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
453 #if defined(CONFIG_PCI)
457 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
458 printf (" 16 kB I-Cache 16 kB D-Cache");
459 #elif defined(CONFIG_440)
460 printf (" 32 kB I-Cache 32 kB D-Cache");
462 printf (" 16 kB I-Cache %d kB D-Cache",
463 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
465 #endif /* !defined(CONFIG_IOP480) */
467 #if defined(CONFIG_IOP480)
468 printf ("PLX IOP480 (PVR=%08x)", pvr);
469 printf (" at %s MHz:", strmhz(buf, clock));
470 printf (" %u kB I-Cache", 4);
471 printf (" %u kB D-Cache", 2);
474 #endif /* !defined(CONFIG_405) */
481 #if defined (CONFIG_440SPE)
482 int ppc440spe_revB() {
486 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
493 /* ------------------------------------------------------------------------- */
495 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
497 #if defined(CONFIG_BOARD_RESET)
500 #if defined(CFG_4xx_RESET_TYPE)
501 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
504 * Initiate system reset in debug control register DBCR
506 mtspr(dbcr0, 0x30000000);
507 #endif /* defined(CFG_4xx_RESET_TYPE) */
508 #endif /* defined(CONFIG_BOARD_RESET) */
513 #if defined(CONFIG_440)
514 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
516 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
519 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
520 mtdcr (cpc0_sys0, sys0);
521 mtdcr (cpc0_sys1, sys1);
522 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
523 mtspr (dbcr0, 0x20000000); /* Reset the chip */
531 * Get timebase clock frequency
533 unsigned long get_tbclk (void)
535 #if !defined(CONFIG_IOP480)
538 get_sys_info(&sys_info);
539 return (sys_info.freqProcessor);
547 #if defined(CONFIG_WATCHDOG)
551 int re_enable = disable_interrupts();
552 reset_4xx_watchdog();
553 if (re_enable) enable_interrupts();
557 reset_4xx_watchdog(void)
562 mtspr(tsr, 0x40000000);
564 #endif /* CONFIG_WATCHDOG */