2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 #if !defined(CONFIG_405)
41 DECLARE_GLOBAL_DATA_PTR;
44 #if defined(CONFIG_BOARD_RESET)
45 void board_reset(void);
48 #if defined(CONFIG_440)
49 #define FREQ_EBC (sys_info.freqEPB)
51 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
54 #if defined(CONFIG_405GP) || \
55 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
56 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
60 int pci_async_enabled(void)
62 #if defined(CONFIG_405GP)
63 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
66 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
67 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
70 mfsdr(sdr_sdstp1, val);
71 return (val & SDR0_SDSTP1_PAME_MASK);
76 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
77 int pci_arbiter_enabled(void)
79 #if defined(CONFIG_405GP)
80 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
83 #if defined(CONFIG_405EP)
84 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
87 #if defined(CONFIG_440GP)
88 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
91 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
95 return (val & 0x80000000);
97 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
98 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
101 mfsdr(sdr_pci0, val);
102 return (val & 0x80000000);
107 #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
108 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
109 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
110 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
114 int i2c_bootrom_enabled(void)
116 #if defined(CONFIG_405EP)
117 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
121 mfsdr(sdr_sdcs, val);
122 return (val & SDR0_SDCS_SDD);
126 #if defined(CONFIG_440GX)
127 #define SDR0_PINSTP_SHIFT 29
128 static char *bootstrap_str[] = {
140 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
141 #define SDR0_PINSTP_SHIFT 30
142 static char *bootstrap_str[] = {
150 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
151 #define SDR0_PINSTP_SHIFT 29
152 static char *bootstrap_str[] = {
164 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
165 #define SDR0_PINSTP_SHIFT 29
166 static char *bootstrap_str[] = {
178 #if defined(SDR0_PINSTP_SHIFT)
179 static int bootstrap_option(void)
183 mfsdr(sdr_pinstp, val);
184 return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
186 #endif /* SDR0_PINSTP_SHIFT */
190 #if defined(CONFIG_440)
191 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
197 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
198 uint pvr = get_pvr();
199 ulong clock = gd->cpu_clk;
202 #if !defined(CONFIG_IOP480)
203 char addstr[64] = "";
208 get_sys_info(&sys_info);
210 puts("AMCC PowerPC 4");
212 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
215 #if defined(CONFIG_440)
233 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
247 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
260 #if defined(CONFIG_440)
263 /* See errata 1.12: CHIP_4 */
264 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
265 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
266 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
267 "Resetting chip ...\n");
268 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
269 do_chip_reset ( mfdcr(cpc0_strp0),
299 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
303 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
306 #endif /* CONFIG_440EP */
309 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
313 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
316 #endif /* CONFIG_440GR */
317 #endif /* CONFIG_440 */
320 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
322 strcpy(addstr, "Security/Kasumi support");
325 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
327 strcpy(addstr, "No Security/Kasumi support");
329 #endif /* CONFIG_440EPX */
332 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
334 strcpy(addstr, "Security/Kasumi support");
337 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
339 strcpy(addstr, "No Security/Kasumi support");
341 #endif /* CONFIG_440GRX */
343 case PVR_440SP_6_RAB:
345 strcpy(addstr, "RAID 6 support");
350 strcpy(addstr, "No RAID 6 support");
355 strcpy(addstr, "RAID 6 support");
360 strcpy(addstr, "No RAID 6 support");
363 case PVR_440SPe_6_RA:
365 strcpy(addstr, "RAID 6 support");
370 strcpy(addstr, "No RAID 6 support");
373 case PVR_440SPe_6_RB:
375 strcpy(addstr, "RAID 6 support");
380 strcpy(addstr, "No RAID 6 support");
384 printf (" UNKNOWN (PVR=%08x)", pvr);
388 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
389 sys_info.freqPLB / 1000000,
390 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
394 printf(" %s\n", addstr);
396 #if defined(I2C_BOOTROM)
397 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
398 #if defined(SDR0_PINSTP_SHIFT)
399 printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
400 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
401 #endif /* SDR0_PINSTP_SHIFT */
402 #endif /* I2C_BOOTROM */
404 #if defined(CONFIG_PCI)
405 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
408 #if defined(PCI_ASYNC)
409 if (pci_async_enabled()) {
410 printf (", PCI async ext clock used");
412 printf (", PCI sync clock at %lu MHz",
413 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
417 #if defined(CONFIG_PCI)
421 #if defined(CONFIG_405EP)
422 printf (" 16 kB I-Cache 16 kB D-Cache");
423 #elif defined(CONFIG_440)
424 printf (" 32 kB I-Cache 32 kB D-Cache");
426 printf (" 16 kB I-Cache %d kB D-Cache",
427 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
429 #endif /* !defined(CONFIG_IOP480) */
431 #if defined(CONFIG_IOP480)
432 printf ("PLX IOP480 (PVR=%08x)", pvr);
433 printf (" at %s MHz:", strmhz(buf, clock));
434 printf (" %u kB I-Cache", 4);
435 printf (" %u kB D-Cache", 2);
438 #endif /* !defined(CONFIG_405) */
445 #if defined (CONFIG_440SPE)
446 int ppc440spe_revB() {
450 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
457 /* ------------------------------------------------------------------------- */
459 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
461 #if defined(CONFIG_BOARD_RESET)
464 #if defined(CFG_4xx_RESET_TYPE)
465 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
468 * Initiate system reset in debug control register DBCR
470 mtspr(dbcr0, 0x30000000);
471 #endif /* defined(CFG_4xx_RESET_TYPE) */
472 #endif /* defined(CONFIG_BOARD_RESET) */
477 #if defined(CONFIG_440)
478 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
480 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
483 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
484 mtdcr (cpc0_sys0, sys0);
485 mtdcr (cpc0_sys1, sys1);
486 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
487 mtspr (dbcr0, 0x20000000); /* Reset the chip */
495 * Get timebase clock frequency
497 unsigned long get_tbclk (void)
499 #if !defined(CONFIG_IOP480)
502 get_sys_info(&sys_info);
503 return (sys_info.freqProcessor);
511 #if defined(CONFIG_WATCHDOG)
515 int re_enable = disable_interrupts();
516 reset_4xx_watchdog();
517 if (re_enable) enable_interrupts();
521 reset_4xx_watchdog(void)
526 mtspr(tsr, 0x40000000);
528 #endif /* CONFIG_WATCHDOG */