1 /*-----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
25 | Function: This module has utilities for accessing the MII PHY through
32 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 05-May-99 Created MKW
35 | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
36 | better match OPB speed. Also modified delay times. JWB
37 | 29-Jul-99 Added Full duplex support MKW
38 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
39 | 19-Jul-00 Ported to esd cpci405 sr
40 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
41 | <travis.sawyer@sandburst.com>
43 +-----------------------------------------------------------------------------*/
46 #include <asm/processor.h>
47 #include <ppc_asm.tmpl>
49 #include <ppc4xx_enet.h>
54 /***********************************************************/
55 /* Dump out to the screen PHY regs */
56 /***********************************************************/
58 void miiphy_dump (unsigned char addr)
64 for (i = 0; i < 0x1A; i++) {
65 if (miiphy_read (addr, i, &data)) {
66 printf ("read error for reg %lx\n", i);
69 printf ("Phy reg %lx ==> %4x\n", i, data);
71 /* jump to the next set of regs */
79 /***********************************************************/
80 /* (Re)start autonegotiation */
81 /***********************************************************/
82 int phy_setup_aneg (unsigned char addr)
84 unsigned short ctl, adv;
86 /* Setup standard advertise */
87 miiphy_read (addr, PHY_ANAR, &adv);
88 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
89 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
91 miiphy_write (addr, PHY_ANAR, adv);
93 /* Start/Restart aneg */
94 miiphy_read (addr, PHY_BMCR, &ctl);
95 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
96 miiphy_write (addr, PHY_BMCR, ctl);
102 /***********************************************************/
103 /* read a phy reg and return the value with a rc */
104 /***********************************************************/
105 unsigned int miiphy_getemac_offset (void)
107 #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
109 unsigned long eoffset;
111 /* Need to find out which mdi port we're using */
112 zmii = in32 (ZMII_FER);
114 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
117 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
120 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
123 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
127 /* None of the mdi ports are enabled! */
129 zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
130 out32 (ZMII_FER, zmii);
132 /* need to soft reset port 0 */
133 zmii = in32 (EMAC_M0);
134 zmii |= EMAC_M0_SRST;
135 out32 (EMAC_M0, zmii);
145 int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
147 unsigned long sta_reg; /* STA scratch area */
149 unsigned long emac_reg;
152 emac_reg = miiphy_getemac_offset ();
153 /* see if it is ready for 1000 nsec */
156 /* see if it is ready for sec */
157 while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
161 printf ("read err 1\n");
167 sta_reg = reg; /* reg address */
168 /* set clock (50Mhz) and read flags */
169 #if defined(CONFIG_440GX)
170 sta_reg |= EMAC_STACR_READ;
172 sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
175 #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
176 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
178 sta_reg = sta_reg | (addr << 5); /* Phy address */
180 out32 (EMAC_STACR + emac_reg, sta_reg);
181 #if 0 /* test-only */
182 printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
185 sta_reg = in32 (EMAC_STACR + emac_reg);
187 while ((sta_reg & EMAC_STACR_OC) == 0) {
193 sta_reg = in32 (EMAC_STACR + emac_reg);
195 if ((sta_reg & EMAC_STACR_PHYE) != 0) {
199 *value = *(short *) (&sta_reg);
206 /***********************************************************/
207 /* write a phy reg and return the value with a rc */
208 /***********************************************************/
210 int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
212 unsigned long sta_reg; /* STA scratch area */
214 unsigned long emac_reg;
216 emac_reg = miiphy_getemac_offset ();
217 /* see if it is ready for 1000 nsec */
220 while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
227 sta_reg = reg; /* reg address */
228 /* set clock (50Mhz) and read flags */
229 #if defined(CONFIG_440GX)
230 sta_reg |= EMAC_STACR_WRITE;
232 sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
235 #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
236 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
238 sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
239 memcpy (&sta_reg, &value, 2); /* put in data */
241 out32 (EMAC_STACR + emac_reg, sta_reg);
243 /* wait for completion */
245 sta_reg = in32 (EMAC_STACR + emac_reg);
246 while ((sta_reg & EMAC_STACR_OC) == 0) {
251 sta_reg = in32 (EMAC_STACR + emac_reg);
254 if ((sta_reg & EMAC_STACR_PHYE) != 0)