2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * DAVE Srl <www.dave-tech.it>
8 * (C) Copyright 2002-2004
9 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/processor.h>
36 #ifdef CONFIG_SDRAM_BANK0
40 #ifndef CFG_SDRAM_TABLE
41 sdram_conf_t mb0cf[] = {
42 {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
43 {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
44 {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
45 {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
46 {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
49 sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
52 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
55 static ulong ns2clks(ulong ns)
57 ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
59 return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
61 #endif /* CFG_SDRAM_CASL */
63 static ulong compute_sdtr1(ulong speed)
70 if (CFG_SDRAM_CASL < 2)
71 sdtr1 |= (1 << SDRAM0_TR_CASL);
73 if (CFG_SDRAM_CASL > 4)
74 sdtr1 |= (3 << SDRAM0_TR_CASL);
76 sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL);
79 tmp = ns2clks(CFG_SDRAM_PTA);
80 if ((tmp >= 2) && (tmp <= 4))
81 sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
83 sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
86 tmp = ns2clks(CFG_SDRAM_CTP);
87 if ((tmp >= 2) && (tmp <= 4))
88 sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
90 sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
93 tmp = ns2clks(CFG_SDRAM_LDF);
94 if ((tmp >= 2) && (tmp <= 4))
95 sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
97 sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
100 tmp = ns2clks(CFG_SDRAM_RFTA);
101 if ((tmp >= 4) && (tmp <= 10))
102 sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
104 sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
107 tmp = ns2clks(CFG_SDRAM_RCD);
108 if ((tmp >= 2) && (tmp <= 4))
109 sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
111 sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
114 #else /* CFG_SDRAM_CASL */
116 * If no values are configured in the board config file
117 * use the default values, which seem to be ok for most
121 * For new board ports we strongly recommend to define the
122 * correct values for the used SDRAM chips in your board
123 * config file (see PPChameleonEVB.h)
125 if (speed > 100000000) {
132 * default: 100 MHz SDRAM
136 #endif /* CFG_SDRAM_CASL */
139 /* refresh is expressed in ms */
140 static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
142 #ifdef CFG_SDRAM_CASL
145 tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
148 return ((tmp & 0x00003FF8) << 16);
149 #else /* CFG_SDRAM_CASL */
150 if (speed > 100000000) {
157 * default: 100 MHz SDRAM
161 #endif /* CFG_SDRAM_CASL */
165 * Autodetect onboard SDRAM on 405 platforms
167 void sdram_init(void)
174 * Determine SDRAM speed
176 speed = get_bus_freq(0); /* parameter not used on ppc4xx */
179 * sdtr1 (register SDRAM0_TR) must take into account timings listed
180 * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
181 * account actual SDRAM size. So we can set up sdtr1 according to what
182 * is specified in board configuration file while rtr dependds on SDRAM
183 * size we are assuming before detection.
185 sdtr1 = compute_sdtr1(speed);
187 for (i=0; i<N_MB0CF; i++) {
189 * Disable memory controller.
191 mtsdram(mem_mcopt1, 0x00000000);
194 * Set MB0CF for bank 0.
196 mtsdram(mem_mb0cf, mb0cf[i].reg);
197 mtsdram(mem_sdtr1, sdtr1);
198 mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
203 * Set memory controller options reg, MCOPT1.
204 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
207 mtsdram(mem_mcopt1, 0x80800000);
211 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
213 * OK, size detected. Enable second bank if
214 * defined (assumes same type as bank 0)
216 #ifdef CONFIG_SDRAM_BANK1
217 u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
219 mtsdram(mem_mcopt1, 0x00000000);
220 mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
221 mtsdram(mem_mcopt1, 0x80800000);
225 * Check if 2nd bank is really available.
226 * If the size not equal to the size of the first
227 * bank, then disable the 2nd bank completely.
229 if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
231 mtsdram(mem_mb1cf, 0);
232 mtsdram(mem_mcopt1, 0);
240 #else /* CONFIG_440 */
243 * Define some default values. Those can be overwritten in the
247 #ifndef CFG_SDRAM_TABLE
248 sdram_conf_t mb0cf[] = {
249 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
250 {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
253 sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
256 #ifndef CFG_SDRAM0_TR0
257 #define CFG_SDRAM0_TR0 0x41094012
260 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
265 static void sdram_tr1_set(int ram_address, int* tr1_value)
269 volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
270 int first_good = -1, last_bad = 0x1ff;
272 unsigned long test[NUM_TRIES] = {
273 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
274 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
275 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
276 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
277 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
278 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
279 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
280 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
281 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
282 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
283 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
284 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
285 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
286 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
287 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
288 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
290 /* go through all possible SDRAM0_TR1[RDCT] values */
291 for (i=0; i<=0x1ff; i++) {
292 /* set the current value for TR1 */
293 mtsdram(mem_tr1, (0x80800800 | i));
296 for (j=0; j<NUM_TRIES; j++) {
297 ram_pointer[j] = test[j];
299 /* clear any cache at ram location */
300 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
303 /* read values back */
304 for (j=0; j<NUM_TRIES; j++) {
305 for (k=0; k<NUM_READS; k++) {
306 /* clear any cache at ram location */
307 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
309 if (ram_pointer[j] != test[j])
318 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
319 if (j == NUM_TRIES) {
320 if (first_good == -1)
321 first_good = i; /* found beginning of window */
322 } else { /* bad read */
323 /* if we have not had a good read then don't care */
324 if (first_good != -1) {
325 /* first failure after a good read */
332 /* return the current value for TR1 */
333 *tr1_value = (first_good + last_bad) / 2;
337 * Autodetect onboard DDR SDRAM on 440 platforms
339 * NOTE: Some of the hardcoded values are hardware dependant,
340 * so this should be extended for other future boards
341 * using this routine!
343 long int initdram(int board_type)
348 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
349 defined(CONFIG_440GR) || defined(CONFIG_440SP)
351 * Soft-reset SDRAM controller.
353 mtsdr(sdr_srst, SDR0_SRST_DMC);
354 mtsdr(sdr_srst, 0x00000000);
357 for (i=0; i<N_MB0CF; i++) {
359 * Disable memory controller.
361 mtsdram(mem_cfg0, 0x00000000);
366 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
367 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
368 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
369 mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
370 mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
373 * Following for CAS Latency = 2.5 @ 133 MHz PLB
375 mtsdram(mem_b0cr, mb0cf[i].reg);
376 mtsdram(mem_tr0, CFG_SDRAM0_TR0);
377 mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
378 mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
379 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
380 udelay(400); /* Delay 200 usecs (min) */
383 * Enable the controller, then wait for DCEN to complete
385 mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */
388 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
390 * Optimize TR1 to current hardware environment
392 sdram_tr1_set(0x00000000, &tr1_bank1);
393 mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
395 #ifdef CONFIG_SDRAM_ECC
396 ecc_init(0, mb0cf[i].size);
400 * OK, size detected -> all done
402 return mb0cf[i].size;
406 return 0; /* nothing found ! */
409 #endif /* CONFIG_440 */
411 #endif /* CONFIG_SDRAM_BANK0 */