2 * (C) Copyright 2002-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
29 #ifdef CONFIG_SDRAM_BANK0
32 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
40 typedef struct sdram_conf_s sdram_conf_t;
42 sdram_conf_t mb0cf[] = {
43 {(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
44 {(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
45 {(32 << 20), 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
46 {(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
47 {(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
49 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
59 * Support for 100MHz and 133MHz SDRAM
61 if (get_bus_freq(0) > 100000000) {
69 * default: 100 MHz SDRAM
75 for (i=0; i<N_MB0CF; i++) {
77 * Disable memory controller.
79 mtsdram0(mem_mcopt1, 0x00000000);
82 * Set MB0CF for bank 0.
84 mtsdram0(mem_mb0cf, mb0cf[i].reg);
85 mtsdram0(mem_sdtr1, sdtr1);
86 mtsdram0(mem_rtr, rtr);
91 * Set memory controller options reg, MCOPT1.
92 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
95 mtsdram0(mem_mcopt1, 0x80800000);
99 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
101 * OK, size detected -> all done
108 #endif /* CONFIG_SDRAM_BANK0 */