3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /*------------------------------------------------------------------------------+ */
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
43 /*------------------------------------------------------------------------------- */
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
50 #include <asm/processor.h>
54 #ifdef CONFIG_SERIAL_MULTI
58 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
62 DECLARE_GLOBAL_DATA_PTR;
64 /*****************************************************************************/
67 #define SPU_BASE 0x40000000
69 #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
70 #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
71 #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
72 #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
73 #define spu_BRateDivh 0x10 /* Baud rate divisor high */
74 #define spu_BRateDivl 0x14 /* Baud rate divisor low */
75 #define spu_CtlReg 0x18 /* Control Register */
76 #define spu_RxCmd 0x1c /* Rx Command Register */
77 #define spu_TxCmd 0x20 /* Tx Command Register */
78 #define spu_RxBuff 0x24 /* Rx data buffer */
79 #define spu_TxBuff 0x24 /* Tx data buffer */
81 /*-----------------------------------------------------------------------------+
82 | Line Status Register.
83 +-----------------------------------------------------------------------------*/
84 #define asyncLSRport1 0x40000000
85 #define asyncLSRport1set 0x40000004
86 #define asyncLSRDataReady 0x80
87 #define asyncLSRFramingError 0x40
88 #define asyncLSROverrunError 0x20
89 #define asyncLSRParityError 0x10
90 #define asyncLSRBreakInterrupt 0x08
91 #define asyncLSRTxHoldEmpty 0x04
92 #define asyncLSRTxShiftEmpty 0x02
94 /*-----------------------------------------------------------------------------+
95 | Handshake Status Register.
96 +-----------------------------------------------------------------------------*/
97 #define asyncHSRport1 0x40000008
98 #define asyncHSRport1set 0x4000000c
99 #define asyncHSRDsr 0x80
100 #define asyncLSRCts 0x40
102 /*-----------------------------------------------------------------------------+
104 +-----------------------------------------------------------------------------*/
105 #define asyncCRport1 0x40000018
106 #define asyncCRNormal 0x00
107 #define asyncCRLoopback 0x40
108 #define asyncCRAutoEcho 0x80
109 #define asyncCRDtr 0x20
110 #define asyncCRRts 0x10
111 #define asyncCRWordLength7 0x00
112 #define asyncCRWordLength8 0x08
113 #define asyncCRParityDisable 0x00
114 #define asyncCRParityEnable 0x04
115 #define asyncCREvenParity 0x00
116 #define asyncCROddParity 0x02
117 #define asyncCRStopBitsOne 0x00
118 #define asyncCRStopBitsTwo 0x01
119 #define asyncCRDisableDtrRts 0x00
121 /*-----------------------------------------------------------------------------+
122 | Receiver Command Register.
123 +-----------------------------------------------------------------------------*/
124 #define asyncRCRport1 0x4000001c
125 #define asyncRCRDisable 0x00
126 #define asyncRCREnable 0x80
127 #define asyncRCRIntDisable 0x00
128 #define asyncRCRIntEnabled 0x20
129 #define asyncRCRDMACh2 0x40
130 #define asyncRCRDMACh3 0x60
131 #define asyncRCRErrorInt 0x10
132 #define asyncRCRPauseEnable 0x08
134 /*-----------------------------------------------------------------------------+
135 | Transmitter Command Register.
136 +-----------------------------------------------------------------------------*/
137 #define asyncTCRport1 0x40000020
138 #define asyncTCRDisable 0x00
139 #define asyncTCREnable 0x80
140 #define asyncTCRIntDisable 0x00
141 #define asyncTCRIntEnabled 0x20
142 #define asyncTCRDMACh2 0x40
143 #define asyncTCRDMACh3 0x60
144 #define asyncTCRTxEmpty 0x10
145 #define asyncTCRErrorInt 0x08
146 #define asyncTCRStopPause 0x04
147 #define asyncTCRBreakGen 0x02
149 /*-----------------------------------------------------------------------------+
150 | Miscellanies defines.
151 +-----------------------------------------------------------------------------*/
152 #define asyncTxBufferport1 0x40000024
153 #define asyncRxBufferport1 0x40000024
154 #define asyncDLABLsbport1 0x40000014
155 #define asyncDLABMsbport1 0x40000010
156 #define asyncXOFFchar 0x13
157 #define asyncXONchar 0x11
160 * Minimal serial functions needed to use one of the SMC ports
161 * as serial console interface.
164 int serial_init (void)
167 unsigned short br_reg;
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
186 void serial_setbrg (void)
188 unsigned short br_reg;
190 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
192 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
193 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
196 void serial_putc (const char c)
201 /* load status from handshake register */
202 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
203 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
205 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
207 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
208 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
209 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
213 void serial_puts (const char *s)
222 unsigned char status = 0;
225 status = in8 (asyncLSRport1);
226 if ((status & asyncLSRDataReady) != 0x0) {
229 if ((status & ( asyncLSRFramingError |
230 asyncLSROverrunError |
231 asyncLSRParityError |
232 asyncLSRBreakInterrupt )) != 0) {
233 (void) out8 (asyncLSRport1,
234 asyncLSRFramingError |
235 asyncLSROverrunError |
236 asyncLSRParityError |
237 asyncLSRBreakInterrupt );
240 return (0x000000ff & (int) in8 (asyncRxBufferport1));
245 unsigned char status;
247 status = in8 (asyncLSRport1);
248 if ((status & asyncLSRDataReady) != 0x0) {
251 if ((status & ( asyncLSRFramingError |
252 asyncLSROverrunError |
253 asyncLSRParityError |
254 asyncLSRBreakInterrupt )) != 0) {
255 (void) out8 (asyncLSRport1,
256 asyncLSRFramingError |
257 asyncLSROverrunError |
258 asyncLSRParityError |
259 asyncLSRBreakInterrupt);
264 #endif /* CONFIG_IOP480 */
266 /*****************************************************************************/
267 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
269 #if defined(CONFIG_440)
270 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
271 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
272 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
274 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
275 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
278 #if defined(CONFIG_440SP)
279 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
282 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
283 #define CR0_MASK 0xdfffffff
284 #define CR0_EXTCLK_ENA 0x00800000
285 #define CR0_UDIV_POS 0
287 #define CR0_MASK 0x3fff0000
288 #define CR0_EXTCLK_ENA 0x00600000
289 #define CR0_UDIV_POS 16
290 #endif /* CONFIG_440GX */
291 #elif defined(CONFIG_405EP)
292 #define UART0_BASE 0xef600300
293 #define UART1_BASE 0xef600400
294 #define UCR0_MASK 0x0000007f
295 #define UCR1_MASK 0x00007f00
296 #define UCR0_UDIV_POS 0
297 #define UCR1_UDIV_POS 8
299 #else /* CONFIG_405GP || CONFIG_405CR */
300 #define UART0_BASE 0xef600300
301 #define UART1_BASE 0xef600400
302 #define CR0_MASK 0x00001fff
303 #define CR0_EXTCLK_ENA 0x000000c0
304 #define CR0_UDIV_POS 1
308 /* using serial port 0 or 1 as U-Boot console ? */
309 #if defined(CONFIG_UART1_CONSOLE)
310 #define ACTING_UART0_BASE UART1_BASE
311 #define ACTING_UART1_BASE UART0_BASE
312 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
313 #define UART0_SDR sdr_uart1
314 #define UART1_SDR sdr_uart0
315 #endif /* CONFIG_440GX */
317 #define ACTING_UART0_BASE UART0_BASE
318 #define ACTING_UART1_BASE UART1_BASE
319 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
320 #define UART0_SDR sdr_uart0
321 #define UART1_SDR sdr_uart1
322 #endif /* CONFIG_440GX */
325 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
326 #error "External serial clock not supported on AMCC PPC405EP!"
329 #define UART_RBR 0x00
330 #define UART_THR 0x00
331 #define UART_IER 0x01
332 #define UART_IIR 0x02
333 #define UART_FCR 0x02
334 #define UART_LCR 0x03
335 #define UART_MCR 0x04
336 #define UART_LSR 0x05
337 #define UART_MSR 0x06
338 #define UART_SCR 0x07
339 #define UART_DLL 0x00
340 #define UART_DLM 0x01
342 /*-----------------------------------------------------------------------------+
343 | Line Status Register.
344 +-----------------------------------------------------------------------------*/
345 /*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
346 #define asyncLSRDataReady1 0x01
347 #define asyncLSROverrunError1 0x02
348 #define asyncLSRParityError1 0x04
349 #define asyncLSRFramingError1 0x08
350 #define asyncLSRBreakInterrupt1 0x10
351 #define asyncLSRTxHoldEmpty1 0x20
352 #define asyncLSRTxShiftEmpty1 0x40
353 #define asyncLSRRxFifoError1 0x80
355 /*-----------------------------------------------------------------------------+
356 | Miscellanies defines.
357 +-----------------------------------------------------------------------------*/
358 /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
359 /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
361 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
362 /*-----------------------------------------------------------------------------+
364 +-----------------------------------------------------------------------------*/
371 volatile static serial_buffer_t buf_info;
374 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
375 static void serial_divs (int baudrate, unsigned long *pudiv,
376 unsigned short *pbdiv )
379 unsigned long div; /* total divisor udiv * bdiv */
380 unsigned long umin; /* minimum udiv */
381 unsigned short diff; /* smallest diff */
382 unsigned long udiv; /* best udiv */
384 unsigned short idiff; /* current diff */
385 unsigned short ibdiv; /* current bdiv */
387 unsigned long est; /* current estimate */
389 get_sys_info( &sysinfo );
391 udiv = 32; /* Assume lowest possible serial clk */
392 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
393 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
394 diff = 32; /* highest possible */
396 /* i is the test udiv value -- start with the largest
397 * possible (32) to minimize serial clock and constrain
400 for( i = 32; i > umin; i-- ){
403 idiff = (est > div) ? (est-div) : (div-est);
406 break; /* can't do better */
408 else if( idiff < diff ){
409 udiv = i; /* best so far */
410 diff = idiff; /* update lowest diff*/
418 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
421 * Minimal serial functions needed to use one of the SMC ports
422 * as serial console interface.
425 #if defined(CONFIG_440)
426 #if defined(CONFIG_SERIAL_MULTI)
427 int serial_init_dev (unsigned long dev_base)
429 int serial_init(void)
436 #ifdef CFG_EXT_SERIAL_CLOCK
440 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
441 #if defined(CONFIG_SERIAL_MULTI)
442 if (UART0_BASE == dev_base) {
443 mfsdr(UART0_SDR,reg);
446 mfsdr(UART1_SDR,reg);
450 mfsdr(UART0_SDR,reg);
454 reg = mfdcr(cntrl0) & ~CR0_MASK;
455 #endif /* CONFIG_440GX */
456 #ifdef CFG_EXT_SERIAL_CLOCK
457 reg |= CR0_EXTCLK_ENA;
459 tmp = gd->baudrate * 16;
460 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
462 /* For 440, the cpu clock is on divider chain A, UART on divider
463 * chain B ... so cpu clock is irrelevant. Get the "optimized"
464 * values that are subject to the 1/2 opb clock constraint
466 serial_divs (gd->baudrate, &udiv, &bdiv);
469 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
470 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
471 #if defined(CONFIG_SERIAL_MULTI)
472 if (UART0_BASE == dev_base) {
473 mtsdr (UART0_SDR,reg);
475 mtsdr (UART1_SDR,reg);
478 mtsdr (UART0_SDR,reg);
481 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
485 #if defined(CONFIG_SERIAL_MULTI)
486 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
487 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
488 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
489 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
490 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
491 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
492 val = in8 (dev_base + UART_LSR); /* clear line status */
493 val = in8 (dev_base + UART_RBR); /* read receive buffer */
494 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
495 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
497 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
498 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
499 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
500 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
501 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
502 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
503 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
504 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
505 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
506 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
511 #else /* !defined(CONFIG_440) */
513 #if defined(CONFIG_SERIAL_MULTI)
514 int serial_init_dev (unsigned long dev_base)
516 int serial_init (void)
527 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
529 tmp = CFG_BASE_BAUD * 16;
530 udiv = (clk + tmp / 2) / tmp;
531 if (udiv > UDIV_MAX) /* max. n bits for udiv */
533 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
534 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
535 mtdcr (cpc0_ucr, reg);
536 #else /* CONFIG_405EP */
537 reg = mfdcr(cntrl0) & ~CR0_MASK;
538 #ifdef CFG_EXT_SERIAL_CLOCK
539 clk = CFG_EXT_SERIAL_CLOCK;
541 reg |= CR0_EXTCLK_ENA;
544 #ifdef CFG_405_UART_ERRATA_59
545 udiv = 31; /* Errata 59: stuck at 31 */
547 tmp = CFG_BASE_BAUD * 16;
548 udiv = (clk + tmp / 2) / tmp;
549 if (udiv > UDIV_MAX) /* max. n bits for udiv */
553 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
555 #endif /* CONFIG_405EP */
557 tmp = gd->baudrate * udiv * 16;
558 bdiv = (clk + tmp / 2) / tmp;
560 #if defined(CONFIG_SERIAL_MULTI)
561 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
562 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
563 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
564 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
565 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
566 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
567 val = in8 (dev_base + UART_LSR); /* clear line status */
568 val = in8 (dev_base + UART_RBR); /* read receive buffer */
569 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
570 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
572 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
573 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
574 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
575 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
576 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
577 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
578 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
579 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
580 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
581 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
586 #endif /* if defined(CONFIG_440) */
588 #if defined(CONFIG_SERIAL_MULTI)
589 void serial_setbrg_dev (unsigned long dev_base)
591 void serial_setbrg (void)
599 #ifdef CFG_EXT_SERIAL_CLOCK
600 clk = CFG_EXT_SERIAL_CLOCK;
606 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
608 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
609 #endif /* CONFIG_405EP */
610 tmp = gd->baudrate * udiv * 16;
611 bdiv = (clk + tmp / 2) / tmp;
613 #if defined(CONFIG_SERIAL_MULTI)
614 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
615 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
616 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
617 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
619 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
620 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
621 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
622 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
626 #if defined(CONFIG_SERIAL_MULTI)
627 void serial_putc_dev (unsigned long dev_base, const char c)
629 void serial_putc (const char c)
635 #if defined(CONFIG_SERIAL_MULTI)
636 serial_putc_dev (dev_base, '\r');
641 /* check THRE bit, wait for transmiter available */
642 for (i = 1; i < 3500; i++) {
643 #if defined(CONFIG_SERIAL_MULTI)
644 if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
646 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
651 #if defined(CONFIG_SERIAL_MULTI)
652 out8 (dev_base + UART_THR, c); /* put character out */
654 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
658 #if defined(CONFIG_SERIAL_MULTI)
659 void serial_puts_dev (unsigned long dev_base, const char *s)
661 void serial_puts (const char *s)
665 #if defined(CONFIG_SERIAL_MULTI)
666 serial_putc_dev (dev_base, *s++);
673 #if defined(CONFIG_SERIAL_MULTI)
674 int serial_getc_dev (unsigned long dev_base)
676 int serial_getc (void)
679 unsigned char status = 0;
682 #if defined(CONFIG_HW_WATCHDOG)
683 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
684 #endif /* CONFIG_HW_WATCHDOG */
685 #if defined(CONFIG_SERIAL_MULTI)
686 status = in8 (dev_base + UART_LSR);
688 status = in8 (ACTING_UART0_BASE + UART_LSR);
690 if ((status & asyncLSRDataReady1) != 0x0) {
693 if ((status & ( asyncLSRFramingError1 |
694 asyncLSROverrunError1 |
695 asyncLSRParityError1 |
696 asyncLSRBreakInterrupt1 )) != 0) {
697 #if defined(CONFIG_SERIAL_MULTI)
698 out8 (dev_base + UART_LSR,
700 out8 (ACTING_UART0_BASE + UART_LSR,
702 asyncLSRFramingError1 |
703 asyncLSROverrunError1 |
704 asyncLSRParityError1 |
705 asyncLSRBreakInterrupt1);
708 #if defined(CONFIG_SERIAL_MULTI)
709 return (0x000000ff & (int) in8 (dev_base));
711 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
715 #if defined(CONFIG_SERIAL_MULTI)
716 int serial_tstc_dev (unsigned long dev_base)
718 int serial_tstc (void)
721 unsigned char status;
723 #if defined(CONFIG_SERIAL_MULTI)
724 status = in8 (dev_base + UART_LSR);
726 status = in8 (ACTING_UART0_BASE + UART_LSR);
728 if ((status & asyncLSRDataReady1) != 0x0) {
731 if ((status & ( asyncLSRFramingError1 |
732 asyncLSROverrunError1 |
733 asyncLSRParityError1 |
734 asyncLSRBreakInterrupt1 )) != 0) {
735 #if defined(CONFIG_SERIAL_MULTI)
736 out8 (dev_base + UART_LSR,
738 out8 (ACTING_UART0_BASE + UART_LSR,
740 asyncLSRFramingError1 |
741 asyncLSROverrunError1 |
742 asyncLSRParityError1 |
743 asyncLSRBreakInterrupt1);
748 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
750 void serial_isr (void *arg)
754 const int rx_get = buf_info.rx_get;
755 int rx_put = buf_info.rx_put;
757 if (rx_get <= rx_put) {
758 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
760 space = rx_get - rx_put;
762 while (serial_tstc_dev (ACTING_UART0_BASE)) {
763 c = serial_getc_dev (ACTING_UART0_BASE);
765 buf_info.rx_buffer[rx_put++] = c;
768 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
770 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
771 /* Stop flow by setting RTS inactive */
772 out8 (ACTING_UART0_BASE + UART_MCR,
773 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
776 buf_info.rx_put = rx_put;
779 void serial_buffered_init (void)
781 serial_puts ("Switching to interrupt driven serial input mode.\n");
782 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
786 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
787 serial_puts ("Check CTS signal present on serial port: OK.\n");
789 serial_puts ("WARNING: CTS signal not present on serial port.\n");
792 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
793 serial_isr /*interrupt_handler_t *handler */ ,
794 (void *) &buf_info /*void *arg */ );
796 /* Enable "RX Data Available" Interrupt on UART */
797 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
798 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
800 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
801 /* Start flow by setting RTS active */
802 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
803 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
804 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
807 void serial_buffered_putc (const char c)
810 #if defined(CONFIG_HW_WATCHDOG)
811 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
814 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
819 void serial_buffered_puts (const char *s)
824 int serial_buffered_getc (void)
828 int rx_get = buf_info.rx_get;
831 #if defined(CONFIG_HW_WATCHDOG)
832 while (rx_get == buf_info.rx_put)
835 while (rx_get == buf_info.rx_put);
837 c = buf_info.rx_buffer[rx_get++];
838 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
840 buf_info.rx_get = rx_get;
842 rx_put = buf_info.rx_put;
843 if (rx_get <= rx_put) {
844 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
846 space = rx_get - rx_put;
848 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
849 /* Start flow by setting RTS active */
850 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
856 int serial_buffered_tstc (void)
858 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
861 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
863 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
865 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
867 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
868 configuration has been already done
869 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
870 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
872 #if (CONFIG_KGDB_SER_INDEX & 2)
873 void kgdb_serial_init (void)
876 unsigned short br_reg;
879 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
882 * Init onboard 16550 UART
884 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
885 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
886 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
887 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
888 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
889 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
890 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
891 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
892 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
893 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
896 void putDebugChar (const char c)
901 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
903 /* check THRE bit, wait for transfer done */
904 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
907 void putDebugStr (const char *s)
914 int getDebugChar (void)
916 unsigned char status = 0;
919 status = in8 (ACTING_UART1_BASE + UART_LSR);
920 if ((status & asyncLSRDataReady1) != 0x0) {
923 if ((status & ( asyncLSRFramingError1 |
924 asyncLSROverrunError1 |
925 asyncLSRParityError1 |
926 asyncLSRBreakInterrupt1 )) != 0) {
927 out8 (ACTING_UART1_BASE + UART_LSR,
928 asyncLSRFramingError1 |
929 asyncLSROverrunError1 |
930 asyncLSRParityError1 |
931 asyncLSRBreakInterrupt1);
934 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
937 void kgdb_interruptible (int yes)
942 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
944 void kgdb_serial_init (void)
946 serial_printf ("[on serial] ");
949 void putDebugChar (int c)
954 void putDebugStr (const char *str)
959 int getDebugChar (void)
961 return serial_getc ();
964 void kgdb_interruptible (int yes)
968 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
969 #endif /* CFG_CMD_KGDB */
972 #if defined(CONFIG_SERIAL_MULTI)
973 int serial0_init(void)
975 return (serial_init_dev(UART0_BASE));
978 int serial1_init(void)
980 return (serial_init_dev(UART1_BASE));
982 void serial0_setbrg (void)
984 serial_setbrg_dev(UART0_BASE);
986 void serial1_setbrg (void)
988 serial_setbrg_dev(UART1_BASE);
991 void serial0_putc(const char c)
993 serial_putc_dev(UART0_BASE,c);
996 void serial1_putc(const char c)
998 serial_putc_dev(UART1_BASE, c);
1000 void serial0_puts(const char *s)
1002 serial_puts_dev(UART0_BASE, s);
1005 void serial1_puts(const char *s)
1007 serial_puts_dev(UART1_BASE, s);
1010 int serial0_getc(void)
1012 return(serial_getc_dev(UART0_BASE));
1015 int serial1_getc(void)
1017 return(serial_getc_dev(UART1_BASE));
1019 int serial0_tstc(void)
1021 return (serial_tstc_dev(UART0_BASE));
1024 int serial1_tstc(void)
1026 return (serial_tstc_dev(UART1_BASE));
1029 struct serial_device serial0_device =
1041 struct serial_device serial1_device =
1052 #endif /* CONFIG_SERIAL_MULTI */
1054 #endif /* CONFIG_405GP || CONFIG_405CR */