3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /*------------------------------------------------------------------------------+ */
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
43 /*------------------------------------------------------------------------------- */
47 #include <asm/processor.h>
51 #if CONFIG_SERIAL_SOFTWARE_FIFO
55 /*****************************************************************************/
58 #define SPU_BASE 0x40000000
60 #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
61 #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
62 #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
63 #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
64 #define spu_BRateDivh 0x10 /* Baud rate divisor high */
65 #define spu_BRateDivl 0x14 /* Baud rate divisor low */
66 #define spu_CtlReg 0x18 /* Control Register */
67 #define spu_RxCmd 0x1c /* Rx Command Register */
68 #define spu_TxCmd 0x20 /* Tx Command Register */
69 #define spu_RxBuff 0x24 /* Rx data buffer */
70 #define spu_TxBuff 0x24 /* Tx data buffer */
72 /*-----------------------------------------------------------------------------+
73 | Line Status Register.
74 +-----------------------------------------------------------------------------*/
75 #define asyncLSRport1 0x40000000
76 #define asyncLSRport1set 0x40000004
77 #define asyncLSRDataReady 0x80
78 #define asyncLSRFramingError 0x40
79 #define asyncLSROverrunError 0x20
80 #define asyncLSRParityError 0x10
81 #define asyncLSRBreakInterrupt 0x08
82 #define asyncLSRTxHoldEmpty 0x04
83 #define asyncLSRTxShiftEmpty 0x02
85 /*-----------------------------------------------------------------------------+
86 | Handshake Status Register.
87 +-----------------------------------------------------------------------------*/
88 #define asyncHSRport1 0x40000008
89 #define asyncHSRport1set 0x4000000c
90 #define asyncHSRDsr 0x80
91 #define asyncLSRCts 0x40
93 /*-----------------------------------------------------------------------------+
95 +-----------------------------------------------------------------------------*/
96 #define asyncCRport1 0x40000018
97 #define asyncCRNormal 0x00
98 #define asyncCRLoopback 0x40
99 #define asyncCRAutoEcho 0x80
100 #define asyncCRDtr 0x20
101 #define asyncCRRts 0x10
102 #define asyncCRWordLength7 0x00
103 #define asyncCRWordLength8 0x08
104 #define asyncCRParityDisable 0x00
105 #define asyncCRParityEnable 0x04
106 #define asyncCREvenParity 0x00
107 #define asyncCROddParity 0x02
108 #define asyncCRStopBitsOne 0x00
109 #define asyncCRStopBitsTwo 0x01
110 #define asyncCRDisableDtrRts 0x00
112 /*-----------------------------------------------------------------------------+
113 | Receiver Command Register.
114 +-----------------------------------------------------------------------------*/
115 #define asyncRCRport1 0x4000001c
116 #define asyncRCRDisable 0x00
117 #define asyncRCREnable 0x80
118 #define asyncRCRIntDisable 0x00
119 #define asyncRCRIntEnabled 0x20
120 #define asyncRCRDMACh2 0x40
121 #define asyncRCRDMACh3 0x60
122 #define asyncRCRErrorInt 0x10
123 #define asyncRCRPauseEnable 0x08
125 /*-----------------------------------------------------------------------------+
126 | Transmitter Command Register.
127 +-----------------------------------------------------------------------------*/
128 #define asyncTCRport1 0x40000020
129 #define asyncTCRDisable 0x00
130 #define asyncTCREnable 0x80
131 #define asyncTCRIntDisable 0x00
132 #define asyncTCRIntEnabled 0x20
133 #define asyncTCRDMACh2 0x40
134 #define asyncTCRDMACh3 0x60
135 #define asyncTCRTxEmpty 0x10
136 #define asyncTCRErrorInt 0x08
137 #define asyncTCRStopPause 0x04
138 #define asyncTCRBreakGen 0x02
140 /*-----------------------------------------------------------------------------+
141 | Miscellanies defines.
142 +-----------------------------------------------------------------------------*/
143 #define asyncTxBufferport1 0x40000024
144 #define asyncRxBufferport1 0x40000024
145 #define asyncDLABLsbport1 0x40000014
146 #define asyncDLABMsbport1 0x40000010
147 #define asyncXOFFchar 0x13
148 #define asyncXONchar 0x11
152 * Minimal serial functions needed to use one of the SMC ports
153 * as serial console interface.
156 int serial_init (void)
158 DECLARE_GLOBAL_DATA_PTR;
161 unsigned short br_reg;
163 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
168 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
169 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
170 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
171 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
172 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
173 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
174 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
175 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
181 void serial_setbrg (void)
183 DECLARE_GLOBAL_DATA_PTR;
185 unsigned short br_reg;
187 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
189 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
190 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
194 void serial_putc (const char c)
199 /* load status from handshake register */
200 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
201 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
203 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
205 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
206 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
207 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
212 void serial_puts (const char *s)
222 unsigned char status = 0;
225 status = in8 (asyncLSRport1);
226 if ((status & asyncLSRDataReady) != 0x0) {
229 if ((status & ( asyncLSRFramingError |
230 asyncLSROverrunError |
231 asyncLSRParityError |
232 asyncLSRBreakInterrupt )) != 0) {
233 (void) out8 (asyncLSRport1,
234 asyncLSRFramingError |
235 asyncLSROverrunError |
236 asyncLSRParityError |
237 asyncLSRBreakInterrupt );
240 return (0x000000ff & (int) in8 (asyncRxBufferport1));
246 unsigned char status;
248 status = in8 (asyncLSRport1);
249 if ((status & asyncLSRDataReady) != 0x0) {
252 if ((status & ( asyncLSRFramingError |
253 asyncLSROverrunError |
254 asyncLSRParityError |
255 asyncLSRBreakInterrupt )) != 0) {
256 (void) out8 (asyncLSRport1,
257 asyncLSRFramingError |
258 asyncLSROverrunError |
259 asyncLSRParityError |
260 asyncLSRBreakInterrupt);
265 #endif /* CONFIG_IOP480 */
268 /*****************************************************************************/
269 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
271 #if defined(CONFIG_440)
272 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
273 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
274 #define CR0_MASK 0x3fff0000
275 #define CR0_EXTCLK_ENA 0x00600000
276 #define CR0_UDIV_POS 16
277 #elif defined(CONFIG_405EP)
278 #define UART0_BASE 0xef600300
279 #define UART1_BASE 0xef600400
280 #define UCR0_MASK 0x0000007f
281 #define UCR1_MASK 0x00007f00
282 #define UCR0_UDIV_POS 0
283 #define UCR1_UDIV_POS 8
285 #else /* CONFIG_405GP || CONFIG_405CR */
286 #define UART0_BASE 0xef600300
287 #define UART1_BASE 0xef600400
288 #define CR0_MASK 0x00001fff
289 #define CR0_EXTCLK_ENA 0x000000c0
290 #define CR0_UDIV_POS 1
294 /* using serial port 0 or 1 as U-Boot console ? */
295 #if defined(CONFIG_UART1_CONSOLE)
296 #define ACTING_UART0_BASE UART1_BASE
297 #define ACTING_UART1_BASE UART0_BASE
299 #define ACTING_UART0_BASE UART0_BASE
300 #define ACTING_UART1_BASE UART1_BASE
303 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
304 #error "External serial clock not supported on IBM PPC405EP!"
307 #define UART_RBR 0x00
308 #define UART_THR 0x00
309 #define UART_IER 0x01
310 #define UART_IIR 0x02
311 #define UART_FCR 0x02
312 #define UART_LCR 0x03
313 #define UART_MCR 0x04
314 #define UART_LSR 0x05
315 #define UART_MSR 0x06
316 #define UART_SCR 0x07
317 #define UART_DLL 0x00
318 #define UART_DLM 0x01
320 /*-----------------------------------------------------------------------------+
321 | Line Status Register.
322 +-----------------------------------------------------------------------------*/
323 /*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
324 #define asyncLSRDataReady1 0x01
325 #define asyncLSROverrunError1 0x02
326 #define asyncLSRParityError1 0x04
327 #define asyncLSRFramingError1 0x08
328 #define asyncLSRBreakInterrupt1 0x10
329 #define asyncLSRTxHoldEmpty1 0x20
330 #define asyncLSRTxShiftEmpty1 0x40
331 #define asyncLSRRxFifoError1 0x80
333 /*-----------------------------------------------------------------------------+
334 | Miscellanies defines.
335 +-----------------------------------------------------------------------------*/
336 /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
337 /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
340 #if CONFIG_SERIAL_SOFTWARE_FIFO
341 /*-----------------------------------------------------------------------------+
343 +-----------------------------------------------------------------------------*/
350 volatile static serial_buffer_t buf_info;
354 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
355 static void serial_divs (int baudrate, unsigned long *pudiv,
356 unsigned short *pbdiv )
359 unsigned long div; /* total divisor udiv * bdiv */
360 unsigned long umin; /* minimum udiv */
361 unsigned short diff; /* smallest diff */
362 unsigned long udiv; /* best udiv */
364 unsigned short idiff; /* current diff */
365 unsigned short ibdiv; /* current bdiv */
367 unsigned long est; /* current estimate */
369 get_sys_info( &sysinfo );
371 udiv = 32; /* Assume lowest possible serial clk */
372 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
373 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
374 diff = 32; /* highest possible */
376 /* i is the test udiv value -- start with the largest
377 * possible (32) to minimize serial clock and constrain
380 for( i = 32; i > umin; i-- ){
383 idiff = (est > div) ? (est-div) : (div-est);
386 break; /* can't do better */
388 else if( idiff < diff ){
389 udiv = i; /* best so far */
390 diff = idiff; /* update lowest diff*/
398 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
402 * Minimal serial functions needed to use one of the SMC ports
403 * as serial console interface.
406 #if defined(CONFIG_440)
407 int serial_init (void)
409 DECLARE_GLOBAL_DATA_PTR;
415 #ifdef CFG_EXT_SERIAL_CLOCK
419 reg = mfdcr(cntrl0) & ~CR0_MASK;
420 #ifdef CFG_EXT_SERIAL_CLOCK
421 reg |= CR0_EXTCLK_ENA;
423 tmp = gd->baudrate * 16;
424 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
426 /* For 440, the cpu clock is on divider chain A, UART on divider
427 * chain B ... so cpu clock is irrelevant. Get the "optimized"
428 * values that are subject to the 1/2 opb clock constraint
430 serial_divs (gd->baudrate, &udiv, &bdiv);
433 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
436 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
437 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
438 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
439 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
440 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
441 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
442 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
443 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
444 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
445 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
450 #else /* !defined(CONFIG_440) */
452 int serial_init (void)
454 DECLARE_GLOBAL_DATA_PTR;
464 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
466 tmp = CFG_BASE_BAUD * 16;
467 udiv = (clk + tmp / 2) / tmp;
468 if (udiv > UDIV_MAX) /* max. n bits for udiv */
470 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
471 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
472 mtdcr (cpc0_ucr, reg);
473 #else /* CONFIG_405EP */
474 reg = mfdcr(cntrl0) & ~CR0_MASK;
475 #ifdef CFG_EXT_SERIAL_CLOCK
476 clk = CFG_EXT_SERIAL_CLOCK;
478 reg |= CR0_EXTCLK_ENA;
481 #ifdef CFG_405_UART_ERRATA_59
482 udiv = 31; /* Errata 59: stuck at 31 */
484 tmp = CFG_BASE_BAUD * 16;
485 udiv = (clk + tmp / 2) / tmp;
486 if (udiv > UDIV_MAX) /* max. n bits for udiv */
490 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
492 #endif /* CONFIG_405EP */
494 tmp = gd->baudrate * udiv * 16;
495 bdiv = (clk + tmp / 2) / tmp;
497 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
498 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
499 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
500 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
501 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
502 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
503 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
504 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
505 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
506 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
511 #endif /* if defined(CONFIG_440) */
513 void serial_setbrg (void)
515 DECLARE_GLOBAL_DATA_PTR;
522 #ifdef CFG_EXT_SERIAL_CLOCK
523 clk = CFG_EXT_SERIAL_CLOCK;
529 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
531 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
532 #endif /* CONFIG_405EP */
533 tmp = gd->baudrate * udiv * 16;
534 bdiv = (clk + tmp / 2) / tmp;
536 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
537 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
538 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
539 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
543 void serial_putc (const char c)
550 /* check THRE bit, wait for transmiter available */
551 for (i = 1; i < 3500; i++) {
552 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
556 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
560 void serial_puts (const char *s)
570 unsigned char status = 0;
573 #if defined(CONFIG_HW_WATCHDOG)
574 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
575 #endif /* CONFIG_HW_WATCHDOG */
576 status = in8 (ACTING_UART0_BASE + UART_LSR);
577 if ((status & asyncLSRDataReady1) != 0x0) {
580 if ((status & ( asyncLSRFramingError1 |
581 asyncLSROverrunError1 |
582 asyncLSRParityError1 |
583 asyncLSRBreakInterrupt1 )) != 0) {
584 out8 (ACTING_UART0_BASE + UART_LSR,
585 asyncLSRFramingError1 |
586 asyncLSROverrunError1 |
587 asyncLSRParityError1 |
588 asyncLSRBreakInterrupt1);
591 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
597 unsigned char status;
599 status = in8 (ACTING_UART0_BASE + UART_LSR);
600 if ((status & asyncLSRDataReady1) != 0x0) {
603 if ((status & ( asyncLSRFramingError1 |
604 asyncLSROverrunError1 |
605 asyncLSRParityError1 |
606 asyncLSRBreakInterrupt1 )) != 0) {
607 out8 (ACTING_UART0_BASE + UART_LSR,
608 asyncLSRFramingError1 |
609 asyncLSROverrunError1 |
610 asyncLSRParityError1 |
611 asyncLSRBreakInterrupt1);
617 #if CONFIG_SERIAL_SOFTWARE_FIFO
619 void serial_isr (void *arg)
623 const int rx_get = buf_info.rx_get;
624 int rx_put = buf_info.rx_put;
626 if (rx_get <= rx_put) {
627 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
629 space = rx_get - rx_put;
631 while (serial_tstc ()) {
634 buf_info.rx_buffer[rx_put++] = c;
637 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
639 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
640 /* Stop flow by setting RTS inactive */
641 out8 (ACTING_UART0_BASE + UART_MCR,
642 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
645 buf_info.rx_put = rx_put;
648 void serial_buffered_init (void)
650 serial_puts ("Switching to interrupt driven serial input mode.\n");
651 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
655 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
656 serial_puts ("Check CTS signal present on serial port: OK.\n");
658 serial_puts ("WARNING: CTS signal not present on serial port.\n");
661 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
662 serial_isr /*interrupt_handler_t *handler */ ,
663 (void *) &buf_info /*void *arg */ );
665 /* Enable "RX Data Available" Interrupt on UART */
666 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
667 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
669 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
670 /* Start flow by setting RTS active */
671 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
672 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
673 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
676 void serial_buffered_putc (const char c)
679 #if defined(CONFIG_HW_WATCHDOG)
680 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
683 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
688 void serial_buffered_puts (const char *s)
693 int serial_buffered_getc (void)
697 int rx_get = buf_info.rx_get;
700 #if defined(CONFIG_HW_WATCHDOG)
701 while (rx_get == buf_info.rx_put)
704 while (rx_get == buf_info.rx_put);
706 c = buf_info.rx_buffer[rx_get++];
707 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
709 buf_info.rx_get = rx_get;
711 rx_put = buf_info.rx_put;
712 if (rx_get <= rx_put) {
713 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
715 space = rx_get - rx_put;
717 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
718 /* Start flow by setting RTS active */
719 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
725 int serial_buffered_tstc (void)
727 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
730 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
733 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
735 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
737 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
738 configuration has been already done
739 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
740 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
742 #if (CONFIG_KGDB_SER_INDEX & 2)
743 void kgdb_serial_init (void)
745 DECLARE_GLOBAL_DATA_PTR;
748 unsigned short br_reg;
751 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
754 * Init onboard 16550 UART
756 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
757 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
758 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
759 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
760 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
761 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
762 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
763 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
764 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
765 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
769 void putDebugChar (const char c)
774 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
776 /* check THRE bit, wait for transfer done */
777 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
781 void putDebugStr (const char *s)
789 int getDebugChar (void)
791 unsigned char status = 0;
794 status = in8 (ACTING_UART1_BASE + UART_LSR);
795 if ((status & asyncLSRDataReady1) != 0x0) {
798 if ((status & ( asyncLSRFramingError1 |
799 asyncLSROverrunError1 |
800 asyncLSRParityError1 |
801 asyncLSRBreakInterrupt1 )) != 0) {
802 out8 (ACTING_UART1_BASE + UART_LSR,
803 asyncLSRFramingError1 |
804 asyncLSROverrunError1 |
805 asyncLSRParityError1 |
806 asyncLSRBreakInterrupt1);
809 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
813 void kgdb_interruptible (int yes)
818 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
820 void kgdb_serial_init (void)
822 serial_printf ("[on serial] ");
825 void putDebugChar (int c)
830 void putDebugStr (const char *str)
835 int getDebugChar (void)
837 return serial_getc ();
840 void kgdb_interruptible (int yes)
844 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
845 #endif /* CFG_CMD_KGDB */
847 #endif /* CONFIG_405GP || CONFIG_405CR */