2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /*------------------------------------------------------------------------------+ */
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
43 /*------------------------------------------------------------------------------- */
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
50 #include <asm/processor.h>
54 #ifdef CONFIG_SERIAL_MULTI
58 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
62 DECLARE_GLOBAL_DATA_PTR;
64 /*****************************************************************************/
67 #define SPU_BASE 0x40000000
69 #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
70 #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
71 #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
72 #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
73 #define spu_BRateDivh 0x10 /* Baud rate divisor high */
74 #define spu_BRateDivl 0x14 /* Baud rate divisor low */
75 #define spu_CtlReg 0x18 /* Control Register */
76 #define spu_RxCmd 0x1c /* Rx Command Register */
77 #define spu_TxCmd 0x20 /* Tx Command Register */
78 #define spu_RxBuff 0x24 /* Rx data buffer */
79 #define spu_TxBuff 0x24 /* Tx data buffer */
81 /*-----------------------------------------------------------------------------+
82 | Line Status Register.
83 +-----------------------------------------------------------------------------*/
84 #define asyncLSRport1 0x40000000
85 #define asyncLSRport1set 0x40000004
86 #define asyncLSRDataReady 0x80
87 #define asyncLSRFramingError 0x40
88 #define asyncLSROverrunError 0x20
89 #define asyncLSRParityError 0x10
90 #define asyncLSRBreakInterrupt 0x08
91 #define asyncLSRTxHoldEmpty 0x04
92 #define asyncLSRTxShiftEmpty 0x02
94 /*-----------------------------------------------------------------------------+
95 | Handshake Status Register.
96 +-----------------------------------------------------------------------------*/
97 #define asyncHSRport1 0x40000008
98 #define asyncHSRport1set 0x4000000c
99 #define asyncHSRDsr 0x80
100 #define asyncLSRCts 0x40
102 /*-----------------------------------------------------------------------------+
104 +-----------------------------------------------------------------------------*/
105 #define asyncCRport1 0x40000018
106 #define asyncCRNormal 0x00
107 #define asyncCRLoopback 0x40
108 #define asyncCRAutoEcho 0x80
109 #define asyncCRDtr 0x20
110 #define asyncCRRts 0x10
111 #define asyncCRWordLength7 0x00
112 #define asyncCRWordLength8 0x08
113 #define asyncCRParityDisable 0x00
114 #define asyncCRParityEnable 0x04
115 #define asyncCREvenParity 0x00
116 #define asyncCROddParity 0x02
117 #define asyncCRStopBitsOne 0x00
118 #define asyncCRStopBitsTwo 0x01
119 #define asyncCRDisableDtrRts 0x00
121 /*-----------------------------------------------------------------------------+
122 | Receiver Command Register.
123 +-----------------------------------------------------------------------------*/
124 #define asyncRCRport1 0x4000001c
125 #define asyncRCRDisable 0x00
126 #define asyncRCREnable 0x80
127 #define asyncRCRIntDisable 0x00
128 #define asyncRCRIntEnabled 0x20
129 #define asyncRCRDMACh2 0x40
130 #define asyncRCRDMACh3 0x60
131 #define asyncRCRErrorInt 0x10
132 #define asyncRCRPauseEnable 0x08
134 /*-----------------------------------------------------------------------------+
135 | Transmitter Command Register.
136 +-----------------------------------------------------------------------------*/
137 #define asyncTCRport1 0x40000020
138 #define asyncTCRDisable 0x00
139 #define asyncTCREnable 0x80
140 #define asyncTCRIntDisable 0x00
141 #define asyncTCRIntEnabled 0x20
142 #define asyncTCRDMACh2 0x40
143 #define asyncTCRDMACh3 0x60
144 #define asyncTCRTxEmpty 0x10
145 #define asyncTCRErrorInt 0x08
146 #define asyncTCRStopPause 0x04
147 #define asyncTCRBreakGen 0x02
149 /*-----------------------------------------------------------------------------+
150 | Miscellanies defines.
151 +-----------------------------------------------------------------------------*/
152 #define asyncTxBufferport1 0x40000024
153 #define asyncRxBufferport1 0x40000024
154 #define asyncDLABLsbport1 0x40000014
155 #define asyncDLABMsbport1 0x40000010
156 #define asyncXOFFchar 0x13
157 #define asyncXONchar 0x11
160 * Minimal serial functions needed to use one of the SMC ports
161 * as serial console interface.
164 int serial_init (void)
167 unsigned short br_reg;
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
186 void serial_setbrg (void)
188 unsigned short br_reg;
190 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
192 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
193 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
196 void serial_putc (const char c)
201 /* load status from handshake register */
202 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
203 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
205 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
207 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
208 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
209 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
213 void serial_puts (const char *s)
222 unsigned char status = 0;
225 status = in8 (asyncLSRport1);
226 if ((status & asyncLSRDataReady) != 0x0) {
229 if ((status & ( asyncLSRFramingError |
230 asyncLSROverrunError |
231 asyncLSRParityError |
232 asyncLSRBreakInterrupt )) != 0) {
233 (void) out8 (asyncLSRport1,
234 asyncLSRFramingError |
235 asyncLSROverrunError |
236 asyncLSRParityError |
237 asyncLSRBreakInterrupt );
240 return (0x000000ff & (int) in8 (asyncRxBufferport1));
245 unsigned char status;
247 status = in8 (asyncLSRport1);
248 if ((status & asyncLSRDataReady) != 0x0) {
251 if ((status & ( asyncLSRFramingError |
252 asyncLSROverrunError |
253 asyncLSRParityError |
254 asyncLSRBreakInterrupt )) != 0) {
255 (void) out8 (asyncLSRport1,
256 asyncLSRFramingError |
257 asyncLSROverrunError |
258 asyncLSRParityError |
259 asyncLSRBreakInterrupt);
264 #endif /* CONFIG_IOP480 */
266 /*****************************************************************************/
267 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
269 #if defined(CONFIG_440)
270 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
271 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
272 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
274 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
275 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
278 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
279 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
282 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
283 #define CR0_MASK 0xdfffffff
284 #define CR0_EXTCLK_ENA 0x00800000
285 #define CR0_UDIV_POS 0
287 #define CR0_MASK 0x3fff0000
288 #define CR0_EXTCLK_ENA 0x00600000
289 #define CR0_UDIV_POS 16
290 #endif /* CONFIG_440GX */
291 #elif defined(CONFIG_405EP)
292 #define UART0_BASE 0xef600300
293 #define UART1_BASE 0xef600400
294 #define UCR0_MASK 0x0000007f
295 #define UCR1_MASK 0x00007f00
296 #define UCR0_UDIV_POS 0
297 #define UCR1_UDIV_POS 8
299 #else /* CONFIG_405GP || CONFIG_405CR */
300 #define UART0_BASE 0xef600300
301 #define UART1_BASE 0xef600400
302 #define CR0_MASK 0x00001fff
303 #define CR0_EXTCLK_ENA 0x000000c0
304 #define CR0_UDIV_POS 1
308 /* using serial port 0 or 1 as U-Boot console ? */
309 #if defined(CONFIG_UART1_CONSOLE)
310 #define ACTING_UART0_BASE UART1_BASE
311 #define ACTING_UART1_BASE UART0_BASE
312 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
313 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
314 defined(CONFIG_440SPE)
315 #define UART0_SDR sdr_uart1
316 #define UART1_SDR sdr_uart0
317 #endif /* CONFIG_440GX */
319 #define ACTING_UART0_BASE UART0_BASE
320 #define ACTING_UART1_BASE UART1_BASE
321 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
322 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
323 defined(CONFIG_440SPE)
324 #define UART0_SDR sdr_uart0
325 #define UART1_SDR sdr_uart1
326 #endif /* CONFIG_440GX */
329 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
330 #error "External serial clock not supported on AMCC PPC405EP!"
333 #define UART_RBR 0x00
334 #define UART_THR 0x00
335 #define UART_IER 0x01
336 #define UART_IIR 0x02
337 #define UART_FCR 0x02
338 #define UART_LCR 0x03
339 #define UART_MCR 0x04
340 #define UART_LSR 0x05
341 #define UART_MSR 0x06
342 #define UART_SCR 0x07
343 #define UART_DLL 0x00
344 #define UART_DLM 0x01
346 /*-----------------------------------------------------------------------------+
347 | Line Status Register.
348 +-----------------------------------------------------------------------------*/
349 /*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
350 #define asyncLSRDataReady1 0x01
351 #define asyncLSROverrunError1 0x02
352 #define asyncLSRParityError1 0x04
353 #define asyncLSRFramingError1 0x08
354 #define asyncLSRBreakInterrupt1 0x10
355 #define asyncLSRTxHoldEmpty1 0x20
356 #define asyncLSRTxShiftEmpty1 0x40
357 #define asyncLSRRxFifoError1 0x80
359 /*-----------------------------------------------------------------------------+
360 | Miscellanies defines.
361 +-----------------------------------------------------------------------------*/
362 /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
363 /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
365 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
366 /*-----------------------------------------------------------------------------+
368 +-----------------------------------------------------------------------------*/
375 volatile static serial_buffer_t buf_info;
378 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
379 static void serial_divs (int baudrate, unsigned long *pudiv,
380 unsigned short *pbdiv )
383 unsigned long div; /* total divisor udiv * bdiv */
384 unsigned long umin; /* minimum udiv */
385 unsigned short diff; /* smallest diff */
386 unsigned long udiv; /* best udiv */
388 unsigned short idiff; /* current diff */
389 unsigned short ibdiv; /* current bdiv */
391 unsigned long est; /* current estimate */
393 get_sys_info( &sysinfo );
395 udiv = 32; /* Assume lowest possible serial clk */
396 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
397 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
398 diff = 32; /* highest possible */
400 /* i is the test udiv value -- start with the largest
401 * possible (32) to minimize serial clock and constrain
404 for( i = 32; i > umin; i-- ){
407 idiff = (est > div) ? (est-div) : (div-est);
410 break; /* can't do better */
412 else if( idiff < diff ){
413 udiv = i; /* best so far */
414 diff = idiff; /* update lowest diff*/
422 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
425 * Minimal serial functions needed to use one of the SMC ports
426 * as serial console interface.
429 #if defined(CONFIG_440)
430 #if defined(CONFIG_SERIAL_MULTI)
431 int serial_init_dev (unsigned long dev_base)
433 int serial_init(void)
440 #ifdef CFG_EXT_SERIAL_CLOCK
444 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
445 defined(CONFIG_440SPE)
446 #if defined(CONFIG_SERIAL_MULTI)
447 if (UART0_BASE == dev_base) {
448 mfsdr(UART0_SDR,reg);
451 mfsdr(UART1_SDR,reg);
455 mfsdr(UART0_SDR,reg);
459 reg = mfdcr(cntrl0) & ~CR0_MASK;
460 #endif /* CONFIG_440GX */
461 #ifdef CFG_EXT_SERIAL_CLOCK
462 reg |= CR0_EXTCLK_ENA;
464 tmp = gd->baudrate * 16;
465 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
467 /* For 440, the cpu clock is on divider chain A, UART on divider
468 * chain B ... so cpu clock is irrelevant. Get the "optimized"
469 * values that are subject to the 1/2 opb clock constraint
471 serial_divs (gd->baudrate, &udiv, &bdiv);
474 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
475 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
476 defined(CONFIG_440SPE)
477 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
478 #if defined(CONFIG_SERIAL_MULTI)
479 if (UART0_BASE == dev_base) {
480 mtsdr (UART0_SDR,reg);
482 mtsdr (UART1_SDR,reg);
485 mtsdr (UART0_SDR,reg);
488 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
492 #if defined(CONFIG_SERIAL_MULTI)
493 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
494 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
495 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
496 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
497 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
498 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
499 val = in8 (dev_base + UART_LSR); /* clear line status */
500 val = in8 (dev_base + UART_RBR); /* read receive buffer */
501 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
502 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
504 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
505 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
506 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
507 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
508 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
509 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
510 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
511 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
512 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
513 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
518 #else /* !defined(CONFIG_440) */
520 #if defined(CONFIG_SERIAL_MULTI)
521 int serial_init_dev (unsigned long dev_base)
523 int serial_init (void)
534 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
536 tmp = CFG_BASE_BAUD * 16;
537 udiv = (clk + tmp / 2) / tmp;
538 if (udiv > UDIV_MAX) /* max. n bits for udiv */
540 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
541 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
542 mtdcr (cpc0_ucr, reg);
543 #else /* CONFIG_405EP */
544 reg = mfdcr(cntrl0) & ~CR0_MASK;
545 #ifdef CFG_EXT_SERIAL_CLOCK
546 clk = CFG_EXT_SERIAL_CLOCK;
548 reg |= CR0_EXTCLK_ENA;
551 #ifdef CFG_405_UART_ERRATA_59
552 udiv = 31; /* Errata 59: stuck at 31 */
554 tmp = CFG_BASE_BAUD * 16;
555 udiv = (clk + tmp / 2) / tmp;
556 if (udiv > UDIV_MAX) /* max. n bits for udiv */
560 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
562 #endif /* CONFIG_405EP */
564 tmp = gd->baudrate * udiv * 16;
565 bdiv = (clk + tmp / 2) / tmp;
567 #if defined(CONFIG_SERIAL_MULTI)
568 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
569 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
570 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
571 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
572 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
573 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
574 val = in8 (dev_base + UART_LSR); /* clear line status */
575 val = in8 (dev_base + UART_RBR); /* read receive buffer */
576 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
577 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
579 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
580 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
581 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
582 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
583 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
584 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
585 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
586 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
587 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
588 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
593 #endif /* if defined(CONFIG_440) */
595 #if defined(CONFIG_SERIAL_MULTI)
596 void serial_setbrg_dev (unsigned long dev_base)
598 void serial_setbrg (void)
606 #ifdef CFG_EXT_SERIAL_CLOCK
607 clk = CFG_EXT_SERIAL_CLOCK;
613 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
615 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
616 #endif /* CONFIG_405EP */
618 #if !defined(CFG_EXT_SERIAL_CLOCK) && \
619 ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
620 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
621 defined(CONFIG_440SPE) )
622 serial_divs (gd->baudrate, &udiv, &bdiv);
623 tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */
624 #if defined(CONFIG_SERIAL_MULTI)
625 if (UART0_BASE == dev_base) {
626 mtsdr (UART0_SDR, tmp);
628 mtsdr (UART1_SDR, tmp);
631 mtsdr (UART0_SDR, tmp);
636 tmp = gd->baudrate * udiv * 16;
637 bdiv = (clk + tmp / 2) / tmp;
638 #endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
640 #if defined(CONFIG_SERIAL_MULTI)
641 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
642 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
643 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
644 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
646 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
647 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
648 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
649 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
653 #if defined(CONFIG_SERIAL_MULTI)
654 void serial_putc_dev (unsigned long dev_base, const char c)
656 void serial_putc (const char c)
662 #if defined(CONFIG_SERIAL_MULTI)
663 serial_putc_dev (dev_base, '\r');
668 /* check THRE bit, wait for transmiter available */
669 for (i = 1; i < 3500; i++) {
670 #if defined(CONFIG_SERIAL_MULTI)
671 if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
673 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
678 #if defined(CONFIG_SERIAL_MULTI)
679 out8 (dev_base + UART_THR, c); /* put character out */
681 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
685 #if defined(CONFIG_SERIAL_MULTI)
686 void serial_puts_dev (unsigned long dev_base, const char *s)
688 void serial_puts (const char *s)
692 #if defined(CONFIG_SERIAL_MULTI)
693 serial_putc_dev (dev_base, *s++);
700 #if defined(CONFIG_SERIAL_MULTI)
701 int serial_getc_dev (unsigned long dev_base)
703 int serial_getc (void)
706 unsigned char status = 0;
709 #if defined(CONFIG_HW_WATCHDOG)
710 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
711 #endif /* CONFIG_HW_WATCHDOG */
712 #if defined(CONFIG_SERIAL_MULTI)
713 status = in8 (dev_base + UART_LSR);
715 status = in8 (ACTING_UART0_BASE + UART_LSR);
717 if ((status & asyncLSRDataReady1) != 0x0) {
720 if ((status & ( asyncLSRFramingError1 |
721 asyncLSROverrunError1 |
722 asyncLSRParityError1 |
723 asyncLSRBreakInterrupt1 )) != 0) {
724 #if defined(CONFIG_SERIAL_MULTI)
725 out8 (dev_base + UART_LSR,
727 out8 (ACTING_UART0_BASE + UART_LSR,
729 asyncLSRFramingError1 |
730 asyncLSROverrunError1 |
731 asyncLSRParityError1 |
732 asyncLSRBreakInterrupt1);
735 #if defined(CONFIG_SERIAL_MULTI)
736 return (0x000000ff & (int) in8 (dev_base));
738 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
742 #if defined(CONFIG_SERIAL_MULTI)
743 int serial_tstc_dev (unsigned long dev_base)
745 int serial_tstc (void)
748 unsigned char status;
750 #if defined(CONFIG_SERIAL_MULTI)
751 status = in8 (dev_base + UART_LSR);
753 status = in8 (ACTING_UART0_BASE + UART_LSR);
755 if ((status & asyncLSRDataReady1) != 0x0) {
758 if ((status & ( asyncLSRFramingError1 |
759 asyncLSROverrunError1 |
760 asyncLSRParityError1 |
761 asyncLSRBreakInterrupt1 )) != 0) {
762 #if defined(CONFIG_SERIAL_MULTI)
763 out8 (dev_base + UART_LSR,
765 out8 (ACTING_UART0_BASE + UART_LSR,
767 asyncLSRFramingError1 |
768 asyncLSROverrunError1 |
769 asyncLSRParityError1 |
770 asyncLSRBreakInterrupt1);
775 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
777 void serial_isr (void *arg)
781 const int rx_get = buf_info.rx_get;
782 int rx_put = buf_info.rx_put;
784 if (rx_get <= rx_put) {
785 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
787 space = rx_get - rx_put;
789 while (serial_tstc_dev (ACTING_UART0_BASE)) {
790 c = serial_getc_dev (ACTING_UART0_BASE);
792 buf_info.rx_buffer[rx_put++] = c;
795 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
797 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
798 /* Stop flow by setting RTS inactive */
799 out8 (ACTING_UART0_BASE + UART_MCR,
800 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
803 buf_info.rx_put = rx_put;
806 void serial_buffered_init (void)
808 serial_puts ("Switching to interrupt driven serial input mode.\n");
809 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
813 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
814 serial_puts ("Check CTS signal present on serial port: OK.\n");
816 serial_puts ("WARNING: CTS signal not present on serial port.\n");
819 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
820 serial_isr /*interrupt_handler_t *handler */ ,
821 (void *) &buf_info /*void *arg */ );
823 /* Enable "RX Data Available" Interrupt on UART */
824 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
825 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
827 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
828 /* Start flow by setting RTS active */
829 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
830 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
831 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
834 void serial_buffered_putc (const char c)
837 #if defined(CONFIG_HW_WATCHDOG)
838 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
841 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
846 void serial_buffered_puts (const char *s)
851 int serial_buffered_getc (void)
855 int rx_get = buf_info.rx_get;
858 #if defined(CONFIG_HW_WATCHDOG)
859 while (rx_get == buf_info.rx_put)
862 while (rx_get == buf_info.rx_put);
864 c = buf_info.rx_buffer[rx_get++];
865 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
867 buf_info.rx_get = rx_get;
869 rx_put = buf_info.rx_put;
870 if (rx_get <= rx_put) {
871 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
873 space = rx_get - rx_put;
875 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
876 /* Start flow by setting RTS active */
877 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
883 int serial_buffered_tstc (void)
885 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
888 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
890 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
892 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
894 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
895 configuration has been already done
896 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
897 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
899 #if (CONFIG_KGDB_SER_INDEX & 2)
900 void kgdb_serial_init (void)
903 unsigned short br_reg;
906 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
909 * Init onboard 16550 UART
911 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
912 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
913 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
914 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
915 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
916 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
917 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
918 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
919 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
920 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
923 void putDebugChar (const char c)
928 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
930 /* check THRE bit, wait for transfer done */
931 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
934 void putDebugStr (const char *s)
941 int getDebugChar (void)
943 unsigned char status = 0;
946 status = in8 (ACTING_UART1_BASE + UART_LSR);
947 if ((status & asyncLSRDataReady1) != 0x0) {
950 if ((status & ( asyncLSRFramingError1 |
951 asyncLSROverrunError1 |
952 asyncLSRParityError1 |
953 asyncLSRBreakInterrupt1 )) != 0) {
954 out8 (ACTING_UART1_BASE + UART_LSR,
955 asyncLSRFramingError1 |
956 asyncLSROverrunError1 |
957 asyncLSRParityError1 |
958 asyncLSRBreakInterrupt1);
961 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
964 void kgdb_interruptible (int yes)
969 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
971 void kgdb_serial_init (void)
973 serial_printf ("[on serial] ");
976 void putDebugChar (int c)
981 void putDebugStr (const char *str)
986 int getDebugChar (void)
988 return serial_getc ();
991 void kgdb_interruptible (int yes)
995 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
996 #endif /* CFG_CMD_KGDB */
999 #if defined(CONFIG_SERIAL_MULTI)
1000 int serial0_init(void)
1002 return (serial_init_dev(UART0_BASE));
1005 int serial1_init(void)
1007 return (serial_init_dev(UART1_BASE));
1009 void serial0_setbrg (void)
1011 serial_setbrg_dev(UART0_BASE);
1013 void serial1_setbrg (void)
1015 serial_setbrg_dev(UART1_BASE);
1018 void serial0_putc(const char c)
1020 serial_putc_dev(UART0_BASE,c);
1023 void serial1_putc(const char c)
1025 serial_putc_dev(UART1_BASE, c);
1027 void serial0_puts(const char *s)
1029 serial_puts_dev(UART0_BASE, s);
1032 void serial1_puts(const char *s)
1034 serial_puts_dev(UART1_BASE, s);
1037 int serial0_getc(void)
1039 return(serial_getc_dev(UART0_BASE));
1042 int serial1_getc(void)
1044 return(serial_getc_dev(UART1_BASE));
1046 int serial0_tstc(void)
1048 return (serial_tstc_dev(UART0_BASE));
1051 int serial1_tstc(void)
1053 return (serial_tstc_dev(UART1_BASE));
1056 struct serial_device serial0_device =
1068 struct serial_device serial1_device =
1079 #endif /* CONFIG_SERIAL_MULTI */
1081 #endif /* CONFIG_405GP || CONFIG_405CR */