2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /*------------------------------------------------------------------------------+ */
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
43 /*------------------------------------------------------------------------------- */
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
50 #include <asm/processor.h>
54 #ifdef CONFIG_SERIAL_MULTI
58 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
62 DECLARE_GLOBAL_DATA_PTR;
64 /*****************************************************************************/
67 #define SPU_BASE 0x40000000
69 #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
70 #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
71 #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
72 #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
73 #define spu_BRateDivh 0x10 /* Baud rate divisor high */
74 #define spu_BRateDivl 0x14 /* Baud rate divisor low */
75 #define spu_CtlReg 0x18 /* Control Register */
76 #define spu_RxCmd 0x1c /* Rx Command Register */
77 #define spu_TxCmd 0x20 /* Tx Command Register */
78 #define spu_RxBuff 0x24 /* Rx data buffer */
79 #define spu_TxBuff 0x24 /* Tx data buffer */
81 /*-----------------------------------------------------------------------------+
82 | Line Status Register.
83 +-----------------------------------------------------------------------------*/
84 #define asyncLSRport1 0x40000000
85 #define asyncLSRport1set 0x40000004
86 #define asyncLSRDataReady 0x80
87 #define asyncLSRFramingError 0x40
88 #define asyncLSROverrunError 0x20
89 #define asyncLSRParityError 0x10
90 #define asyncLSRBreakInterrupt 0x08
91 #define asyncLSRTxHoldEmpty 0x04
92 #define asyncLSRTxShiftEmpty 0x02
94 /*-----------------------------------------------------------------------------+
95 | Handshake Status Register.
96 +-----------------------------------------------------------------------------*/
97 #define asyncHSRport1 0x40000008
98 #define asyncHSRport1set 0x4000000c
99 #define asyncHSRDsr 0x80
100 #define asyncLSRCts 0x40
102 /*-----------------------------------------------------------------------------+
104 +-----------------------------------------------------------------------------*/
105 #define asyncCRport1 0x40000018
106 #define asyncCRNormal 0x00
107 #define asyncCRLoopback 0x40
108 #define asyncCRAutoEcho 0x80
109 #define asyncCRDtr 0x20
110 #define asyncCRRts 0x10
111 #define asyncCRWordLength7 0x00
112 #define asyncCRWordLength8 0x08
113 #define asyncCRParityDisable 0x00
114 #define asyncCRParityEnable 0x04
115 #define asyncCREvenParity 0x00
116 #define asyncCROddParity 0x02
117 #define asyncCRStopBitsOne 0x00
118 #define asyncCRStopBitsTwo 0x01
119 #define asyncCRDisableDtrRts 0x00
121 /*-----------------------------------------------------------------------------+
122 | Receiver Command Register.
123 +-----------------------------------------------------------------------------*/
124 #define asyncRCRport1 0x4000001c
125 #define asyncRCRDisable 0x00
126 #define asyncRCREnable 0x80
127 #define asyncRCRIntDisable 0x00
128 #define asyncRCRIntEnabled 0x20
129 #define asyncRCRDMACh2 0x40
130 #define asyncRCRDMACh3 0x60
131 #define asyncRCRErrorInt 0x10
132 #define asyncRCRPauseEnable 0x08
134 /*-----------------------------------------------------------------------------+
135 | Transmitter Command Register.
136 +-----------------------------------------------------------------------------*/
137 #define asyncTCRport1 0x40000020
138 #define asyncTCRDisable 0x00
139 #define asyncTCREnable 0x80
140 #define asyncTCRIntDisable 0x00
141 #define asyncTCRIntEnabled 0x20
142 #define asyncTCRDMACh2 0x40
143 #define asyncTCRDMACh3 0x60
144 #define asyncTCRTxEmpty 0x10
145 #define asyncTCRErrorInt 0x08
146 #define asyncTCRStopPause 0x04
147 #define asyncTCRBreakGen 0x02
149 /*-----------------------------------------------------------------------------+
150 | Miscellanies defines.
151 +-----------------------------------------------------------------------------*/
152 #define asyncTxBufferport1 0x40000024
153 #define asyncRxBufferport1 0x40000024
154 #define asyncDLABLsbport1 0x40000014
155 #define asyncDLABMsbport1 0x40000010
156 #define asyncXOFFchar 0x13
157 #define asyncXONchar 0x11
160 * Minimal serial functions needed to use one of the SMC ports
161 * as serial console interface.
164 int serial_init (void)
167 unsigned short br_reg;
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
186 void serial_setbrg (void)
188 unsigned short br_reg;
190 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
192 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
193 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
196 void serial_putc (const char c)
201 /* load status from handshake register */
202 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
203 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
205 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
207 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
208 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
209 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
213 void serial_puts (const char *s)
222 unsigned char status = 0;
225 status = in8 (asyncLSRport1);
226 if ((status & asyncLSRDataReady) != 0x0) {
229 if ((status & ( asyncLSRFramingError |
230 asyncLSROverrunError |
231 asyncLSRParityError |
232 asyncLSRBreakInterrupt )) != 0) {
233 (void) out8 (asyncLSRport1,
234 asyncLSRFramingError |
235 asyncLSROverrunError |
236 asyncLSRParityError |
237 asyncLSRBreakInterrupt );
240 return (0x000000ff & (int) in8 (asyncRxBufferport1));
245 unsigned char status;
247 status = in8 (asyncLSRport1);
248 if ((status & asyncLSRDataReady) != 0x0) {
251 if ((status & ( asyncLSRFramingError |
252 asyncLSROverrunError |
253 asyncLSRParityError |
254 asyncLSRBreakInterrupt )) != 0) {
255 (void) out8 (asyncLSRport1,
256 asyncLSRFramingError |
257 asyncLSROverrunError |
258 asyncLSRParityError |
259 asyncLSRBreakInterrupt);
264 #endif /* CONFIG_IOP480 */
266 /*****************************************************************************/
267 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
270 #if defined(CONFIG_440)
271 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
272 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
273 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
274 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
276 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
277 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
280 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
281 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
284 #if defined(CONFIG_440GP)
285 #define CR0_MASK 0x3fff0000
286 #define CR0_EXTCLK_ENA 0x00600000
287 #define CR0_UDIV_POS 16
288 #define UDIV_SUBTRACT 1
289 #define UART0_SDR cntrl0
290 #define MFREG(a, d) d = mfdcr(a)
291 #define MTREG(a, d) mtdcr(a, d)
292 #else /* #if defined(CONFIG_440GP) */
293 /* all other 440 PPC's access clock divider via sdr register */
294 #define CR0_MASK 0xdfffffff
295 #define CR0_EXTCLK_ENA 0x00800000
296 #define CR0_UDIV_POS 0
297 #define UDIV_SUBTRACT 0
298 #define UART0_SDR sdr_uart0
299 #define UART1_SDR sdr_uart1
300 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
301 defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
302 defined(CONFIG_440SP) || defined(CONFIG_440SPe)
303 #define UART2_SDR sdr_uart2
305 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
306 defined(CONFIG_440GR) || defined(CONFIG_440GRx)
307 #define UART3_SDR sdr_uart3
309 #define MFREG(a, d) mfsdr(a, d)
310 #define MTREG(a, d) mtsdr(a, d)
311 #endif /* #if defined(CONFIG_440GP) */
312 #elif defined(CONFIG_405EP)
313 #define UART0_BASE 0xef600300
314 #define UART1_BASE 0xef600400
315 #define UCR0_MASK 0x0000007f
316 #define UCR1_MASK 0x00007f00
317 #define UCR0_UDIV_POS 0
318 #define UCR1_UDIV_POS 8
320 #else /* CONFIG_405GP || CONFIG_405CR */
321 #define UART0_BASE 0xef600300
322 #define UART1_BASE 0xef600400
323 #define CR0_MASK 0x00001fff
324 #define CR0_EXTCLK_ENA 0x000000c0
325 #define CR0_UDIV_POS 1
329 /* using serial port 0 or 1 as U-Boot console ? */
330 #if defined(CONFIG_UART1_CONSOLE)
331 #define ACTING_UART0_BASE UART1_BASE
332 #define ACTING_UART1_BASE UART0_BASE
334 #define ACTING_UART0_BASE UART0_BASE
335 #define ACTING_UART1_BASE UART1_BASE
338 #if defined(CONFIG_SERIAL_MULTI)
339 #define UART_BASE dev_base
341 #define UART_BASE ACTING_UART0_BASE
344 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
345 #error "External serial clock not supported on AMCC PPC405EP!"
348 #define UART_RBR 0x00
349 #define UART_THR 0x00
350 #define UART_IER 0x01
351 #define UART_IIR 0x02
352 #define UART_FCR 0x02
353 #define UART_LCR 0x03
354 #define UART_MCR 0x04
355 #define UART_LSR 0x05
356 #define UART_MSR 0x06
357 #define UART_SCR 0x07
358 #define UART_DLL 0x00
359 #define UART_DLM 0x01
361 /*-----------------------------------------------------------------------------+
362 | Line Status Register.
363 +-----------------------------------------------------------------------------*/
364 /*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
365 #define asyncLSRDataReady1 0x01
366 #define asyncLSROverrunError1 0x02
367 #define asyncLSRParityError1 0x04
368 #define asyncLSRFramingError1 0x08
369 #define asyncLSRBreakInterrupt1 0x10
370 #define asyncLSRTxHoldEmpty1 0x20
371 #define asyncLSRTxShiftEmpty1 0x40
372 #define asyncLSRRxFifoError1 0x80
374 /*-----------------------------------------------------------------------------+
375 | Miscellanies defines.
376 +-----------------------------------------------------------------------------*/
377 /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
378 /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
380 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
381 /*-----------------------------------------------------------------------------+
383 +-----------------------------------------------------------------------------*/
390 volatile static serial_buffer_t buf_info;
393 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
394 static void serial_divs (int baudrate, unsigned long *pudiv,
395 unsigned short *pbdiv )
398 unsigned long div; /* total divisor udiv * bdiv */
399 unsigned long umin; /* minimum udiv */
400 unsigned short diff; /* smallest diff */
401 unsigned long udiv; /* best udiv */
403 unsigned short idiff; /* current diff */
404 unsigned short ibdiv; /* current bdiv */
406 unsigned long est; /* current estimate */
408 get_sys_info( &sysinfo );
410 udiv = 32; /* Assume lowest possible serial clk */
411 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
412 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
413 diff = 32; /* highest possible */
415 /* i is the test udiv value -- start with the largest
416 * possible (32) to minimize serial clock and constrain
419 for( i = 32; i > umin; i-- ){
422 idiff = (est > div) ? (est-div) : (div-est);
425 break; /* can't do better */
427 else if( idiff < diff ){
428 udiv = i; /* best so far */
429 diff = idiff; /* update lowest diff*/
437 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
440 * Minimal serial functions needed to use one of the SMC ports
441 * as serial console interface.
444 #if defined(CONFIG_440)
445 #if defined(CONFIG_SERIAL_MULTI)
446 int serial_init_dev (unsigned long dev_base)
448 int serial_init(void)
455 #ifdef CFG_EXT_SERIAL_CLOCK
459 MFREG(UART0_SDR, reg);
462 #ifdef CFG_EXT_SERIAL_CLOCK
463 reg |= CR0_EXTCLK_ENA;
465 tmp = gd->baudrate * 16;
466 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
468 /* For 440, the cpu clock is on divider chain A, UART on divider
469 * chain B ... so cpu clock is irrelevant. Get the "optimized"
470 * values that are subject to the 1/2 opb clock constraint
472 serial_divs (gd->baudrate, &udiv, &bdiv);
475 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
478 * Configure input clock to baudrate generator for all
479 * available serial ports here
481 MTREG(UART0_SDR, reg);
482 #if defined(UART1_SDR)
483 MTREG(UART1_SDR, reg);
485 #if defined(UART2_SDR)
486 MTREG(UART2_SDR, reg);
488 #if defined(UART3_SDR)
489 MTREG(UART3_SDR, reg);
492 out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
493 out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
494 out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
495 out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
496 out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
497 out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
498 val = in8(UART_BASE + UART_LSR); /* clear line status */
499 val = in8(UART_BASE + UART_RBR); /* read receive buffer */
500 out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
501 out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
506 #else /* !defined(CONFIG_440) */
508 #if defined(CONFIG_SERIAL_MULTI)
509 int serial_init_dev (unsigned long dev_base)
511 int serial_init (void)
522 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
524 tmp = CFG_BASE_BAUD * 16;
525 udiv = (clk + tmp / 2) / tmp;
526 if (udiv > UDIV_MAX) /* max. n bits for udiv */
528 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
529 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
530 mtdcr (cpc0_ucr, reg);
531 #else /* CONFIG_405EP */
532 reg = mfdcr(cntrl0) & ~CR0_MASK;
533 #ifdef CFG_EXT_SERIAL_CLOCK
534 clk = CFG_EXT_SERIAL_CLOCK;
536 reg |= CR0_EXTCLK_ENA;
539 #ifdef CFG_405_UART_ERRATA_59
540 udiv = 31; /* Errata 59: stuck at 31 */
542 tmp = CFG_BASE_BAUD * 16;
543 udiv = (clk + tmp / 2) / tmp;
544 if (udiv > UDIV_MAX) /* max. n bits for udiv */
548 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
550 #endif /* CONFIG_405EP */
552 tmp = gd->baudrate * udiv * 16;
553 bdiv = (clk + tmp / 2) / tmp;
555 out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
556 out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
557 out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
558 out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
559 out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
560 out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
561 val = in8(UART_BASE + UART_LSR); /* clear line status */
562 val = in8(UART_BASE + UART_RBR); /* read receive buffer */
563 out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
564 out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
569 #endif /* if defined(CONFIG_440) */
571 #if defined(CONFIG_SERIAL_MULTI)
572 void serial_setbrg_dev (unsigned long dev_base)
574 void serial_setbrg (void)
577 #if defined(CONFIG_SERIAL_MULTI)
578 serial_init_dev(dev_base);
584 #if defined(CONFIG_SERIAL_MULTI)
585 void serial_putc_dev (unsigned long dev_base, const char c)
587 void serial_putc (const char c)
593 #if defined(CONFIG_SERIAL_MULTI)
594 serial_putc_dev (dev_base, '\r');
599 /* check THRE bit, wait for transmiter available */
600 for (i = 1; i < 3500; i++) {
601 if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
605 out8 (UART_BASE + UART_THR, c); /* put character out */
608 #if defined(CONFIG_SERIAL_MULTI)
609 void serial_puts_dev (unsigned long dev_base, const char *s)
611 void serial_puts (const char *s)
615 #if defined(CONFIG_SERIAL_MULTI)
616 serial_putc_dev (dev_base, *s++);
623 #if defined(CONFIG_SERIAL_MULTI)
624 int serial_getc_dev (unsigned long dev_base)
626 int serial_getc (void)
629 unsigned char status = 0;
632 #if defined(CONFIG_HW_WATCHDOG)
633 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
634 #endif /* CONFIG_HW_WATCHDOG */
635 status = in8 (UART_BASE + UART_LSR);
636 if ((status & asyncLSRDataReady1) != 0x0) {
639 if ((status & ( asyncLSRFramingError1 |
640 asyncLSROverrunError1 |
641 asyncLSRParityError1 |
642 asyncLSRBreakInterrupt1 )) != 0) {
643 out8 (UART_BASE + UART_LSR,
644 asyncLSRFramingError1 |
645 asyncLSROverrunError1 |
646 asyncLSRParityError1 |
647 asyncLSRBreakInterrupt1);
650 return (0x000000ff & (int) in8 (UART_BASE));
653 #if defined(CONFIG_SERIAL_MULTI)
654 int serial_tstc_dev (unsigned long dev_base)
656 int serial_tstc (void)
659 unsigned char status;
661 status = in8 (UART_BASE + UART_LSR);
662 if ((status & asyncLSRDataReady1) != 0x0) {
665 if ((status & ( asyncLSRFramingError1 |
666 asyncLSROverrunError1 |
667 asyncLSRParityError1 |
668 asyncLSRBreakInterrupt1 )) != 0) {
669 out8 (UART_BASE + UART_LSR,
670 asyncLSRFramingError1 |
671 asyncLSROverrunError1 |
672 asyncLSRParityError1 |
673 asyncLSRBreakInterrupt1);
678 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
680 void serial_isr (void *arg)
684 const int rx_get = buf_info.rx_get;
685 int rx_put = buf_info.rx_put;
687 if (rx_get <= rx_put) {
688 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
690 space = rx_get - rx_put;
692 while (serial_tstc_dev (ACTING_UART0_BASE)) {
693 c = serial_getc_dev (ACTING_UART0_BASE);
695 buf_info.rx_buffer[rx_put++] = c;
698 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
700 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
701 /* Stop flow by setting RTS inactive */
702 out8 (ACTING_UART0_BASE + UART_MCR,
703 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
706 buf_info.rx_put = rx_put;
709 void serial_buffered_init (void)
711 serial_puts ("Switching to interrupt driven serial input mode.\n");
712 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
716 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
717 serial_puts ("Check CTS signal present on serial port: OK.\n");
719 serial_puts ("WARNING: CTS signal not present on serial port.\n");
722 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
723 serial_isr /*interrupt_handler_t *handler */ ,
724 (void *) &buf_info /*void *arg */ );
726 /* Enable "RX Data Available" Interrupt on UART */
727 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
728 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
730 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
731 /* Start flow by setting RTS active */
732 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
733 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
734 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
737 void serial_buffered_putc (const char c)
740 #if defined(CONFIG_HW_WATCHDOG)
741 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
744 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
749 void serial_buffered_puts (const char *s)
754 int serial_buffered_getc (void)
758 int rx_get = buf_info.rx_get;
761 #if defined(CONFIG_HW_WATCHDOG)
762 while (rx_get == buf_info.rx_put)
765 while (rx_get == buf_info.rx_put);
767 c = buf_info.rx_buffer[rx_get++];
768 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
770 buf_info.rx_get = rx_get;
772 rx_put = buf_info.rx_put;
773 if (rx_get <= rx_put) {
774 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
776 space = rx_get - rx_put;
778 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
779 /* Start flow by setting RTS active */
780 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
786 int serial_buffered_tstc (void)
788 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
791 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
793 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
795 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
797 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
798 configuration has been already done
799 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
800 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
802 #if (CONFIG_KGDB_SER_INDEX & 2)
803 void kgdb_serial_init (void)
806 unsigned short br_reg;
809 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
812 * Init onboard 16550 UART
814 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
815 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
816 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
817 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
818 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
819 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
820 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
821 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
822 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
823 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
826 void putDebugChar (const char c)
831 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
833 /* check THRE bit, wait for transfer done */
834 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
837 void putDebugStr (const char *s)
844 int getDebugChar (void)
846 unsigned char status = 0;
849 status = in8 (ACTING_UART1_BASE + UART_LSR);
850 if ((status & asyncLSRDataReady1) != 0x0) {
853 if ((status & ( asyncLSRFramingError1 |
854 asyncLSROverrunError1 |
855 asyncLSRParityError1 |
856 asyncLSRBreakInterrupt1 )) != 0) {
857 out8 (ACTING_UART1_BASE + UART_LSR,
858 asyncLSRFramingError1 |
859 asyncLSROverrunError1 |
860 asyncLSRParityError1 |
861 asyncLSRBreakInterrupt1);
864 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
867 void kgdb_interruptible (int yes)
872 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
874 void kgdb_serial_init (void)
876 serial_printf ("[on serial] ");
879 void putDebugChar (int c)
884 void putDebugStr (const char *str)
889 int getDebugChar (void)
891 return serial_getc ();
894 void kgdb_interruptible (int yes)
898 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
899 #endif /* CFG_CMD_KGDB */
902 #if defined(CONFIG_SERIAL_MULTI)
903 int serial0_init(void)
905 return (serial_init_dev(UART0_BASE));
908 int serial1_init(void)
910 return (serial_init_dev(UART1_BASE));
912 void serial0_setbrg (void)
914 serial_setbrg_dev(UART0_BASE);
916 void serial1_setbrg (void)
918 serial_setbrg_dev(UART1_BASE);
921 void serial0_putc(const char c)
923 serial_putc_dev(UART0_BASE,c);
926 void serial1_putc(const char c)
928 serial_putc_dev(UART1_BASE, c);
930 void serial0_puts(const char *s)
932 serial_puts_dev(UART0_BASE, s);
935 void serial1_puts(const char *s)
937 serial_puts_dev(UART1_BASE, s);
940 int serial0_getc(void)
942 return(serial_getc_dev(UART0_BASE));
945 int serial1_getc(void)
947 return(serial_getc_dev(UART1_BASE));
949 int serial0_tstc(void)
951 return (serial_tstc_dev(UART0_BASE));
954 int serial1_tstc(void)
956 return (serial_tstc_dev(UART1_BASE));
959 struct serial_device serial0_device =
971 struct serial_device serial1_device =
982 #endif /* CONFIG_SERIAL_MULTI */
984 #endif /* CONFIG_405GP || CONFIG_405CR */