3 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
7 * Kenneth Johansson ,Ericsson Business Innovation.
8 * kenneth.johansson@inn.ericsson.se
10 * hacked up by bill hunter. fixed so we could run before
11 * serial_init and console_init. previous version avoided this by
12 * running out of cache memory during serial/console init, then running
16 * Jun Gu, Artesyn Technology, jung@artesyncp.com
17 * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/processor.h>
43 #ifdef CONFIG_SPD_EEPROM
49 #define CFG_I2C_SPEED 50000
53 #define CFG_I2C_SLAVE 0xFE
56 #ifndef CONFIG_440 /* for 405 WALNUT board */
58 #define SDRAM0_CFG_DCE 0x80000000
59 #define SDRAM0_CFG_SRE 0x40000000
60 #define SDRAM0_CFG_PME 0x20000000
61 #define SDRAM0_CFG_MEMCHK 0x10000000
62 #define SDRAM0_CFG_REGEN 0x08000000
63 #define SDRAM0_CFG_ECCDD 0x00400000
64 #define SDRAM0_CFG_EMDULR 0x00200000
65 #define SDRAM0_CFG_DRW_SHIFT (31-6)
66 #define SDRAM0_CFG_BRPF_SHIFT (31-8)
68 #define SDRAM0_TR_CASL_SHIFT (31-8)
69 #define SDRAM0_TR_PTA_SHIFT (31-13)
70 #define SDRAM0_TR_CTP_SHIFT (31-15)
71 #define SDRAM0_TR_LDF_SHIFT (31-17)
72 #define SDRAM0_TR_RFTA_SHIFT (31-29)
73 #define SDRAM0_TR_RCD_SHIFT (31-31)
75 #define SDRAM0_RTR_SHIFT (31-15)
76 #define SDRAM0_ECCCFG_SHIFT (31-11)
78 /* SDRAM0_CFG enable macro */
79 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
81 #define SDRAM0_BXCR_SZ_MASK 0x000e0000
82 #define SDRAM0_BXCR_AM_MASK 0x0000e000
84 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
85 #define SDRAM0_BXCR_AM_SHIFT (31-18)
87 #define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
88 #define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
91 # define SPD_ERR(x) do { return 0; } while (0)
93 # define SPD_ERR(x) do { printf(x); hang(); } while (0)
97 * what we really want is
98 * (1/hertz) but we don't want to use floats so multiply with 10E9
100 * The error needs to be on the safe side so we want the floor function.
101 * This means we get an exact value or we calculate that our bus frequency is
102 * a bit faster than it really is and thus we don't progam the sdram controller
105 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
107 /* function prototypes */
108 int spd_read(uint addr); /* prototype */
112 * This function is reading data from the DIMM module EEPROM over the SPD bus
113 * and uses that to program the sdram controller.
115 * This works on boards that has the same schematics that the IBM walnut has.
117 * BUG: Don't handle ECC memory
118 * BUG: A few values in the TR register is currently hardcoded
121 long int spd_sdram(void)
123 int bus_period,tmp,row,col;
124 int total_size,bank_size,bank_code;
129 int sdram0_pmit=0x07c00000;
132 int sdram0_eccesr=-1;
147 int t_rc = 70; /* This value not available in SPD_EEPROM */
151 * Make sure I2C controller is initialized
154 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
157 * Calculate the bus period, we do it this
158 * way to minimize stack utilization.
160 tmp = (mfdcr(pllmd) >> (31-6)) & 0xf; /* get FBDV bits */
161 tmp = CONFIG_SYS_CLK_FREQ * tmp; /* get plb freq */
162 bus_period = sdram_HZ_to_ns(tmp); /* get sdram speed */
164 /* Make shure we are using SDRAM */
165 if (spd_read(2) != 0x04){
166 SPD_ERR("SDRAM - non SDRAM memory module found\n");
169 /*------------------------------------------------------------------
170 configure memory timing register
173 27 IN Row Precharge Time ( t RP)
174 29 MIN RAS to CAS Delay ( t RCD)
175 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
176 -------------------------------------------------------------------*/
179 * first figure out which cas latency mode to use
180 * use the min supported mode
183 tmp = spd_read(127) & 0x6;
184 if(tmp == 0x02){ /* only cas = 2 supported */
186 /* t_ck = spd_read(9); */
187 /* t_ac = spd_read(10); */
189 else if (tmp == 0x04){ /* only cas = 3 supported */
191 /* t_ck = spd_read(9); */
192 /* t_ac = spd_read(10); */
194 else if (tmp == 0x06){ /* 2,3 supported, so use 2 */
196 /* t_ck = spd_read(23); */
197 /* t_ac = spd_read(24); */
200 SPD_ERR("SDRAM - unsupported CAS latency \n");
203 /* get some timing values, t_rp,t_rcd
206 t_rcd = spd_read(29);
209 /* The following timing calcs subtract 1 before deviding.
210 * this has effect of using ceiling intead of floor rounding,
211 * and also subtracting 1 to convert number to reg value
214 sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
216 sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
218 tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
219 if(tmp<1) SPD_ERR("SDRAM - unsupported prech to act time (Trp)\n");
220 sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
221 /* set LDF = 2 cycles, reg value = 1 */
222 sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
223 /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
224 tmp = ((t_rc - 1) / bus_period)-4;
227 sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
228 /* set RCD = t_rcd/bus_period*/
229 sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
232 /*------------------------------------------------------------------
233 configure RTR register
234 -------------------------------------------------------------------*/
237 tmp = spd_read(12) & 0x7f ; /* refresh type less self refresh bit */
258 SPD_ERR("SDRAM - Bad refresh period \n");
260 /* convert from nsec to bus cycles */
261 tmp = tmp/bus_period;
262 sdram0_rtr = (tmp & 0x3ff8)<< SDRAM0_RTR_SHIFT;
264 /*------------------------------------------------------------------
265 determine the number of banks used
266 -------------------------------------------------------------------*/
267 /* byte 7:6 is module data width */
269 SPD_ERR("SDRAM - unsupported module width\n");
272 SPD_ERR("SDRAM - unsupported module width\n");
274 bank_cnt=1; /* one bank per sdram side */
276 bank_cnt=2; /* need two banks per side */
278 bank_cnt=4; /* need four banks per side */
280 SPD_ERR("SDRAM - unsupported module width\n");
282 /* byte 5 is the module row count (refered to as dimm "sides") */
285 else if(tmp==2) bank_cnt *=2;
286 else if(tmp==4) bank_cnt *=4;
287 else bank_cnt = 8; /* 8 is an error code */
289 if(bank_cnt > 4) /* we only have 4 banks to work with */
290 SPD_ERR("SDRAM - unsupported module rows for this width\n");
292 /* now check for ECC ability of module. We only support ECC
293 * on 32 bit wide devices with 8 bit ECC.
295 if ( (spd_read(11)==2) && ((spd_read(6)==40) || (spd_read(14)==8)) ){
296 sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
304 /*------------------------------------------------------------------
306 -------------------------------------------------------------------*/
307 /* calculate total size and do sanity check */
309 total_size=1<<22; /* total_size = 4MB */
310 /* now multiply 4M by the smallest device roe density */
311 /* note that we don't support asymetric rows */
312 while (((tmp & 0x0001) == 0) && (tmp != 0)){
313 total_size= total_size<<1;
316 total_size *= spd_read(5); /* mult by module rows (dimm sides) */
318 /*------------------------------------------------------------------
319 map rows * cols * banks to a mode
320 -------------------------------------------------------------------*/
335 SPD_ERR("SDRAM - unsupported mode\n");
349 SPD_ERR("SDRAM - unsupported mode\n");
360 if (spd_read(17) ==2 )
369 SPD_ERR("SDRAM - unsupported mode\n");
373 SPD_ERR("SDRAM - unsupported mode\n");
376 /*------------------------------------------------------------------
377 using the calculated values, compute the bank
378 config register values.
379 -------------------------------------------------------------------*/
384 /* compute the size of each bank */
385 bank_size = total_size / bank_cnt;
386 /* convert bank size to bank size code for ppc4xx
387 by takeing log2(bank_size) - 22 */
388 tmp=bank_size; /* start with tmp = bank_size */
389 bank_code=0; /* and bank_code = 0 */
390 while (tmp>1){ /* this takes log2 of tmp */
391 bank_code++; /* and stores result in bank_code */
393 } /* bank_code is now log2(bank_size) */
394 bank_code-=22; /* subtract 22 to get the code */
396 tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
397 sdram0_b0cr = (bank_size) * 0 | tmp;
398 if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
399 if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
400 if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
404 * enable sdram controller DCE=1
405 * enable burst read prefetch to 32 bytes BRPF=2
406 * leave other functions off
409 /*------------------------------------------------------------------
410 now that we've done our calculations, we are ready to
411 program all the registers.
412 -------------------------------------------------------------------*/
415 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
416 /* disable memcontroller so updates work */
418 mtsdram0( mem_mcopt1, sdram0_cfg );
420 mtsdram0( mem_besra , sdram0_besr0 );
421 mtsdram0( mem_besrb , sdram0_besr1 );
422 mtsdram0( mem_rtr , sdram0_rtr );
423 mtsdram0( mem_pmit , sdram0_pmit );
424 mtsdram0( mem_mb0cf , sdram0_b0cr );
425 mtsdram0( mem_mb1cf , sdram0_b1cr );
426 mtsdram0( mem_mb2cf , sdram0_b2cr );
427 mtsdram0( mem_mb3cf , sdram0_b3cr );
428 mtsdram0( mem_sdtr1 , sdram0_tr );
429 mtsdram0( mem_ecccf , sdram0_ecccfg );
430 mtsdram0( mem_eccerr, sdram0_eccesr );
432 /* SDRAM have a power on delay, 500 micro should do */
434 sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
435 if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
436 mtsdram0( mem_mcopt1, sdram0_cfg );
439 /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
440 #ifdef MVISTA_MEM_BUG
441 if (total_size > 128*1024*1024 )
442 total_size=128*1024*1024;
447 int spd_read(uint addr)
451 if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
457 #else /* CONFIG_440 */
459 /*-----------------------------------------------------------------------------
460 | Memory Controller Options 0
461 +-----------------------------------------------------------------------------*/
462 #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
463 #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
464 #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
465 #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
466 #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
467 #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
468 #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
469 #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
470 #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
471 #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
472 #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
473 #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
475 /*-----------------------------------------------------------------------------
476 | Memory Controller Options 1
477 +-----------------------------------------------------------------------------*/
478 #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
479 #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
481 /*-----------------------------------------------------------------------------+
482 | SDRAM DEVPOT Options
483 +-----------------------------------------------------------------------------*/
484 #define SDRAM_DEVOPT_DLL 0x80000000
485 #define SDRAM_DEVOPT_DS 0x40000000
487 /*-----------------------------------------------------------------------------+
488 | SDRAM MCSTS Options
489 +-----------------------------------------------------------------------------*/
490 #define SDRAM_MCSTS_MRSC 0x80000000
491 #define SDRAM_MCSTS_SRMS 0x40000000
492 #define SDRAM_MCSTS_CIS 0x20000000
494 /*-----------------------------------------------------------------------------
495 | SDRAM Refresh Timer Register
496 +-----------------------------------------------------------------------------*/
497 #define SDRAM_RTR_RINT_MASK 0xFFFF0000
498 #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
499 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
501 /*-----------------------------------------------------------------------------+
502 | SDRAM UABus Base Address Reg
503 +-----------------------------------------------------------------------------*/
504 #define SDRAM_UABBA_UBBA_MASK 0x0000000F
506 /*-----------------------------------------------------------------------------+
507 | Memory Bank 0-7 configuration
508 +-----------------------------------------------------------------------------*/
509 #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
510 #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
511 #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
512 #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
513 #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
514 #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
515 #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
516 #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
517 #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
518 #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
519 #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
520 #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
521 #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
522 #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
523 #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
525 /*-----------------------------------------------------------------------------+
527 +-----------------------------------------------------------------------------*/
528 #define SDRAM_TR0_SDWR_MASK 0x80000000
529 #define SDRAM_TR0_SDWR_2_CLK 0x00000000
530 #define SDRAM_TR0_SDWR_3_CLK 0x80000000
531 #define SDRAM_TR0_SDWD_MASK 0x40000000
532 #define SDRAM_TR0_SDWD_0_CLK 0x00000000
533 #define SDRAM_TR0_SDWD_1_CLK 0x40000000
534 #define SDRAM_TR0_SDCL_MASK 0x01800000
535 #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
536 #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
537 #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
538 #define SDRAM_TR0_SDPA_MASK 0x000C0000
539 #define SDRAM_TR0_SDPA_2_CLK 0x00040000
540 #define SDRAM_TR0_SDPA_3_CLK 0x00080000
541 #define SDRAM_TR0_SDPA_4_CLK 0x000C0000
542 #define SDRAM_TR0_SDCP_MASK 0x00030000
543 #define SDRAM_TR0_SDCP_2_CLK 0x00000000
544 #define SDRAM_TR0_SDCP_3_CLK 0x00010000
545 #define SDRAM_TR0_SDCP_4_CLK 0x00020000
546 #define SDRAM_TR0_SDCP_5_CLK 0x00030000
547 #define SDRAM_TR0_SDLD_MASK 0x0000C000
548 #define SDRAM_TR0_SDLD_1_CLK 0x00000000
549 #define SDRAM_TR0_SDLD_2_CLK 0x00004000
550 #define SDRAM_TR0_SDRA_MASK 0x0000001C
551 #define SDRAM_TR0_SDRA_6_CLK 0x00000000
552 #define SDRAM_TR0_SDRA_7_CLK 0x00000004
553 #define SDRAM_TR0_SDRA_8_CLK 0x00000008
554 #define SDRAM_TR0_SDRA_9_CLK 0x0000000C
555 #define SDRAM_TR0_SDRA_10_CLK 0x00000010
556 #define SDRAM_TR0_SDRA_11_CLK 0x00000014
557 #define SDRAM_TR0_SDRA_12_CLK 0x00000018
558 #define SDRAM_TR0_SDRA_13_CLK 0x0000001C
559 #define SDRAM_TR0_SDRD_MASK 0x00000003
560 #define SDRAM_TR0_SDRD_2_CLK 0x00000001
561 #define SDRAM_TR0_SDRD_3_CLK 0x00000002
562 #define SDRAM_TR0_SDRD_4_CLK 0x00000003
564 /*-----------------------------------------------------------------------------+
566 +-----------------------------------------------------------------------------*/
567 #define SDRAM_TR1_RDSS_MASK 0xC0000000
568 #define SDRAM_TR1_RDSS_TR0 0x00000000
569 #define SDRAM_TR1_RDSS_TR1 0x40000000
570 #define SDRAM_TR1_RDSS_TR2 0x80000000
571 #define SDRAM_TR1_RDSS_TR3 0xC0000000
572 #define SDRAM_TR1_RDSL_MASK 0x00C00000
573 #define SDRAM_TR1_RDSL_STAGE1 0x00000000
574 #define SDRAM_TR1_RDSL_STAGE2 0x00400000
575 #define SDRAM_TR1_RDSL_STAGE3 0x00800000
576 #define SDRAM_TR1_RDCD_MASK 0x00000800
577 #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
578 #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
579 #define SDRAM_TR1_RDCT_MASK 0x000001FF
580 #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
581 #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
582 #define SDRAM_TR1_RDCT_MIN 0x00000000
583 #define SDRAM_TR1_RDCT_MAX 0x000001FF
585 /*-----------------------------------------------------------------------------+
586 | SDRAM WDDCTR Options
587 +-----------------------------------------------------------------------------*/
588 #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
589 #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
590 #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
591 #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
592 #define SDRAM_WDDCTR_DCD_MASK 0x000001FF
594 /*-----------------------------------------------------------------------------+
595 | SDRAM CLKTR Options
596 +-----------------------------------------------------------------------------*/
597 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
598 #define SDRAM_CLKTR_CLKP_0DEG 0x00000000
599 #define SDRAM_CLKTR_CLKP_90DEG 0x40000000
600 #define SDRAM_CLKTR_CLKP_180DEG 0x80000000
601 #define SDRAM_CLKTR_DCDT_MASK 0x000001FF
603 /*-----------------------------------------------------------------------------+
604 | SDRAM DLYCAL Options
605 +-----------------------------------------------------------------------------*/
606 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
607 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
608 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
610 /*-----------------------------------------------------------------------------+
612 +-----------------------------------------------------------------------------*/
613 #define DEFAULT_SPD_ADDR1 0x53
614 #define DEFAULT_SPD_ADDR2 0x52
615 #define ONE_BILLION 1000000000
616 #define MAXBANKS 4 /* at most 4 dimm banks */
617 #define MAX_SPD_BYTES 256
618 #define NUMHALFCYCLES 4
619 #define NUMMEMTESTS 8
620 #define NUMMEMWORDS 8
625 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
626 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
627 0xFFFFFFFF, 0xFFFFFFFF},
628 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
629 0x00000000, 0x00000000},
630 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
631 0x55555555, 0x55555555},
632 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
633 0xAAAAAAAA, 0xAAAAAAAA},
634 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
635 0x5A5A5A5A, 0x5A5A5A5A},
636 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
637 0xA5A5A5A5, 0xA5A5A5A5},
638 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
639 0x55AA55AA, 0x55AA55AA},
640 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
641 0xAA55AA55, 0xAA55AA55}
645 unsigned char spd_read(uchar chip, uint addr);
647 void get_spd_info(unsigned long* dimm_populated,
648 unsigned char* iic0_dimm_addr,
649 unsigned long num_dimm_banks);
652 (unsigned long* dimm_populated,
653 unsigned char* iic0_dimm_addr,
654 unsigned long num_dimm_banks);
657 (unsigned long* dimm_populated,
658 unsigned char* iic0_dimm_addr,
659 unsigned long num_dimm_banks);
661 void program_cfg0(unsigned long* dimm_populated,
662 unsigned char* iic0_dimm_addr,
663 unsigned long num_dimm_banks);
665 void program_cfg1(unsigned long* dimm_populated,
666 unsigned char* iic0_dimm_addr,
667 unsigned long num_dimm_banks);
669 void program_rtr (unsigned long* dimm_populated,
670 unsigned char* iic0_dimm_addr,
671 unsigned long num_dimm_banks);
673 void program_tr0 (unsigned long* dimm_populated,
674 unsigned char* iic0_dimm_addr,
675 unsigned long num_dimm_banks);
677 void program_tr1 (void);
679 void program_ecc (unsigned long num_bytes);
682 long program_bxcr(unsigned long* dimm_populated,
683 unsigned char* iic0_dimm_addr,
684 unsigned long num_dimm_banks);
687 * This function is reading data from the DIMM module EEPROM over the SPD bus
688 * and uses that to program the sdram controller.
690 * This works on boards that has the same schematics that the IBM walnut has.
692 * BUG: Don't handle ECC memory
693 * BUG: A few values in the TR register is currently hardcoded
696 long int spd_sdram(void) {
697 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
698 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
699 unsigned long total_size;
702 unsigned long num_dimm_banks; /* on board dimm banks */
704 num_dimm_banks = sizeof(iic0_dimm_addr);
707 * Make sure I2C controller is initialized
710 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
713 * Read the SPD information using I2C interface. Check to see if the
714 * DIMM slots are populated.
716 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
719 * Check the memory type for the dimms plugged.
721 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
724 * Check the voltage type for the dimms plugged.
726 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
729 * program 440GP SDRAM controller options (SDRAM0_CFG0)
731 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
734 * program 440GP SDRAM controller options (SDRAM0_CFG1)
736 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
739 * program SDRAM refresh register (SDRAM0_RTR)
741 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
744 * program SDRAM Timing Register 0 (SDRAM0_TR0)
746 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
749 * program the BxCR registers to find out total sdram installed
751 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
755 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
757 mtsdram(mem_clktr, 0x40000000);
760 * delay to ensure 200 usec has elapsed
765 * enable the memory controller
767 mfsdram(mem_cfg0, cfg0);
768 mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
771 * wait for SDRAM_CFG0_DC_EN to complete
774 mfsdram(mem_mcsts, mcsts);
775 if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
781 * program SDRAM Timing Register 1, adding some delays
786 * if ECC is enabled, initialize parity bits
792 unsigned char spd_read(uchar chip, uint addr) {
793 unsigned char data[2];
795 if (i2c_read(chip, addr, 1, data, 1) == 0)
801 void get_spd_info(unsigned long* dimm_populated,
802 unsigned char* iic0_dimm_addr,
803 unsigned long num_dimm_banks)
805 unsigned long dimm_num;
806 unsigned long dimm_found;
807 unsigned char num_of_bytes;
808 unsigned char total_size;
811 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
815 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
816 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
818 if ((num_of_bytes != 0) && (total_size != 0)) {
819 dimm_populated[dimm_num] = TRUE;
822 printf("DIMM slot %lu: populated\n", dimm_num);
826 dimm_populated[dimm_num] = FALSE;
828 printf("DIMM slot %lu: Not populated\n", dimm_num);
833 if (dimm_found == FALSE) {
834 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
839 void check_mem_type(unsigned long* dimm_populated,
840 unsigned char* iic0_dimm_addr,
841 unsigned long num_dimm_banks)
843 unsigned long dimm_num;
844 unsigned char dimm_type;
846 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
847 if (dimm_populated[dimm_num] == TRUE) {
848 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
852 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
856 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
858 printf("Only DDR SDRAM DIMMs are supported.\n");
859 printf("Replace the DIMM module with a supported DIMM.\n\n");
868 void check_volt_type(unsigned long* dimm_populated,
869 unsigned char* iic0_dimm_addr,
870 unsigned long num_dimm_banks)
872 unsigned long dimm_num;
873 unsigned long voltage_type;
875 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
876 if (dimm_populated[dimm_num] == TRUE) {
877 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
878 if (voltage_type != 0x04) {
879 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
885 printf("DIMM %lu voltage level supported.\n", dimm_num);
893 void program_cfg0(unsigned long* dimm_populated,
894 unsigned char* iic0_dimm_addr,
895 unsigned long num_dimm_banks)
897 unsigned long dimm_num;
899 unsigned long ecc_enabled;
901 unsigned char attributes;
902 unsigned long data_width;
903 unsigned long dimm_32bit;
904 unsigned long dimm_64bit;
907 * get Memory Controller Options 0 data
909 mfsdram(mem_cfg0, cfg0);
914 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
915 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
916 SDRAM_CFG0_DMWD_MASK |
917 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
921 * FIXME: assume the DDR SDRAMs in both banks are the same
924 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
925 if (dimm_populated[dimm_num] == TRUE) {
926 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
932 * program Registered DIMM Enable
934 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
935 if ((attributes & 0x02) != 0x00) {
936 cfg0 |= SDRAM_CFG0_RDEN;
940 * program DDR SDRAM Data Width
943 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
944 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
945 if (data_width == 64 || data_width == 72) {
947 cfg0 |= SDRAM_CFG0_DMWD_64;
949 else if (data_width == 32 || data_width == 40) {
951 cfg0 |= SDRAM_CFG0_DMWD_32;
954 printf("WARNING: DIMM with datawidth of %lu bits.\n",
956 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
964 * program Memory Data Error Checking
966 if (ecc_enabled == TRUE) {
967 cfg0 |= SDRAM_CFG0_MCHK_GEN;
970 cfg0 |= SDRAM_CFG0_MCHK_NON;
974 * program Page Management Unit
976 cfg0 |= SDRAM_CFG0_PMUD;
979 * program Memory Controller Options 0
980 * Note: DCEN must be enabled after all DDR SDRAM controller
981 * configuration registers get initialized.
983 mtsdram(mem_cfg0, cfg0);
986 void program_cfg1(unsigned long* dimm_populated,
987 unsigned char* iic0_dimm_addr,
988 unsigned long num_dimm_banks)
991 mfsdram(mem_cfg1, cfg1);
994 * Self-refresh exit, disable PM
996 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
999 * program Memory Controller Options 1
1001 mtsdram(mem_cfg1, cfg1);
1004 void program_rtr (unsigned long* dimm_populated,
1005 unsigned char* iic0_dimm_addr,
1006 unsigned long num_dimm_banks)
1008 unsigned long dimm_num;
1009 unsigned long bus_period_x_10;
1010 unsigned long refresh_rate = 0;
1011 unsigned char refresh_rate_type;
1012 unsigned long refresh_interval;
1013 unsigned long sdram_rtr;
1014 PPC440_SYS_INFO sys_info;
1017 * get the board info
1019 get_sys_info(&sys_info);
1020 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1023 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1024 if (dimm_populated[dimm_num] == TRUE) {
1025 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1026 switch (refresh_rate_type) {
1028 refresh_rate = 15625;
1031 refresh_rate = 15625/4;
1034 refresh_rate = 15625/2;
1037 refresh_rate = 15626*2;
1040 refresh_rate = 15625*4;
1043 refresh_rate = 15625*8;
1046 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1048 printf("Replace the DIMM module with a supported DIMM.\n");
1056 refresh_interval = refresh_rate * 10 / bus_period_x_10;
1057 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
1060 * program Refresh Timer Register (SDRAM0_RTR)
1062 mtsdram(mem_rtr, sdram_rtr);
1065 void program_tr0 (unsigned long* dimm_populated,
1066 unsigned char* iic0_dimm_addr,
1067 unsigned long num_dimm_banks)
1069 unsigned long dimm_num;
1071 unsigned char wcsbc;
1072 unsigned char t_rp_ns;
1073 unsigned char t_rcd_ns;
1074 unsigned char t_ras_ns;
1075 unsigned long t_rp_clk;
1076 unsigned long t_ras_rcd_clk;
1077 unsigned long t_rcd_clk;
1078 unsigned long t_rfc_clk;
1079 unsigned long plb_check;
1080 unsigned char cas_bit;
1081 unsigned long cas_index;
1082 unsigned char cas_2_0_available;
1083 unsigned char cas_2_5_available;
1084 unsigned char cas_3_0_available;
1085 unsigned long cycle_time_ns_x_10[3];
1086 unsigned long tcyc_3_0_ns_x_10;
1087 unsigned long tcyc_2_5_ns_x_10;
1088 unsigned long tcyc_2_0_ns_x_10;
1089 unsigned long tcyc_reg;
1090 unsigned long bus_period_x_10;
1091 PPC440_SYS_INFO sys_info;
1092 unsigned long residue;
1095 * get the board info
1097 get_sys_info(&sys_info);
1098 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1101 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1103 mfsdram(mem_tr0, tr0);
1104 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1105 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1106 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1107 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1116 cas_2_0_available = TRUE;
1117 cas_2_5_available = TRUE;
1118 cas_3_0_available = TRUE;
1119 tcyc_2_0_ns_x_10 = 0;
1120 tcyc_2_5_ns_x_10 = 0;
1121 tcyc_3_0_ns_x_10 = 0;
1123 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1124 if (dimm_populated[dimm_num] == TRUE) {
1125 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1126 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1127 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1128 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1129 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1131 for (cas_index = 0; cas_index < 3; cas_index++) {
1132 switch (cas_index) {
1134 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1137 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1140 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1144 if ((tcyc_reg & 0x0F) >= 10) {
1145 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1150 cycle_time_ns_x_10[cas_index] =
1151 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1156 if ((cas_bit & 0x80) != 0) {
1159 else if ((cas_bit & 0x40) != 0) {
1162 else if ((cas_bit & 0x20) != 0) {
1166 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1167 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1171 if (cas_index != 0) {
1174 cas_3_0_available = FALSE;
1177 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1178 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1182 if (cas_index != 0) {
1185 cas_2_5_available = FALSE;
1188 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1189 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1193 if (cas_index != 0) {
1196 cas_2_0_available = FALSE;
1204 * Program SD_WR and SD_WCSBC fields
1206 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
1209 tr0 |= SDRAM_TR0_SDWD_0_CLK;
1212 tr0 |= SDRAM_TR0_SDWD_1_CLK;
1217 * Program SD_CASL field
1219 if ((cas_2_0_available == TRUE) &&
1220 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1221 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1223 else if((cas_2_5_available == TRUE) &&
1224 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1225 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1227 else if((cas_3_0_available == TRUE) &&
1228 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1229 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1232 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1233 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1234 printf("Make sure the PLB speed is within the supported range.\n");
1239 * Calculate Trp in clock cycles and round up if necessary
1240 * Program SD_PTA field
1242 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1243 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1244 if (sys_info.freqPLB != plb_check) {
1247 switch ((unsigned long)t_rp_clk) {
1251 tr0 |= SDRAM_TR0_SDPA_2_CLK;
1254 tr0 |= SDRAM_TR0_SDPA_3_CLK;
1257 tr0 |= SDRAM_TR0_SDPA_4_CLK;
1262 * Program SD_CTP field
1264 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1265 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1266 if (sys_info.freqPLB != plb_check) {
1269 switch (t_ras_rcd_clk) {
1273 tr0 |= SDRAM_TR0_SDCP_2_CLK;
1276 tr0 |= SDRAM_TR0_SDCP_3_CLK;
1279 tr0 |= SDRAM_TR0_SDCP_4_CLK;
1282 tr0 |= SDRAM_TR0_SDCP_5_CLK;
1287 * Program SD_LDF field
1289 tr0 |= SDRAM_TR0_SDLD_2_CLK;
1292 * Program SD_RFTA field
1293 * FIXME tRFC hardcoded as 75 nanoseconds
1295 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1296 residue = sys_info.freqPLB % (ONE_BILLION / 75);
1297 if (residue >= (ONE_BILLION / 150)) {
1300 switch (t_rfc_clk) {
1308 tr0 |= SDRAM_TR0_SDRA_6_CLK;
1311 tr0 |= SDRAM_TR0_SDRA_7_CLK;
1314 tr0 |= SDRAM_TR0_SDRA_8_CLK;
1317 tr0 |= SDRAM_TR0_SDRA_9_CLK;
1320 tr0 |= SDRAM_TR0_SDRA_10_CLK;
1323 tr0 |= SDRAM_TR0_SDRA_11_CLK;
1326 tr0 |= SDRAM_TR0_SDRA_12_CLK;
1329 tr0 |= SDRAM_TR0_SDRA_13_CLK;
1334 * Program SD_RCD field
1336 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1337 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1338 if (sys_info.freqPLB != plb_check) {
1341 switch (t_rcd_clk) {
1345 tr0 |= SDRAM_TR0_SDRD_2_CLK;
1348 tr0 |= SDRAM_TR0_SDRD_3_CLK;
1351 tr0 |= SDRAM_TR0_SDRD_4_CLK;
1356 printf("tr0: %x\n", tr0);
1358 mtsdram(mem_tr0, tr0);
1361 void program_tr1 (void)
1366 unsigned long ecc_temp;
1367 unsigned long dlycal;
1368 unsigned long dly_val;
1369 unsigned long i, j, k;
1370 unsigned long bxcr_num;
1371 unsigned long max_pass_length;
1372 unsigned long current_pass_length;
1373 unsigned long current_fail_length;
1374 unsigned long current_start;
1375 unsigned long rdclt;
1376 unsigned long rdclt_offset;
1380 unsigned char window_found;
1381 unsigned char fail_found;
1382 unsigned char pass_found;
1383 unsigned long * membase;
1384 PPC440_SYS_INFO sys_info;
1387 * get the board info
1389 get_sys_info(&sys_info);
1392 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1394 mfsdram(mem_tr1, tr1);
1395 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1396 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1398 mfsdram(mem_tr0, tr0);
1399 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1400 (sys_info.freqPLB > 100000000)) {
1401 tr1 |= SDRAM_TR1_RDSS_TR2;
1402 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1403 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1406 tr1 |= SDRAM_TR1_RDSS_TR1;
1407 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1408 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1412 * save CFG0 ECC setting to a temporary variable and turn ECC off
1414 mfsdram(mem_cfg0, cfg0);
1415 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1416 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1419 * get the delay line calibration register value
1421 mfsdram(mem_dlycal, dlycal);
1422 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1424 max_pass_length = 0;
1427 current_pass_length = 0;
1428 current_fail_length = 0;
1431 window_found = FALSE;
1435 printf("Starting memory test ");
1437 for (k = 0; k < NUMHALFCYCLES; k++) {
1438 for (rdclt = 0; rdclt < dly_val; rdclt++) {
1440 * Set the timing reg for the test.
1442 mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1444 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1445 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1446 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1447 /* Bank is enabled */
1448 membase = (unsigned long*)
1449 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1452 * Run the short memory test
1454 for (i = 0; i < NUMMEMTESTS; i++) {
1455 for (j = 0; j < NUMMEMWORDS; j++) {
1456 membase[j] = test[i][j];
1457 ppcDcbf((unsigned long)&(membase[j]));
1460 for (j = 0; j < NUMMEMWORDS; j++) {
1461 if (membase[j] != test[i][j]) {
1462 ppcDcbf((unsigned long)&(membase[j]));
1465 ppcDcbf((unsigned long)&(membase[j]));
1468 if (j < NUMMEMWORDS) {
1474 * see if the rdclt value passed
1476 if (i < NUMMEMTESTS) {
1482 if (bxcr_num == MAXBXCR) {
1483 if (fail_found == TRUE) {
1485 if (current_pass_length == 0) {
1486 current_start = rdclt_offset + rdclt;
1489 current_fail_length = 0;
1490 current_pass_length++;
1492 if (current_pass_length > max_pass_length) {
1493 max_pass_length = current_pass_length;
1494 max_start = current_start;
1495 max_end = rdclt_offset + rdclt;
1500 current_pass_length = 0;
1501 current_fail_length++;
1503 if (current_fail_length >= (dly_val>>2)) {
1504 if (fail_found == FALSE) {
1507 else if (pass_found == TRUE) {
1508 window_found = TRUE;
1517 if (window_found == TRUE) {
1521 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1522 rdclt_offset += dly_val;
1529 * make sure we find the window
1531 if (window_found == FALSE) {
1532 printf("ERROR: Cannot determine a common read delay.\n");
1537 * restore the orignal ECC setting
1539 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1542 * set the SDRAM TR1 RDCD value
1544 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1545 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1546 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1549 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1553 * set the SDRAM TR1 RDCLT value
1555 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1556 while (max_end >= (dly_val<<1)) {
1557 max_end -= (dly_val<<1);
1558 max_start -= (dly_val<<1);
1561 rdclt_average = ((max_start + max_end) >> 1);
1562 if (rdclt_average >= 0x60)
1565 if (rdclt_average < 0) {
1569 if (rdclt_average >= dly_val) {
1570 rdclt_average -= dly_val;
1571 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1573 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1576 printf("tr1: %x\n", tr1);
1579 * program SDRAM Timing Register 1 TR1
1581 mtsdram(mem_tr1, tr1);
1584 unsigned long program_bxcr(unsigned long* dimm_populated,
1585 unsigned char* iic0_dimm_addr,
1586 unsigned long num_dimm_banks)
1588 unsigned long dimm_num;
1589 unsigned long bxcr_num;
1590 unsigned long bank_base_addr;
1591 unsigned long bank_size_bytes;
1595 unsigned char num_row_addr;
1596 unsigned char num_col_addr;
1597 unsigned char num_banks;
1598 unsigned char bank_size_id;
1602 * Set the BxCR regs. First, wipe out the bank config registers.
1604 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1605 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1606 mtdcr(memcfgd, 0x00000000);
1610 * reset the bank_base address
1612 bank_base_addr = CFG_SDRAM_BASE;
1614 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1615 if (dimm_populated[dimm_num] == TRUE) {
1616 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1617 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1618 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1619 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1622 * Set the SDRAM0_BxCR regs
1625 bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1626 switch (bank_size_id) {
1628 cr |= SDRAM_BXCR_SDSZ_8;
1631 cr |= SDRAM_BXCR_SDSZ_16;
1634 cr |= SDRAM_BXCR_SDSZ_32;
1637 cr |= SDRAM_BXCR_SDSZ_64;
1640 cr |= SDRAM_BXCR_SDSZ_128;
1643 cr |= SDRAM_BXCR_SDSZ_256;
1646 cr |= SDRAM_BXCR_SDSZ_512;
1649 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1651 printf("ERROR: Unsupported value for the banksize: %d.\n",
1653 printf("Replace the DIMM module with a supported DIMM.\n\n");
1657 switch (num_col_addr) {
1659 cr |= SDRAM_BXCR_SDAM_1;
1662 cr |= SDRAM_BXCR_SDAM_2;
1665 cr |= SDRAM_BXCR_SDAM_3;
1668 cr |= SDRAM_BXCR_SDAM_4;
1671 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1673 printf("ERROR: Unsupported value for number of "
1674 "column addresses: %d.\n", num_col_addr);
1675 printf("Replace the DIMM module with a supported DIMM.\n\n");
1682 cr |= SDRAM_BXCR_SDBE;
1684 /*------------------------------------------------------------------
1685 | This next section is hardware dependent and must be programmed
1686 | to match the hardware.
1687 +-----------------------------------------------------------------*/
1688 if (dimm_num == 0) {
1689 for (i = 0; i < num_banks; i++) {
1690 mtdcr(memcfga, mem_b0cr + (i << 2));
1691 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1692 SDRAM_BXCR_SDSZ_MASK |
1693 SDRAM_BXCR_SDAM_MASK |
1696 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1698 bank_base_addr += bank_size_bytes;
1702 for (i = 0; i < num_banks; i++) {
1703 mtdcr(memcfga, mem_b2cr + (i << 2));
1704 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1705 SDRAM_BXCR_SDSZ_MASK |
1706 SDRAM_BXCR_SDAM_MASK |
1709 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1711 bank_base_addr += bank_size_bytes;
1717 return(bank_base_addr);
1720 void program_ecc (unsigned long num_bytes)
1722 unsigned long bank_base_addr;
1723 unsigned long current_address;
1724 unsigned long end_address;
1725 unsigned long address_increment;
1729 * get Memory Controller Options 0 data
1731 mfsdram(mem_cfg0, cfg0);
1734 * reset the bank_base address
1736 bank_base_addr = CFG_SDRAM_BASE;
1738 if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1739 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1740 SDRAM_CFG0_MCHK_GEN);
1742 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1743 address_increment = 4;
1746 address_increment = 8;
1749 current_address = (unsigned long)(bank_base_addr);
1750 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1752 while (current_address < end_address) {
1753 *((unsigned long*)current_address) = 0x00000000;
1754 current_address += address_increment;
1757 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1758 SDRAM_CFG0_MCHK_CHK);
1762 #endif /* CONFIG_440 */
1764 #endif /* CONFIG_SPD_EEPROM */