3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <ppc_asm.tmpl>
27 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
31 #define ONE_BILLION 1000000000
34 #if defined(CONFIG_405GP) || defined(CONFIG_405CR)
36 void get_sys_info (PPC405_SYS_INFO * sysInfo)
39 unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
45 * Read PLL Mode register
47 pllmr = mfdcr (pllmd);
50 * Read Pin Strapping register
57 sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
62 sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
63 if (sysInfo->pllFbkDiv == 0) {
64 sysInfo->pllFbkDiv = 16;
70 sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
75 sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
78 * Determine EXTBUS_DIV.
80 sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
85 sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
88 * Check if PPC405GPr used (mask minor revision field)
90 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
92 * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
94 sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
97 * Determine factor m depending on PLL feedback clock source
99 if (!(psr & PSR_PCI_ASYNC_EN)) {
100 if (psr & PSR_NEW_MODE_EN) {
102 * sync pci clock used as feedback (new mode)
104 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
107 * sync pci clock used as feedback (legacy mode)
109 m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
111 } else if (psr & PSR_NEW_MODE_EN) {
112 if (psr & PSR_PERCLK_SYNC_MODE_EN) {
114 * PerClk used as feedback (new mode)
116 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
119 * CPU clock used as feedback (new mode)
121 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
123 } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
125 * PerClk used as feedback (legacy mode)
127 m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
130 * PLB clock used as feedback (legacy mode)
132 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
135 sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
136 (unsigned long long)sysClkPeriodPs;
137 sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv;
138 sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
141 * Check pllFwdDiv to see if running in bypass mode where the CPU speed
142 * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
143 * to make sure it is within the proper range.
144 * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
145 * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
147 if (sysInfo->pllFwdDiv == 1) {
148 sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
149 sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
151 sysInfo->freqVCOHz = ( 1000000000000LL *
152 (unsigned long long)sysInfo->pllFwdDiv *
153 (unsigned long long)sysInfo->pllFbkDiv *
154 (unsigned long long)sysInfo->pllPlbDiv
155 ) / (unsigned long long)sysClkPeriodPs;
156 sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) /
157 sysInfo->pllFbkDiv)) * 10000;
158 sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
164 /********************************************
166 * return OPB bus freq in Hz
167 *********************************************/
168 ulong get_OPB_freq (void)
172 PPC405_SYS_INFO sys_info;
174 get_sys_info (&sys_info);
175 val = sys_info.freqPLB / sys_info.pllOpbDiv;
181 /********************************************
183 * return PCI bus freq in Hz
184 *********************************************/
185 ulong get_PCI_freq (void)
188 PPC405_SYS_INFO sys_info;
190 get_sys_info (&sys_info);
191 val = sys_info.freqPLB / sys_info.pllPciDiv;
196 #elif defined(CONFIG_440)
197 #if !defined(CONFIG_440_GX)
198 void get_sys_info (sys_info_t * sysInfo)
204 /* Extract configured divisors */
205 strp0 = mfdcr( cpc0_strp0 );
206 sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
207 sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
208 temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
209 sysInfo->pllFbkDiv = temp ? temp : 16;
210 sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
211 sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
213 /* Calculate 'M' based on feedback source */
214 if( strp0 & PLLSYS0_EXTSL_MASK )
215 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
217 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
219 /* Now calculate the individual clocks */
220 sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
221 sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
222 sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
223 if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
224 sysInfo->freqPLB >>= 1;
225 sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
226 sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
230 void get_sys_info (sys_info_t * sysInfo)
238 unsigned long prbdv0;
240 /* Extract configured divisors */
241 mfsdr( sdr_sdstp0,strp0 );
242 mfsdr( sdr_sdstp1,strp1 );
244 temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
245 sysInfo->pllFwdDivA = temp ? temp : 16 ;
246 temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
247 sysInfo->pllFwdDivB = temp ? temp: 8 ;
248 temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
249 sysInfo->pllFbkDiv = temp ? temp : 32;
250 temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
251 sysInfo->pllOpbDiv = temp ? temp : 4;
252 temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
253 sysInfo->pllExtBusDiv = temp ? temp : 4;
254 prbdv0 = (strp0 >> 2) & 0x7;
256 /* Calculate 'M' based on feedback source */
257 temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
258 temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
259 lfdiv = temp1 ? temp1 : 64;
260 if (temp == 0) { /* PLL output */
261 /* Figure which pll to use */
262 temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
264 m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
266 m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
268 else if (temp == 1) /* CPU output */
269 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
271 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
273 /* Now calculate the individual clocks */
274 sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
275 sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
276 sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
277 sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
278 sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
283 ulong get_OPB_freq (void)
287 get_sys_info (&sys_info);
288 return sys_info.freqOPB;
291 #elif defined(CONFIG_XILINX_ML300)
292 extern void get_sys_info (sys_info_t * sysInfo);
293 extern ulong get_PCI_freq (void);
295 #elif defined(CONFIG_405)
297 void get_sys_info (sys_info_t * sysInfo) {
299 sysInfo->freqVCOMhz=3125000;
300 sysInfo->freqProcessor=12*1000*1000;
301 sysInfo->freqPLB=50*1000*1000;
302 sysInfo->freqPCI=66*1000*1000;
306 #elif defined(CONFIG_405EP)
307 void get_sys_info (PPC405_SYS_INFO * sysInfo)
309 unsigned long pllmr0;
310 unsigned long pllmr1;
311 unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
313 unsigned long pllmr0_ccdv;
316 * Read PLL Mode registers
318 pllmr0 = mfdcr (cpc0_pllmr0);
319 pllmr1 = mfdcr (cpc0_pllmr1);
322 * Determine forward divider A
324 sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);
327 * Determine forward divider B (should be equal to A)
329 sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);
334 sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
335 if (sysInfo->pllFbkDiv == 0) {
336 sysInfo->pllFbkDiv = 16;
342 sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
347 sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;
350 * Determine EXTBUS_DIV.
352 sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;
357 sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;
360 * Determine the M factor
362 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
365 * Determine VCO clock frequency
367 sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
368 (unsigned long long)sysClkPeriodPs;
371 * Determine CPU clock frequency
373 pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
374 if (pllmr1 & PLLMR1_SSCS_MASK) {
376 * This is true if FWDVA == FWDVB:
377 * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
380 sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
381 / sysInfo->pllFwdDiv / pllmr0_ccdv;
383 sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
387 * Determine PLB clock frequency
389 sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
393 /********************************************
395 * return OPB bus freq in Hz
396 *********************************************/
397 ulong get_OPB_freq (void)
401 PPC405_SYS_INFO sys_info;
403 get_sys_info (&sys_info);
404 val = sys_info.freqPLB / sys_info.pllOpbDiv;
410 /********************************************
412 * return PCI bus freq in Hz
413 *********************************************/
414 ulong get_PCI_freq (void)
417 PPC405_SYS_INFO sys_info;
419 get_sys_info (&sys_info);
420 val = sys_info.freqPLB / sys_info.pllPciDiv;
426 int get_clocks (void)
428 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
429 DECLARE_GLOBAL_DATA_PTR;
433 get_sys_info (&sys_info);
434 gd->cpu_clk = sys_info.freqProcessor;
435 gd->bus_clk = sys_info.freqPLB;
437 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
440 DECLARE_GLOBAL_DATA_PTR;
442 gd->cpu_clk = 66000000;
443 gd->bus_clk = 66000000;
449 /********************************************
451 * return PLB bus freq in Hz
452 *********************************************/
453 ulong get_bus_freq (ulong dummy)
457 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
460 get_sys_info (&sys_info);
461 val = sys_info.freqPLB;
463 #elif defined(CONFIG_IOP480)
468 # error get_bus_freq() not implemented