2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
46 *-------------------------------------------------------------------------------
49 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 * The processor starts at 0xfffffffc and the code is executed
54 * in memory, but as long we don't jump around before relocating.
55 * board_init lies at a quite high address and when the cpu has
56 * jumped there, everything is ok.
57 * This works because the cpu gives the FLASH (CS0) the whole
58 * address space at startup, and board_init lies as a echo of
59 * the flash somewhere up there in the memorymap.
61 * board_init will change CS0 to be positioned at the correct
62 * address and (s)dram will be positioned at address 0
68 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
70 #include <ppc_asm.tmpl>
73 #include <asm/cache.h>
76 #ifndef CONFIG_IDENT_STRING
77 #define CONFIG_IDENT_STRING ""
80 #ifdef CONFIG_SYS_INIT_DCACHE_CS
81 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
84 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
85 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
86 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
89 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
92 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
93 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
94 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
97 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
100 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
101 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
102 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
105 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
108 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
109 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
110 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
113 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
116 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
117 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
118 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
121 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
124 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
125 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
126 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
129 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
132 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
133 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
134 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
137 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
140 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
141 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
142 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
152 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
153 * used as temporary stack pointer for the primordial stack
155 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
156 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
157 EBC_BXAP_TWT_ENCODE(7) | \
158 EBC_BXAP_BCE_DISABLE | \
159 EBC_BXAP_BCT_2TRANS | \
160 EBC_BXAP_CSN_ENCODE(0) | \
161 EBC_BXAP_OEN_ENCODE(0) | \
162 EBC_BXAP_WBN_ENCODE(0) | \
163 EBC_BXAP_WBF_ENCODE(0) | \
164 EBC_BXAP_TH_ENCODE(2) | \
165 EBC_BXAP_RE_DISABLED | \
166 EBC_BXAP_SOR_NONDELAYED | \
167 EBC_BXAP_BEM_WRITEONLY | \
168 EBC_BXAP_PEN_DISABLED)
169 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
170 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
171 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
175 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
176 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
177 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
179 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
181 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
182 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
186 * Unless otherwise overriden, enable two 128MB cachable instruction regions
187 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
188 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
190 #if !defined(CONFIG_SYS_FLASH_BASE)
191 /* If not already defined, set it to the "last" 128MByte region */
192 # define CONFIG_SYS_FLASH_BASE 0xf8000000
194 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
195 # define CONFIG_SYS_ICACHE_SACR_VALUE \
196 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
197 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
198 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
199 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
201 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
202 # define CONFIG_SYS_DCACHE_SACR_VALUE \
204 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
206 #define function_prolog(func_name) .text; \
210 #define function_epilog(func_name) .type func_name,@function; \
211 .size func_name,.-func_name
213 /* We don't want the MMU yet.
216 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
219 .extern ext_bus_cntlr_init
220 #ifdef CONFIG_NAND_U_BOOT
221 .extern reconfig_tlb0
225 * Set up GOT: Global Offset Table
227 * Use r14 to access the GOT
229 #if !defined(CONFIG_NAND_SPL)
231 GOT_ENTRY(_GOT2_TABLE_)
232 GOT_ENTRY(_FIXUP_TABLE_)
235 GOT_ENTRY(_start_of_vectors)
236 GOT_ENTRY(_end_of_vectors)
237 GOT_ENTRY(transfer_to_handler)
239 GOT_ENTRY(__init_end)
241 GOT_ENTRY(__bss_start)
243 #endif /* CONFIG_NAND_SPL */
245 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
247 * NAND U-Boot image is started from offset 0
250 #if defined(CONFIG_440)
254 bl cpu_init_f /* run low-level CPU init code (from Flash) */
259 * 440 Startup -- on reset only the top 4k of the effective
260 * address space is mapped in by an entry in the instruction
261 * and data shadow TLB. The .bootpg section is located in the
262 * top 4k & does only what's necessary to map in the the rest
263 * of the boot rom. Once the boot rom is mapped in we can
264 * proceed with normal startup.
266 * NOTE: CS0 only covers the top 2MB of the effective address
270 #if defined(CONFIG_440)
271 #if !defined(CONFIG_NAND_SPL)
272 .section .bootpg,"ax"
276 /**************************************************************************/
278 /*--------------------------------------------------------------------+
279 | 440EPX BUP Change - Hardware team request
280 +--------------------------------------------------------------------*/
281 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
286 /*----------------------------------------------------------------+
287 | Core bug fix. Clear the esr
288 +-----------------------------------------------------------------*/
291 /*----------------------------------------------------------------*/
292 /* Clear and set up some registers. */
293 /*----------------------------------------------------------------*/
294 iccci r0,r0 /* NOTE: operands not used for 440 */
295 dccci r0,r0 /* NOTE: operands not used for 440 */
302 /* NOTE: 440GX adds machine check status regs */
303 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
310 /*----------------------------------------------------------------*/
312 /*----------------------------------------------------------------*/
313 /* Disable store gathering & broadcast, guarantee inst/data
314 * cache block touch, force load/store alignment
315 * (see errata 1.12: 440_33)
317 lis r1,0x0030 /* store gathering & broadcast disable */
318 ori r1,r1,0x6000 /* cache touch */
321 /*----------------------------------------------------------------*/
322 /* Initialize debug */
323 /*----------------------------------------------------------------*/
325 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
326 bne skip_debug_init /* if set, don't clear debug register */
339 mtspr dbsr,r1 /* Clear all valid bits */
342 #if defined (CONFIG_440SPE)
343 /*----------------------------------------------------------------+
344 | Initialize Core Configuration Reg1.
345 | a. ICDPEI: Record even parity. Normal operation.
346 | b. ICTPEI: Record even parity. Normal operation.
347 | c. DCTPEI: Record even parity. Normal operation.
348 | d. DCDPEI: Record even parity. Normal operation.
349 | e. DCUPEI: Record even parity. Normal operation.
350 | f. DCMPEI: Record even parity. Normal operation.
351 | g. FCOM: Normal operation
352 | h. MMUPEI: Record even parity. Normal operation.
353 | i. FFF: Flush only as much data as necessary.
354 | j. TCS: Timebase increments from CPU clock.
355 +-----------------------------------------------------------------*/
359 /*----------------------------------------------------------------+
360 | Reset the timebase.
361 | The previous write to CCR1 sets the timebase source.
362 +-----------------------------------------------------------------*/
367 /*----------------------------------------------------------------*/
368 /* Setup interrupt vectors */
369 /*----------------------------------------------------------------*/
370 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
372 mtspr ivor0,r1 /* Critical input */
374 mtspr ivor1,r1 /* Machine check */
376 mtspr ivor2,r1 /* Data storage */
378 mtspr ivor3,r1 /* Instruction storage */
380 mtspr ivor4,r1 /* External interrupt */
382 mtspr ivor5,r1 /* Alignment */
384 mtspr ivor6,r1 /* Program check */
386 mtspr ivor7,r1 /* Floating point unavailable */
388 mtspr ivor8,r1 /* System call */
390 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
392 mtspr ivor10,r1 /* Decrementer */
394 mtspr ivor13,r1 /* Data TLB error */
396 mtspr ivor14,r1 /* Instr TLB error */
398 mtspr ivor15,r1 /* Debug */
400 /*----------------------------------------------------------------*/
401 /* Configure cache regions */
402 /*----------------------------------------------------------------*/
420 /*----------------------------------------------------------------*/
421 /* Cache victim limits */
422 /*----------------------------------------------------------------*/
423 /* floors 0, ceiling max to use the entire cache -- nothing locked
430 /*----------------------------------------------------------------+
431 |Initialize MMUCR[STID] = 0.
432 +-----------------------------------------------------------------*/
439 /*----------------------------------------------------------------*/
440 /* Clear all TLB entries -- TID = 0, TS = 0 */
441 /*----------------------------------------------------------------*/
443 li r1,0x003f /* 64 TLB entries */
445 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
451 /*----------------------------------------------------------------*/
452 /* TLB entry setup -- step thru tlbtab */
453 /*----------------------------------------------------------------*/
454 #if defined(CONFIG_440SPE)
455 /*----------------------------------------------------------------*/
456 /* We have different TLB tables for revA and rev B of 440SPe */
457 /*----------------------------------------------------------------*/
469 bl tlbtab /* Get tlbtab pointer */
472 li r1,0x003f /* 64 TLB entries max */
479 beq 2f /* 0 marks end */
482 tlbwe r0,r4,0 /* TLB Word 0 */
483 tlbwe r1,r4,1 /* TLB Word 1 */
484 tlbwe r2,r4,2 /* TLB Word 2 */
485 addi r4,r4,1 /* Next TLB */
488 /*----------------------------------------------------------------*/
489 /* Continue from 'normal' start */
490 /*----------------------------------------------------------------*/
496 mtspr srr1,r0 /* Keep things disabled for now */
500 #endif /* CONFIG_440 */
503 * r3 - 1st arg to board_init(): IMMP pointer
504 * r4 - 2nd arg to board_init(): boot flag
506 #ifndef CONFIG_NAND_SPL
508 .long 0x27051956 /* U-Boot Magic Number */
509 .globl version_string
511 .ascii U_BOOT_VERSION
512 .ascii " (", __DATE__, " - ", __TIME__, ")"
513 .ascii CONFIG_IDENT_STRING, "\0"
515 . = EXC_OFF_SYS_RESET
516 .globl _start_of_vectors
519 /* Critical input. */
520 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
524 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
526 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
527 #endif /* CONFIG_440 */
529 /* Data Storage exception. */
530 STD_EXCEPTION(0x300, DataStorage, UnknownException)
532 /* Instruction Storage exception. */
533 STD_EXCEPTION(0x400, InstStorage, UnknownException)
535 /* External Interrupt exception. */
536 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
538 /* Alignment exception. */
541 EXCEPTION_PROLOG(SRR0, SRR1)
546 addi r3,r1,STACK_FRAME_OVERHEAD
548 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
549 lwz r6,GOT(transfer_to_handler)
553 .long AlignmentException - _start + _START_OFFSET
554 .long int_return - _start + _START_OFFSET
556 /* Program check exception */
559 EXCEPTION_PROLOG(SRR0, SRR1)
560 addi r3,r1,STACK_FRAME_OVERHEAD
562 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
563 lwz r6,GOT(transfer_to_handler)
567 .long ProgramCheckException - _start + _START_OFFSET
568 .long int_return - _start + _START_OFFSET
571 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
572 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
573 STD_EXCEPTION(0xa00, APU, UnknownException)
575 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
578 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
579 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
581 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
582 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
583 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
585 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
587 .globl _end_of_vectors
594 /*****************************************************************************/
595 #if defined(CONFIG_440)
597 /*----------------------------------------------------------------*/
598 /* Clear and set up some registers. */
599 /*----------------------------------------------------------------*/
602 mtspr dec,r0 /* prevent dec exceptions */
603 mtspr tbl,r0 /* prevent fit & wdt exceptions */
605 mtspr tsr,r1 /* clear all timer exception status */
606 mtspr tcr,r0 /* disable all */
607 mtspr esr,r0 /* clear exception syndrome register */
608 mtxer r0 /* clear integer exception register */
610 /*----------------------------------------------------------------*/
611 /* Debug setup -- some (not very good) ice's need an event*/
612 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
613 /* value you need in this case 0x8cff 0000 should do the trick */
614 /*----------------------------------------------------------------*/
615 #if defined(CONFIG_SYS_INIT_DBCR)
618 mtspr dbsr,r1 /* Clear all status bits */
619 lis r0,CONFIG_SYS_INIT_DBCR@h
620 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
625 /*----------------------------------------------------------------*/
626 /* Setup the internal SRAM */
627 /*----------------------------------------------------------------*/
630 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
631 /* Clear Dcache to use as RAM */
632 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
633 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
634 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
635 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
636 rlwinm. r5,r4,0,27,31
648 * Lock the init-ram/stack in d-cache, so that other regions
649 * may use d-cache as well
650 * Note, that this current implementation locks exactly 4k
651 * of d-cache, so please make sure that you don't define a
652 * bigger init-ram area. Take a look at the lwmon5 440EPx
653 * implementation as a reference.
657 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
673 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
675 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
676 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
677 /* not all PPC's have internal SRAM usable as L2-cache */
678 #if defined(CONFIG_440GX) || \
679 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
680 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
681 defined(CONFIG_460SX)
682 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
688 and r1,r1,r2 /* Disable parity check */
691 and r1,r1,r2 /* Disable pwr mgmt */
694 lis r1,0x8000 /* BAS = 8000_0000 */
695 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
696 ori r1,r1,0x0980 /* first 64k */
697 mtdcr isram0_sb0cr,r1
699 ori r1,r1,0x0980 /* second 64k */
700 mtdcr isram0_sb1cr,r1
702 ori r1,r1, 0x0980 /* third 64k */
703 mtdcr isram0_sb2cr,r1
705 ori r1,r1, 0x0980 /* fourth 64k */
706 mtdcr isram0_sb3cr,r1
707 #elif defined(CONFIG_440SPE)
708 lis r1,0x0000 /* BAS = 0000_0000 */
709 ori r1,r1,0x0984 /* first 64k */
710 mtdcr isram0_sb0cr,r1
712 ori r1,r1,0x0984 /* second 64k */
713 mtdcr isram0_sb1cr,r1
715 ori r1,r1, 0x0984 /* third 64k */
716 mtdcr isram0_sb2cr,r1
718 ori r1,r1, 0x0984 /* fourth 64k */
719 mtdcr isram0_sb3cr,r1
720 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
721 lis r1,0x4000 /* BAS = 8000_0000 */
722 ori r1,r1,0x4580 /* 16k */
723 mtdcr isram0_sb0cr,r1
724 #elif defined(CONFIG_460SX)
725 lis r1,0x0000 /* BAS = 0000_0000 */
726 ori r1,r1,0x0B84 /* first 128k */
727 mtdcr isram0_sb0cr,r1
729 ori r1,r1,0x0B84 /* second 128k */
730 mtdcr isram0_sb1cr,r1
732 ori r1,r1, 0x0B84 /* third 128k */
733 mtdcr isram0_sb2cr,r1
735 ori r1,r1, 0x0B84 /* fourth 128k */
736 mtdcr isram0_sb3cr,r1
737 #elif defined(CONFIG_440GP)
738 ori r1,r1,0x0380 /* 8k rw */
739 mtdcr isram0_sb0cr,r1
740 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
742 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
744 /*----------------------------------------------------------------*/
745 /* Setup the stack in internal SRAM */
746 /*----------------------------------------------------------------*/
747 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
748 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
751 stwu r0,-4(r1) /* Terminate call chain */
753 stwu r1,-8(r1) /* Save back chain and move SP */
754 lis r0,RESET_VECTOR@h /* Address of reset vector */
755 ori r0,r0, RESET_VECTOR@l
756 stwu r1,-8(r1) /* Save back chain and move SP */
757 stw r0,+12(r1) /* Save return addr (underflow vect) */
759 #ifdef CONFIG_NAND_SPL
760 bl nand_boot_common /* will not return */
764 bl cpu_init_f /* run low-level CPU init code (from Flash) */
768 #endif /* CONFIG_440 */
770 /*****************************************************************************/
772 /*----------------------------------------------------------------------- */
773 /* Set up some machine state registers. */
774 /*----------------------------------------------------------------------- */
775 addi r0,r0,0x0000 /* initialize r0 to zero */
776 mtspr esr,r0 /* clear Exception Syndrome Reg */
777 mttcr r0 /* timer control register */
778 mtexier r0 /* disable all interrupts */
779 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
780 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
781 mtdbsr r4 /* clear/reset the dbsr */
782 mtexisr r4 /* clear all pending interrupts */
784 mtexier r4 /* enable critical exceptions */
785 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
786 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
787 mtiocr r4 /* since bit not used) & DRC to latch */
788 /* data bus on rising edge of CAS */
789 /*----------------------------------------------------------------------- */
791 /*----------------------------------------------------------------------- */
793 /*----------------------------------------------------------------------- */
794 /* Invalidate i-cache and d-cache TAG arrays. */
795 /*----------------------------------------------------------------------- */
796 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
797 addi r4,0,1024 /* 1/4 of I-cache */
802 addic. r3,r3,-16 /* move back one cache line */
803 bne ..cloop /* loop back to do rest until r3 = 0 */
806 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
807 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
810 /* first copy IOP480 register base address into r3 */
811 addis r3,0,0x5000 /* IOP480 register base address hi */
812 /* ori r3,r3,0x0000 / IOP480 register base address lo */
815 /* use r4 as the working variable */
816 /* turn on CS3 (LOCCTL.7) */
817 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
818 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
819 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
822 #ifdef CONFIG_DASA_SIM
823 /* use r4 as the working variable */
824 /* turn on MA17 (LOCCTL.7) */
825 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
826 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
827 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
830 /* turn on MA16..13 (LCS0BRD.12 = 0) */
831 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
832 andi. r4,r4,0xefff /* make bit 12 = 0 */
833 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
835 /* make sure above stores all comlete before going on */
838 /* last thing, set local init status done bit (DEVINIT.31) */
839 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
840 oris r4,r4,0x8000 /* make bit 31 = 1 */
841 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
843 /* clear all pending interrupts and disable all interrupts */
844 li r4,-1 /* set p1 to 0xffffffff */
845 stw r4,0x1b0(r3) /* clear all pending interrupts */
846 stw r4,0x1b8(r3) /* clear all pending interrupts */
847 li r4,0 /* set r4 to 0 */
848 stw r4,0x1b4(r3) /* disable all interrupts */
849 stw r4,0x1bc(r3) /* disable all interrupts */
851 /* make sure above stores all comlete before going on */
854 /* Set-up icache cacheability. */
855 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
856 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
860 /* Set-up dcache cacheability. */
861 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
862 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
865 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
866 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
867 li r0, 0 /* Make room for stack frame header and */
868 stwu r0, -4(r1) /* clear final stack frame so that */
869 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
871 GET_GOT /* initialize GOT access */
873 bl board_init_f /* run first part of init code (from Flash) */
875 #endif /* CONFIG_IOP480 */
877 /*****************************************************************************/
878 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
879 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
880 defined(CONFIG_405EX) || defined(CONFIG_405)
881 /*----------------------------------------------------------------------- */
882 /* Clear and set up some registers. */
883 /*----------------------------------------------------------------------- */
885 #if !defined(CONFIG_405EX)
889 * On 405EX, completely clearing the SGR leads to PPC hangup
890 * upon PCIe configuration access. The PCIe memory regions
891 * need to be guarded!
898 mtesr r4 /* clear Exception Syndrome Reg */
899 mttcr r4 /* clear Timer Control Reg */
900 mtxer r4 /* clear Fixed-Point Exception Reg */
901 mtevpr r4 /* clear Exception Vector Prefix Reg */
902 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
903 /* dbsr is cleared by setting bits to 1) */
904 mtdbsr r4 /* clear/reset the dbsr */
906 /* Invalidate the i- and d-caches. */
910 /* Set-up icache cacheability. */
911 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
912 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
916 /* Set-up dcache cacheability. */
917 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
918 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
921 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
922 && !defined (CONFIG_XILINX_405)
923 /*----------------------------------------------------------------------- */
924 /* Tune the speed and size for flash CS0 */
925 /*----------------------------------------------------------------------- */
926 bl ext_bus_cntlr_init
929 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
931 * For boards that don't have OCM and can't use the data cache
932 * for their primordial stack, setup stack here directly after the
933 * SDRAM is initialized in ext_bus_cntlr_init.
935 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
936 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
938 li r0, 0 /* Make room for stack frame header and */
939 stwu r0, -4(r1) /* clear final stack frame so that */
940 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
942 * Set up a dummy frame to store reset vector as return address.
943 * this causes stack underflow to reset board.
945 stwu r1, -8(r1) /* Save back chain and move SP */
946 lis r0, RESET_VECTOR@h /* Address of reset vector */
947 ori r0, r0, RESET_VECTOR@l
948 stwu r1, -8(r1) /* Save back chain and move SP */
949 stw r0, +12(r1) /* Save return addr (underflow vect) */
950 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
952 #if defined(CONFIG_405EP)
953 /*----------------------------------------------------------------------- */
954 /* DMA Status, clear to come up clean */
955 /*----------------------------------------------------------------------- */
956 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
960 bl ppc405ep_init /* do ppc405ep specific init */
961 #endif /* CONFIG_405EP */
963 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
964 #if defined(CONFIG_405EZ)
965 /********************************************************************
966 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
967 *******************************************************************/
969 * We can map the OCM on the PLB3, so map it at
970 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
972 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
973 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
974 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
975 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
976 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
977 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
980 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
981 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
982 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
983 mtdcr ocmdscr1, r3 /* Set Data Side */
984 mtdcr ocmiscr1, r3 /* Set Instruction Side */
985 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
986 mtdcr ocmdscr2, r3 /* Set Data Side */
987 mtdcr ocmiscr2, r3 /* Set Instruction Side */
988 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
992 #else /* CONFIG_405EZ */
993 /********************************************************************
994 * Setup OCM - On Chip Memory
995 *******************************************************************/
999 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
1000 mfdcr r4, ocmdscntl /* get data-side IRAM config */
1001 and r3, r3, r0 /* disable data-side IRAM */
1002 and r4, r4, r0 /* disable data-side IRAM */
1003 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
1004 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
1007 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1008 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1010 addis r4, 0, 0xC000 /* OCM data area enabled */
1013 #endif /* CONFIG_405EZ */
1016 /*----------------------------------------------------------------------- */
1017 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1018 /*----------------------------------------------------------------------- */
1019 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1022 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1023 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1028 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1029 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1033 * Enable the data cache for the 128MB storage access control region
1034 * at CONFIG_SYS_INIT_RAM_ADDR.
1037 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1038 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1042 * Preallocate data cache lines to be used to avoid a subsequent
1043 * cache miss and an ensuing machine check exception when exceptions
1048 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1049 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1051 lis r4, CONFIG_SYS_INIT_RAM_END@h
1052 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1055 * Convert the size, in bytes, to the number of cache lines/blocks
1058 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1059 srwi r5, r4, L1_CACHE_SHIFT
1065 /* Preallocate the computed number of cache blocks. */
1066 ..alloc_dcache_block:
1068 addi r3, r3, L1_CACHE_BYTES
1069 bdnz ..alloc_dcache_block
1073 * Load the initial stack pointer and data area and convert the size,
1074 * in bytes, to the number of words to initialize to a known value.
1076 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1077 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1079 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1080 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1083 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1084 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1086 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1087 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1094 * Make room for stack frame header and clear final stack frame so
1095 * that stack backtraces terminate cleanly.
1101 * Set up a dummy frame to store reset vector as return address.
1102 * this causes stack underflow to reset board.
1104 stwu r1, -8(r1) /* Save back chain and move SP */
1105 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1106 ori r0, r0, RESET_VECTOR@l
1107 stwu r1, -8(r1) /* Save back chain and move SP */
1108 stw r0, +12(r1) /* Save return addr (underflow vect) */
1110 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1111 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1116 /* Set up Stack at top of OCM */
1117 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1118 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1120 /* Set up a zeroized stack frame so that backtrace works right */
1126 * Set up a dummy frame to store reset vector as return address.
1127 * this causes stack underflow to reset board.
1129 stwu r1, -8(r1) /* Save back chain and move SP */
1130 lis r0, RESET_VECTOR@h /* Address of reset vector */
1131 ori r0, r0, RESET_VECTOR@l
1132 stwu r1, -8(r1) /* Save back chain and move SP */
1133 stw r0, +12(r1) /* Save return addr (underflow vect) */
1134 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1136 #ifdef CONFIG_NAND_SPL
1137 bl nand_boot_common /* will not return */
1139 GET_GOT /* initialize GOT access */
1141 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1143 /* NEVER RETURNS! */
1144 bl board_init_f /* run first part of init code (from Flash) */
1145 #endif /* CONFIG_NAND_SPL */
1147 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1148 /*----------------------------------------------------------------------- */
1151 #ifndef CONFIG_NAND_SPL
1153 * This code finishes saving the registers to the exception frame
1154 * and jumps to the appropriate handler for the exception.
1155 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1157 .globl transfer_to_handler
1158 transfer_to_handler:
1168 andi. r24,r23,0x3f00 /* get vector offset */
1172 mtspr SPRG2,r22 /* r1 is now kernel sp */
1173 lwz r24,0(r23) /* virtual address of handler */
1174 lwz r23,4(r23) /* where to go when done */
1179 rfi /* jump to handler, enable MMU */
1182 mfmsr r28 /* Disable interrupts */
1186 SYNC /* Some chip revs need this... */
1201 lwz r2,_NIP(r1) /* Restore environment */
1212 mfmsr r28 /* Disable interrupts */
1216 SYNC /* Some chip revs need this... */
1231 lwz r2,_NIP(r1) /* Restore environment */
1243 mfmsr r28 /* Disable interrupts */
1247 SYNC /* Some chip revs need this... */
1262 lwz r2,_NIP(r1) /* Restore environment */
1271 #endif /* CONFIG_440 */
1279 /*------------------------------------------------------------------------------- */
1280 /* Function: out16 */
1281 /* Description: Output 16 bits */
1282 /*------------------------------------------------------------------------------- */
1288 /*------------------------------------------------------------------------------- */
1289 /* Function: out16r */
1290 /* Description: Byte reverse and output 16 bits */
1291 /*------------------------------------------------------------------------------- */
1297 /*------------------------------------------------------------------------------- */
1298 /* Function: out32r */
1299 /* Description: Byte reverse and output 32 bits */
1300 /*------------------------------------------------------------------------------- */
1306 /*------------------------------------------------------------------------------- */
1307 /* Function: in16 */
1308 /* Description: Input 16 bits */
1309 /*------------------------------------------------------------------------------- */
1315 /*------------------------------------------------------------------------------- */
1316 /* Function: in16r */
1317 /* Description: Input 16 bits and byte reverse */
1318 /*------------------------------------------------------------------------------- */
1324 /*------------------------------------------------------------------------------- */
1325 /* Function: in32r */
1326 /* Description: Input 32 bits and byte reverse */
1327 /*------------------------------------------------------------------------------- */
1334 * void relocate_code (addr_sp, gd, addr_moni)
1336 * This "function" does not return, instead it continues in RAM
1337 * after relocating the monitor code.
1339 * r3 = Relocated stack pointer
1340 * r4 = Relocated global data pointer
1341 * r5 = Relocated text pointer
1343 .globl relocate_code
1345 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1347 * We need to flush the initial global data (gd_t) before the dcache
1348 * will be invalidated.
1351 /* Save registers */
1356 /* Flush initial global data range */
1358 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1359 bl flush_dcache_range
1361 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1363 * Undo the earlier data cache set-up for the primordial stack and
1364 * data area. First, invalidate the data cache and then disable data
1365 * cacheability for that area. Finally, restore the EBC values, if
1369 /* Invalidate the primordial stack and data area in cache */
1370 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1371 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1373 lis r4, CONFIG_SYS_INIT_RAM_END@h
1374 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1377 bl invalidate_dcache_range
1379 /* Disable cacheability for the region */
1381 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1382 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1386 /* Restore the EBC parameters */
1390 ori r3, r3, PBxAP_VAL@l
1396 ori r3, r3, PBxCR_VAL@l
1398 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1400 /* Restore registers */
1404 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1406 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1408 * Unlock the previously locked d-cache
1412 /* set TFLOOR/NFLOOR to 0 again */
1428 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1430 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1431 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1432 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1433 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1434 defined(CONFIG_460SX)
1436 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1437 * to speed up the boot process. Now this cache needs to be disabled.
1439 iccci 0,0 /* Invalidate inst cache */
1440 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1443 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
1444 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1446 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1447 #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
1448 tlbre r0,r1,0x0002 /* Read contents */
1449 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1450 tlbwe r0,r1,0x0002 /* Save it out */
1453 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1454 mr r1, r3 /* Set new stack pointer */
1455 mr r9, r4 /* Save copy of Init Data pointer */
1456 mr r10, r5 /* Save copy of Destination Address */
1458 mr r3, r5 /* Destination Address */
1459 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1460 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1461 lwz r5, GOT(__init_end)
1463 li r6, L1_CACHE_BYTES /* Cache Line Size */
1468 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1474 /* First our own GOT */
1476 /* then the one used by the C code */
1486 beq cr1,4f /* In place copy is not necessary */
1487 beq 7f /* Protect against 0 count */
1506 * Now flush the cache: note that we must start from a cache aligned
1507 * address. Otherwise we might miss one cache line.
1511 beq 7f /* Always flush prefetch queue in any case */
1519 sync /* Wait for all dcbst to complete on bus */
1525 7: sync /* Wait for all icbi to complete on bus */
1529 * We are done. Do not return, instead branch to second part of board
1530 * initialization, now running from RAM.
1533 addi r0, r10, in_ram - _start + _START_OFFSET
1535 blr /* NEVER RETURNS! */
1540 * Relocation Function, r14 point to got2+0x8000
1542 * Adjust got2 pointers, no need to check for 0, this code
1543 * already puts a few entries in the table.
1545 li r0,__got2_entries@sectoff@l
1546 la r3,GOT(_GOT2_TABLE_)
1547 lwz r11,GOT(_GOT2_TABLE_)
1557 * Now adjust the fixups and the pointers to the fixups
1558 * in case we need to move ourselves again.
1560 2: li r0,__fixup_entries@sectoff@l
1561 lwz r3,GOT(_FIXUP_TABLE_)
1575 * Now clear BSS segment
1577 lwz r3,GOT(__bss_start)
1600 mr r3, r9 /* Init Data pointer */
1601 mr r4, r10 /* Destination Address */
1605 * Copy exception vector code to low memory
1608 * r7: source address, r8: end address, r9: target address
1612 lwz r7, GOT(_start_of_vectors)
1613 lwz r8, GOT(_end_of_vectors)
1615 li r9, 0x100 /* reset vector always at 0x100 */
1618 bgelr /* return if r7>=r8 - just in case */
1620 mflr r4 /* save link register */
1630 * relocate `hdlr' and `int_return' entries
1632 li r7, .L_MachineCheck - _start + _START_OFFSET
1633 li r8, Alignment - _start + _START_OFFSET
1636 addi r7, r7, 0x100 /* next exception vector */
1640 li r7, .L_Alignment - _start + _START_OFFSET
1643 li r7, .L_ProgramCheck - _start + _START_OFFSET
1647 li r7, .L_FPUnavailable - _start + _START_OFFSET
1650 li r7, .L_Decrementer - _start + _START_OFFSET
1653 li r7, .L_APU - _start + _START_OFFSET
1656 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1659 li r7, .L_DataTLBError - _start + _START_OFFSET
1661 #else /* CONFIG_440 */
1662 li r7, .L_PIT - _start + _START_OFFSET
1665 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1668 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1670 #endif /* CONFIG_440 */
1672 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1675 #if !defined(CONFIG_440)
1676 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1677 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1678 mtmsr r7 /* change MSR */
1681 b __440_msr_continue
1684 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1685 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1693 mtlr r4 /* restore link register */
1697 * Function: relocate entries for one exception vector
1700 lwz r0, 0(r7) /* hdlr ... */
1701 add r0, r0, r3 /* ... += dest_addr */
1704 lwz r0, 4(r7) /* int_return ... */
1705 add r0, r0, r3 /* ... += dest_addr */
1710 #if defined(CONFIG_440)
1711 /*----------------------------------------------------------------------------+
1713 +----------------------------------------------------------------------------*/
1714 function_prolog(dcbz_area)
1715 rlwinm. r5,r4,0,27,31
1716 rlwinm r5,r4,27,5,31
1725 function_epilog(dcbz_area)
1726 #endif /* CONFIG_440 */
1727 #endif /* CONFIG_NAND_SPL */
1729 /*------------------------------------------------------------------------------- */
1731 /* Description: Input 8 bits */
1732 /*------------------------------------------------------------------------------- */
1738 /*------------------------------------------------------------------------------- */
1739 /* Function: out8 */
1740 /* Description: Output 8 bits */
1741 /*------------------------------------------------------------------------------- */
1747 /*------------------------------------------------------------------------------- */
1748 /* Function: out32 */
1749 /* Description: Output 32 bits */
1750 /*------------------------------------------------------------------------------- */
1756 /*------------------------------------------------------------------------------- */
1757 /* Function: in32 */
1758 /* Description: Input 32 bits */
1759 /*------------------------------------------------------------------------------- */
1765 /**************************************************************************/
1766 /* PPC405EP specific stuff */
1767 /**************************************************************************/
1771 #ifdef CONFIG_BUBINGA
1773 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1774 * function) to support FPGA and NVRAM accesses below.
1777 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1778 ori r3,r3,GPIO0_OSRH@l
1779 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1780 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1783 ori r3,r3,GPIO0_OSRL@l
1784 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1785 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1788 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1789 ori r3,r3,GPIO0_ISR1H@l
1790 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1791 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1793 lis r3,GPIO0_ISR1L@h
1794 ori r3,r3,GPIO0_ISR1L@l
1795 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1796 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1799 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1800 ori r3,r3,GPIO0_TSRH@l
1801 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1802 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1805 ori r3,r3,GPIO0_TSRL@l
1806 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1807 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1810 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1811 ori r3,r3,GPIO0_TCR@l
1812 lis r4,CONFIG_SYS_GPIO0_TCR@h
1813 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1816 li r3,pb1ap /* program EBC bank 1 for RTC access */
1818 lis r3,CONFIG_SYS_EBC_PB1AP@h
1819 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1823 lis r3,CONFIG_SYS_EBC_PB1CR@h
1824 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1827 li r3,pb1ap /* program EBC bank 1 for RTC access */
1829 lis r3,CONFIG_SYS_EBC_PB1AP@h
1830 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1834 lis r3,CONFIG_SYS_EBC_PB1CR@h
1835 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1838 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1840 lis r3,CONFIG_SYS_EBC_PB4AP@h
1841 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1845 lis r3,CONFIG_SYS_EBC_PB4CR@h
1846 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1851 !-----------------------------------------------------------------------
1852 ! Check to see if chip is in bypass mode.
1853 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1854 ! CPU reset Otherwise, skip this step and keep going.
1855 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1856 ! will not be fast enough for the SDRAM (min 66MHz)
1857 !-----------------------------------------------------------------------
1859 mfdcr r5, CPC0_PLLMR1
1860 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1863 beq pll_done /* if SSCS =b'1' then PLL has */
1864 /* already been set */
1865 /* and CPU has been reset */
1866 /* so skip to next section */
1868 #ifdef CONFIG_BUBINGA
1870 !-----------------------------------------------------------------------
1871 ! Read NVRAM to get value to write in PLLMR.
1872 ! If value has not been correctly saved, write default value
1873 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1874 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1876 ! WARNING: This code assumes the first three words in the nvram_t
1877 ! structure in openbios.h. Changing the beginning of
1878 ! the structure will break this code.
1880 !-----------------------------------------------------------------------
1882 addis r3,0,NVRAM_BASE@h
1883 addi r3,r3,NVRAM_BASE@l
1886 addis r5,0,NVRVFY1@h
1887 addi r5,r5,NVRVFY1@l
1888 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1892 addis r5,0,NVRVFY2@h
1893 addi r5,r5,NVRVFY2@l
1894 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1896 addi r3,r3,8 /* Skip over conf_size */
1897 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1898 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1899 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1900 cmpi cr0,0,r5,1 /* See if PLL is locked */
1903 #endif /* CONFIG_BUBINGA */
1907 andi. r5, r4, CPC0_BOOT_SEP@l
1908 bne strap_1 /* serial eeprom present */
1909 addis r5,0,CPLD_REG0_ADDR@h
1910 ori r5,r5,CPLD_REG0_ADDR@l
1913 #endif /* CONFIG_TAIHU */
1915 #if defined(CONFIG_ZEUS)
1917 andi. r5, r4, CPC0_BOOT_SEP@l
1918 bne strap_1 /* serial eeprom present */
1925 mfdcr r3, CPC0_PLLMR0
1926 mfdcr r4, CPC0_PLLMR1
1930 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1931 ori r3,r3,PLLMR0_DEFAULT@l /* */
1932 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1933 ori r4,r4,PLLMR1_DEFAULT@l /* */
1938 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1939 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1940 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1941 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1944 mfdcr r3, CPC0_PLLMR0
1945 mfdcr r4, CPC0_PLLMR1
1946 #endif /* CONFIG_TAIHU */
1949 b pll_write /* Write the CPC0_PLLMR with new value */
1953 !-----------------------------------------------------------------------
1954 ! Clear Soft Reset Register
1955 ! This is needed to enable PCI if not booting from serial EPROM
1956 !-----------------------------------------------------------------------
1966 blr /* return to main code */
1969 !-----------------------------------------------------------------------------
1970 ! Function: pll_write
1971 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1973 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1975 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1976 ! 4. PLL Reset is cleared
1977 ! 5. Wait 100us for PLL to lock
1978 ! 6. A core reset is performed
1979 ! Input: r3 = Value to write to CPC0_PLLMR0
1980 ! Input: r4 = Value to write to CPC0_PLLMR1
1982 !-----------------------------------------------------------------------------
1987 ori r5,r5,0x0101 /* Stop the UART clocks */
1988 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1990 mfdcr r5, CPC0_PLLMR1
1991 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1992 mtdcr CPC0_PLLMR1,r5
1993 oris r5,r5,0x4000 /* Set PLL Reset */
1994 mtdcr CPC0_PLLMR1,r5
1996 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1997 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1998 oris r5,r5,0x4000 /* Set PLL Reset */
1999 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2000 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2001 mtdcr CPC0_PLLMR1,r5
2004 ! Wait min of 100us for PLL to lock.
2005 ! See CMOS 27E databook for more info.
2006 ! At 200MHz, that means waiting 20,000 instructions
2008 addi r3,0,20000 /* 2000 = 0x4e20 */
2013 oris r5,r5,0x8000 /* Enable PLL */
2014 mtdcr CPC0_PLLMR1,r5 /* Engage */
2017 * Reset CPU to guarantee timings are OK
2018 * Not sure if this is needed...
2021 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2022 /* execution will continue from the poweron */
2023 /* vector of 0xfffffffc */
2024 #endif /* CONFIG_405EP */
2026 #if defined(CONFIG_440)
2027 /*----------------------------------------------------------------------------+
2029 +----------------------------------------------------------------------------*/
2030 function_prolog(mttlb3)
2033 function_epilog(mttlb3)
2035 /*----------------------------------------------------------------------------+
2037 +----------------------------------------------------------------------------*/
2038 function_prolog(mftlb3)
2041 function_epilog(mftlb3)
2043 /*----------------------------------------------------------------------------+
2045 +----------------------------------------------------------------------------*/
2046 function_prolog(mttlb2)
2049 function_epilog(mttlb2)
2051 /*----------------------------------------------------------------------------+
2053 +----------------------------------------------------------------------------*/
2054 function_prolog(mftlb2)
2057 function_epilog(mftlb2)
2059 /*----------------------------------------------------------------------------+
2061 +----------------------------------------------------------------------------*/
2062 function_prolog(mttlb1)
2065 function_epilog(mttlb1)
2067 /*----------------------------------------------------------------------------+
2069 +----------------------------------------------------------------------------*/
2070 function_prolog(mftlb1)
2073 function_epilog(mftlb1)
2074 #endif /* CONFIG_440 */
2076 #if defined(CONFIG_NAND_SPL)
2078 * void nand_boot_relocate(dst, src, bytes)
2080 * r3 = Destination address to copy code to (in SDRAM)
2081 * r4 = Source address to copy code from
2082 * r5 = size to copy in bytes
2090 * Copy SPL from icache into SDRAM
2102 * Calculate "corrected" link register, so that we "continue"
2103 * in execution in destination range
2105 sub r3,r7,r6 /* r3 = src - dst */
2106 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2112 * First initialize SDRAM. It has to be available *before* calling
2115 lis r3,CONFIG_SYS_SDRAM_BASE@h
2116 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2120 * Now copy the 4k SPL code into SDRAM and continue execution
2123 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2124 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2125 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2126 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2127 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2128 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2129 bl nand_boot_relocate
2132 * We're running from SDRAM now!!!
2134 * It is necessary for 4xx systems to relocate from running at
2135 * the original location (0xfffffxxx) to somewhere else (SDRAM
2136 * preferably). This is because CS0 needs to be reconfigured for
2137 * NAND access. And we can't reconfigure this CS when currently
2138 * "running" from it.
2142 * Finally call nand_boot() to load main NAND U-Boot image from
2143 * NAND and jump to it.
2145 bl nand_boot /* will not return */
2146 #endif /* CONFIG_NAND_SPL */