2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*------------------------------------------------------------------------------+ */
27 /* This source code has been made available to you by IBM on an AS-IS */
28 /* basis. Anyone receiving this source is licensed under IBM */
29 /* copyrights to use it in any way he or she deems fit, including */
30 /* copying it, modifying it, compiling it, and redistributing it either */
31 /* with or without modifications. No license under IBM patents or */
32 /* patent applications is to be implied by the copyright license. */
34 /* Any user of this software should understand that IBM cannot provide */
35 /* technical support for this software and will not be responsible for */
36 /* any consequences resulting from the use of this software. */
38 /* Any person who transfers this source code or any derivative work */
39 /* must include the IBM copyright notice, this paragraph, and the */
40 /* preceding two paragraphs in the transferred software. */
42 /* COPYRIGHT I B M CORPORATION 1995 */
43 /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
44 /*------------------------------------------------------------------------------- */
46 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
49 * The processor starts at 0xfffffffc and the code is executed
51 * in memory, but as long we don't jump around before relocating.
52 * board_init lies at a quite high address and when the cpu has
53 * jumped there, everything is ok.
54 * This works because the cpu gives the FLASH (CS0) the whole
55 * address space at startup, and board_init lies as a echo of
56 * the flash somewhere up there in the memorymap.
58 * board_init will change CS0 to be positioned at the correct
59 * address and (s)dram will be positioned at address 0
66 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
68 #include <ppc_asm.tmpl>
71 #include <asm/cache.h>
74 #ifndef CONFIG_IDENT_STRING
75 #define CONFIG_IDENT_STRING ""
78 #ifdef CFG_INIT_DCACHE_CS
79 # if (CFG_INIT_DCACHE_CS == 0)
83 # if (CFG_INIT_DCACHE_CS == 1)
87 # if (CFG_INIT_DCACHE_CS == 2)
91 # if (CFG_INIT_DCACHE_CS == 3)
95 # if (CFG_INIT_DCACHE_CS == 4)
99 # if (CFG_INIT_DCACHE_CS == 5)
103 # if (CFG_INIT_DCACHE_CS == 6)
107 # if (CFG_INIT_DCACHE_CS == 7)
111 #endif /* CFG_INIT_DCACHE_CS */
113 #define function_prolog(func_name) .text; \
117 #define function_epilog(func_name) .type func_name,@function; \
118 .size func_name,.-func_name
120 /* We don't want the MMU yet.
123 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
126 .extern ext_bus_cntlr_init
128 #ifdef CONFIG_NAND_U_BOOT
129 .extern reconfig_tlb0
133 * Set up GOT: Global Offset Table
135 * Use r14 to access the GOT
137 #if !defined(CONFIG_NAND_SPL)
139 GOT_ENTRY(_GOT2_TABLE_)
140 GOT_ENTRY(_FIXUP_TABLE_)
143 GOT_ENTRY(_start_of_vectors)
144 GOT_ENTRY(_end_of_vectors)
145 GOT_ENTRY(transfer_to_handler)
147 GOT_ENTRY(__init_end)
149 GOT_ENTRY(__bss_start)
151 #endif /* CONFIG_NAND_SPL */
153 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
155 * NAND U-Boot image is started from offset 0
158 #if defined(CONFIG_440)
162 bl cpu_init_f /* run low-level CPU init code (from Flash) */
167 * 440 Startup -- on reset only the top 4k of the effective
168 * address space is mapped in by an entry in the instruction
169 * and data shadow TLB. The .bootpg section is located in the
170 * top 4k & does only what's necessary to map in the the rest
171 * of the boot rom. Once the boot rom is mapped in we can
172 * proceed with normal startup.
174 * NOTE: CS0 only covers the top 2MB of the effective address
178 #if defined(CONFIG_440)
179 #if !defined(CONFIG_NAND_SPL)
180 .section .bootpg,"ax"
184 /**************************************************************************/
186 /*--------------------------------------------------------------------+
187 | 440EPX BUP Change - Hardware team request
188 +--------------------------------------------------------------------*/
189 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
194 /*----------------------------------------------------------------+
195 | Core bug fix. Clear the esr
196 +-----------------------------------------------------------------*/
199 /*----------------------------------------------------------------*/
200 /* Clear and set up some registers. */
201 /*----------------------------------------------------------------*/
202 iccci r0,r0 /* NOTE: operands not used for 440 */
203 dccci r0,r0 /* NOTE: operands not used for 440 */
210 /* NOTE: 440GX adds machine check status regs */
211 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
218 /*----------------------------------------------------------------*/
220 /*----------------------------------------------------------------*/
221 /* Disable store gathering & broadcast, guarantee inst/data
222 * cache block touch, force load/store alignment
223 * (see errata 1.12: 440_33)
225 lis r1,0x0030 /* store gathering & broadcast disable */
226 ori r1,r1,0x6000 /* cache touch */
229 /*----------------------------------------------------------------*/
230 /* Initialize debug */
231 /*----------------------------------------------------------------*/
233 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
234 bne skip_debug_init /* if set, don't clear debug register */
247 mtspr dbsr,r1 /* Clear all valid bits */
250 #if defined (CONFIG_440SPE)
251 /*----------------------------------------------------------------+
252 | Initialize Core Configuration Reg1.
253 | a. ICDPEI: Record even parity. Normal operation.
254 | b. ICTPEI: Record even parity. Normal operation.
255 | c. DCTPEI: Record even parity. Normal operation.
256 | d. DCDPEI: Record even parity. Normal operation.
257 | e. DCUPEI: Record even parity. Normal operation.
258 | f. DCMPEI: Record even parity. Normal operation.
259 | g. FCOM: Normal operation
260 | h. MMUPEI: Record even parity. Normal operation.
261 | i. FFF: Flush only as much data as necessary.
262 | j. TCS: Timebase increments from CPU clock.
263 +-----------------------------------------------------------------*/
267 /*----------------------------------------------------------------+
268 | Reset the timebase.
269 | The previous write to CCR1 sets the timebase source.
270 +-----------------------------------------------------------------*/
275 /*----------------------------------------------------------------*/
276 /* Setup interrupt vectors */
277 /*----------------------------------------------------------------*/
278 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
280 mtspr ivor0,r1 /* Critical input */
282 mtspr ivor1,r1 /* Machine check */
284 mtspr ivor2,r1 /* Data storage */
286 mtspr ivor3,r1 /* Instruction storage */
288 mtspr ivor4,r1 /* External interrupt */
290 mtspr ivor5,r1 /* Alignment */
292 mtspr ivor6,r1 /* Program check */
294 mtspr ivor7,r1 /* Floating point unavailable */
296 mtspr ivor8,r1 /* System call */
298 mtspr ivor10,r1 /* Decrementer (PIT for 440) */
300 mtspr ivor13,r1 /* Data TLB error */
302 mtspr ivor14,r1 /* Instr TLB error */
304 mtspr ivor15,r1 /* Debug */
306 /*----------------------------------------------------------------*/
307 /* Configure cache regions */
308 /*----------------------------------------------------------------*/
326 /*----------------------------------------------------------------*/
327 /* Cache victim limits */
328 /*----------------------------------------------------------------*/
329 /* floors 0, ceiling max to use the entire cache -- nothing locked
336 /*----------------------------------------------------------------+
337 |Initialize MMUCR[STID] = 0.
338 +-----------------------------------------------------------------*/
345 /*----------------------------------------------------------------*/
346 /* Clear all TLB entries -- TID = 0, TS = 0 */
347 /*----------------------------------------------------------------*/
349 li r1,0x003f /* 64 TLB entries */
351 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
357 /*----------------------------------------------------------------*/
358 /* TLB entry setup -- step thru tlbtab */
359 /*----------------------------------------------------------------*/
360 #if defined(CONFIG_440SPE)
361 /*----------------------------------------------------------------*/
362 /* We have different TLB tables for revA and rev B of 440SPe */
363 /*----------------------------------------------------------------*/
375 bl tlbtab /* Get tlbtab pointer */
378 li r1,0x003f /* 64 TLB entries max */
385 beq 2f /* 0 marks end */
388 tlbwe r0,r4,0 /* TLB Word 0 */
389 tlbwe r1,r4,1 /* TLB Word 1 */
390 tlbwe r2,r4,2 /* TLB Word 2 */
391 addi r4,r4,1 /* Next TLB */
394 /*----------------------------------------------------------------*/
395 /* Continue from 'normal' start */
396 /*----------------------------------------------------------------*/
399 #if defined(CONFIG_NAND_SPL)
400 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
402 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
407 and r1,r1,r2 /* Disable parity check */
410 and r1,r1,r2 /* Disable pwr mgmt */
413 #if defined(CONFIG_440EP)
415 * On 440EP with no internal SRAM, we setup SDRAM very early
416 * and copy the NAND_SPL to SDRAM and jump to it
418 /* Clear Dcache to use as RAM */
419 addis r3,r0,CFG_INIT_RAM_ADDR@h
420 ori r3,r3,CFG_INIT_RAM_ADDR@l
421 addis r4,r0,CFG_INIT_RAM_END@h
422 ori r4,r4,CFG_INIT_RAM_END@l
423 rlwinm. r5,r4,0,27,31
433 /*----------------------------------------------------------------*/
434 /* Setup the stack in internal SRAM */
435 /*----------------------------------------------------------------*/
436 lis r1,CFG_INIT_RAM_ADDR@h
437 ori r1,r1,CFG_INIT_SP_OFFSET@l
440 stwu r0,-4(r1) /* Terminate call chain */
442 stwu r1,-8(r1) /* Save back chain and move SP */
443 lis r0,RESET_VECTOR@h /* Address of reset vector */
444 ori r0,r0, RESET_VECTOR@l
445 stwu r1,-8(r1) /* Save back chain and move SP */
446 stw r0,+12(r1) /* Save return addr (underflow vect) */
450 #endif /* CONFIG_440EP */
453 * Copy SPL from cache into internal SRAM
455 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
457 lis r2,CFG_NAND_BOOT_SPL_SRC@h
458 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
459 lis r3,CFG_NAND_BOOT_SPL_DST@h
460 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
467 * Jump to code in RAM
471 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
472 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
481 #endif /* CONFIG_NAND_SPL */
487 mtspr srr1,r0 /* Keep things disabled for now */
491 #endif /* CONFIG_440 */
494 * r3 - 1st arg to board_init(): IMMP pointer
495 * r4 - 2nd arg to board_init(): boot flag
497 #ifndef CONFIG_NAND_SPL
499 .long 0x27051956 /* U-Boot Magic Number */
500 .globl version_string
502 .ascii U_BOOT_VERSION
503 .ascii " (", __DATE__, " - ", __TIME__, ")"
504 .ascii CONFIG_IDENT_STRING, "\0"
507 * Maybe this should be moved somewhere else because the current
508 * location (0x100) is where the CriticalInput Execption should be.
510 . = EXC_OFF_SYS_RESET
515 /*****************************************************************************/
516 #if defined(CONFIG_440)
518 /*----------------------------------------------------------------*/
519 /* Clear and set up some registers. */
520 /*----------------------------------------------------------------*/
523 mtspr dec,r0 /* prevent dec exceptions */
524 mtspr tbl,r0 /* prevent fit & wdt exceptions */
526 mtspr tsr,r1 /* clear all timer exception status */
527 mtspr tcr,r0 /* disable all */
528 mtspr esr,r0 /* clear exception syndrome register */
529 mtxer r0 /* clear integer exception register */
531 /*----------------------------------------------------------------*/
532 /* Debug setup -- some (not very good) ice's need an event*/
533 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
534 /* value you need in this case 0x8cff 0000 should do the trick */
535 /*----------------------------------------------------------------*/
536 #if defined(CFG_INIT_DBCR)
539 mtspr dbsr,r1 /* Clear all status bits */
540 lis r0,CFG_INIT_DBCR@h
541 ori r0,r0,CFG_INIT_DBCR@l
546 /*----------------------------------------------------------------*/
547 /* Setup the internal SRAM */
548 /*----------------------------------------------------------------*/
551 #ifdef CFG_INIT_RAM_DCACHE
552 /* Clear Dcache to use as RAM */
553 addis r3,r0,CFG_INIT_RAM_ADDR@h
554 ori r3,r3,CFG_INIT_RAM_ADDR@l
555 addis r4,r0,CFG_INIT_RAM_END@h
556 ori r4,r4,CFG_INIT_RAM_END@l
557 rlwinm. r5,r4,0,27,31
567 #endif /* CFG_INIT_RAM_DCACHE */
569 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
570 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
571 /* not all PPC's have internal SRAM usable as L2-cache */
572 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
573 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
579 and r1,r1,r2 /* Disable parity check */
582 and r1,r1,r2 /* Disable pwr mgmt */
585 lis r1,0x8000 /* BAS = 8000_0000 */
586 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
587 ori r1,r1,0x0980 /* first 64k */
588 mtdcr isram0_sb0cr,r1
590 ori r1,r1,0x0980 /* second 64k */
591 mtdcr isram0_sb1cr,r1
593 ori r1,r1, 0x0980 /* third 64k */
594 mtdcr isram0_sb2cr,r1
596 ori r1,r1, 0x0980 /* fourth 64k */
597 mtdcr isram0_sb3cr,r1
598 #elif defined(CONFIG_440SPE)
599 lis r1,0x0000 /* BAS = 0000_0000 */
600 ori r1,r1,0x0984 /* first 64k */
601 mtdcr isram0_sb0cr,r1
603 ori r1,r1,0x0984 /* second 64k */
604 mtdcr isram0_sb1cr,r1
606 ori r1,r1, 0x0984 /* third 64k */
607 mtdcr isram0_sb2cr,r1
609 ori r1,r1, 0x0984 /* fourth 64k */
610 mtdcr isram0_sb3cr,r1
611 #elif defined(CONFIG_440GP)
612 ori r1,r1,0x0380 /* 8k rw */
613 mtdcr isram0_sb0cr,r1
614 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
616 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
618 /*----------------------------------------------------------------*/
619 /* Setup the stack in internal SRAM */
620 /*----------------------------------------------------------------*/
621 lis r1,CFG_INIT_RAM_ADDR@h
622 ori r1,r1,CFG_INIT_SP_OFFSET@l
625 stwu r0,-4(r1) /* Terminate call chain */
627 stwu r1,-8(r1) /* Save back chain and move SP */
628 lis r0,RESET_VECTOR@h /* Address of reset vector */
629 ori r0,r0, RESET_VECTOR@l
630 stwu r1,-8(r1) /* Save back chain and move SP */
631 stw r0,+12(r1) /* Save return addr (underflow vect) */
633 #ifdef CONFIG_NAND_SPL
634 bl nand_boot /* will not return */
638 bl cpu_init_f /* run low-level CPU init code (from Flash) */
642 #endif /* CONFIG_440 */
644 /*****************************************************************************/
646 /*----------------------------------------------------------------------- */
647 /* Set up some machine state registers. */
648 /*----------------------------------------------------------------------- */
649 addi r0,r0,0x0000 /* initialize r0 to zero */
650 mtspr esr,r0 /* clear Exception Syndrome Reg */
651 mttcr r0 /* timer control register */
652 mtexier r0 /* disable all interrupts */
653 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
654 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
655 mtdbsr r4 /* clear/reset the dbsr */
656 mtexisr r4 /* clear all pending interrupts */
658 mtexier r4 /* enable critical exceptions */
659 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
660 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
661 mtiocr r4 /* since bit not used) & DRC to latch */
662 /* data bus on rising edge of CAS */
663 /*----------------------------------------------------------------------- */
665 /*----------------------------------------------------------------------- */
667 /*----------------------------------------------------------------------- */
668 /* Invalidate i-cache and d-cache TAG arrays. */
669 /*----------------------------------------------------------------------- */
670 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
671 addi r4,0,1024 /* 1/4 of I-cache */
676 addic. r3,r3,-16 /* move back one cache line */
677 bne ..cloop /* loop back to do rest until r3 = 0 */
680 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
681 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
684 /* first copy IOP480 register base address into r3 */
685 addis r3,0,0x5000 /* IOP480 register base address hi */
686 /* ori r3,r3,0x0000 / IOP480 register base address lo */
689 /* use r4 as the working variable */
690 /* turn on CS3 (LOCCTL.7) */
691 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
692 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
693 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
696 #ifdef CONFIG_DASA_SIM
697 /* use r4 as the working variable */
698 /* turn on MA17 (LOCCTL.7) */
699 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
700 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
701 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
704 /* turn on MA16..13 (LCS0BRD.12 = 0) */
705 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
706 andi. r4,r4,0xefff /* make bit 12 = 0 */
707 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
709 /* make sure above stores all comlete before going on */
712 /* last thing, set local init status done bit (DEVINIT.31) */
713 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
714 oris r4,r4,0x8000 /* make bit 31 = 1 */
715 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
717 /* clear all pending interrupts and disable all interrupts */
718 li r4,-1 /* set p1 to 0xffffffff */
719 stw r4,0x1b0(r3) /* clear all pending interrupts */
720 stw r4,0x1b8(r3) /* clear all pending interrupts */
721 li r4,0 /* set r4 to 0 */
722 stw r4,0x1b4(r3) /* disable all interrupts */
723 stw r4,0x1bc(r3) /* disable all interrupts */
725 /* make sure above stores all comlete before going on */
728 /*----------------------------------------------------------------------- */
729 /* Enable two 128MB cachable regions. */
730 /*----------------------------------------------------------------------- */
733 mticcr r1 /* instruction cache */
737 mtdccr r1 /* data cache */
739 addis r1,r0,CFG_INIT_RAM_ADDR@h
740 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
741 li r0, 0 /* Make room for stack frame header and */
742 stwu r0, -4(r1) /* clear final stack frame so that */
743 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
745 GET_GOT /* initialize GOT access */
747 bl board_init_f /* run first part of init code (from Flash) */
749 #endif /* CONFIG_IOP480 */
751 /*****************************************************************************/
752 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
753 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
755 /*----------------------------------------------------------------------- */
756 /* Clear and set up some registers. */
757 /*----------------------------------------------------------------------- */
761 mtesr r4 /* clear Exception Syndrome Reg */
762 mttcr r4 /* clear Timer Control Reg */
763 mtxer r4 /* clear Fixed-Point Exception Reg */
764 mtevpr r4 /* clear Exception Vector Prefix Reg */
765 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
766 /* dbsr is cleared by setting bits to 1) */
767 mtdbsr r4 /* clear/reset the dbsr */
769 /*----------------------------------------------------------------------- */
770 /* Invalidate I and D caches. Enable I cache for defined memory regions */
771 /* to speed things up. Leave the D cache disabled for now. It will be */
772 /* enabled/left disabled later based on user selected menu options. */
773 /* Be aware that the I cache may be disabled later based on the menu */
774 /* options as well. See miscLib/main.c. */
775 /*----------------------------------------------------------------------- */
779 /*----------------------------------------------------------------------- */
780 /* Enable two 128MB cachable regions. */
781 /*----------------------------------------------------------------------- */
784 mticcr r4 /* instruction cache */
789 mtdccr r4 /* data cache */
791 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
792 /*----------------------------------------------------------------------- */
793 /* Tune the speed and size for flash CS0 */
794 /*----------------------------------------------------------------------- */
795 bl ext_bus_cntlr_init
798 #if defined(CONFIG_405EP)
799 /*----------------------------------------------------------------------- */
800 /* DMA Status, clear to come up clean */
801 /*----------------------------------------------------------------------- */
802 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
806 bl ppc405ep_init /* do ppc405ep specific init */
807 #endif /* CONFIG_405EP */
809 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
810 #if defined(CONFIG_405EZ)
811 /********************************************************************
812 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
813 *******************************************************************/
815 * We can map the OCM on the PLB3, so map it at
816 * CFG_OCM_DATA_ADDR + 0x8000
818 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
819 ori r3,r3,CFG_OCM_DATA_ADDR@l
820 ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */
821 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
822 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
823 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
826 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
827 ori r3,r3,CFG_OCM_DATA_ADDR@l
828 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
829 mtdcr ocmdscr1, r3 /* Set Data Side */
830 mtdcr ocmiscr1, r3 /* Set Instruction Side */
831 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
832 mtdcr ocmdscr2, r3 /* Set Data Side */
833 mtdcr ocmiscr2, r3 /* Set Instruction Side */
834 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
838 #else /* CONFIG_405EZ */
839 /********************************************************************
840 * Setup OCM - On Chip Memory
841 *******************************************************************/
845 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
846 mfdcr r4, ocmdscntl /* get data-side IRAM config */
847 and r3, r3, r0 /* disable data-side IRAM */
848 and r4, r4, r0 /* disable data-side IRAM */
849 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
850 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
853 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
854 ori r3,r3,CFG_OCM_DATA_ADDR@l
856 addis r4, 0, 0xC000 /* OCM data area enabled */
859 #endif /* CONFIG_405EZ */
862 #ifdef CONFIG_NAND_SPL
864 * Copy SPL from cache into internal SRAM
866 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
868 lis r2,CFG_NAND_BOOT_SPL_SRC@h
869 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
870 lis r3,CFG_NAND_BOOT_SPL_DST@h
871 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
878 * Jump to code in RAM
882 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
883 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
892 #endif /* CONFIG_NAND_SPL */
894 /*----------------------------------------------------------------------- */
895 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
896 /*----------------------------------------------------------------------- */
897 #ifdef CFG_INIT_DCACHE_CS
898 /*----------------------------------------------------------------------- */
899 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
900 /* used as temporary stack pointer for stage0 */
901 /*----------------------------------------------------------------------- */
914 /* turn on data chache for this region */
918 /* set stack pointer and clear stack to known value */
920 lis r1,CFG_INIT_RAM_ADDR@h
921 ori r1,r1,CFG_INIT_SP_OFFSET@l
923 li r4,2048 /* we store 2048 words to stack */
926 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
927 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
929 lis r4,0xdead /* we store 0xdeaddead in the stack */
936 li r0, 0 /* Make room for stack frame header and */
937 stwu r0, -4(r1) /* clear final stack frame so that */
938 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
940 * Set up a dummy frame to store reset vector as return address.
941 * this causes stack underflow to reset board.
943 stwu r1, -8(r1) /* Save back chain and move SP */
944 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
945 ori r0, r0, RESET_VECTOR@l
946 stwu r1, -8(r1) /* Save back chain and move SP */
947 stw r0, +12(r1) /* Save return addr (underflow vect) */
949 #elif defined(CFG_TEMP_STACK_OCM) && \
950 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
955 /* Set up Stack at top of OCM */
956 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
957 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
959 /* Set up a zeroized stack frame so that backtrace works right */
965 * Set up a dummy frame to store reset vector as return address.
966 * this causes stack underflow to reset board.
968 stwu r1, -8(r1) /* Save back chain and move SP */
969 lis r0, RESET_VECTOR@h /* Address of reset vector */
970 ori r0, r0, RESET_VECTOR@l
971 stwu r1, -8(r1) /* Save back chain and move SP */
972 stw r0, +12(r1) /* Save return addr (underflow vect) */
973 #endif /* CFG_INIT_DCACHE_CS */
975 /*----------------------------------------------------------------------- */
976 /* Initialize SDRAM Controller */
977 /*----------------------------------------------------------------------- */
981 * Setup temporary stack pointer only for boards
982 * that do not use SDRAM SPD I2C stuff since it
983 * is already initialized to use DCACHE or OCM
986 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
987 lis r1, CFG_INIT_RAM_ADDR@h
988 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
990 li r0, 0 /* Make room for stack frame header and */
991 stwu r0, -4(r1) /* clear final stack frame so that */
992 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
994 * Set up a dummy frame to store reset vector as return address.
995 * this causes stack underflow to reset board.
997 stwu r1, -8(r1) /* Save back chain and move SP */
998 lis r0, RESET_VECTOR@h /* Address of reset vector */
999 ori r0, r0, RESET_VECTOR@l
1000 stwu r1, -8(r1) /* Save back chain and move SP */
1001 stw r0, +12(r1) /* Save return addr (underflow vect) */
1002 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
1004 #ifdef CONFIG_NAND_SPL
1005 bl nand_boot /* will not return */
1007 GET_GOT /* initialize GOT access */
1009 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1011 /* NEVER RETURNS! */
1012 bl board_init_f /* run first part of init code (from Flash) */
1013 #endif /* CONFIG_NAND_SPL */
1015 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1016 /*----------------------------------------------------------------------- */
1019 #ifndef CONFIG_NAND_SPL
1020 /*****************************************************************************/
1021 .globl _start_of_vectors
1025 /*TODO Fixup _start above so we can do this*/
1026 /* Critical input. */
1027 CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
1031 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1033 /* Data Storage exception. */
1034 STD_EXCEPTION(0x300, DataStorage, UnknownException)
1036 /* Instruction Storage exception. */
1037 STD_EXCEPTION(0x400, InstStorage, UnknownException)
1039 /* External Interrupt exception. */
1040 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
1042 /* Alignment exception. */
1050 addi r3,r1,STACK_FRAME_OVERHEAD
1052 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
1053 lwz r6,GOT(transfer_to_handler)
1057 .long AlignmentException - _start + EXC_OFF_SYS_RESET
1058 .long int_return - _start + EXC_OFF_SYS_RESET
1060 /* Program check exception */
1064 addi r3,r1,STACK_FRAME_OVERHEAD
1066 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
1067 lwz r6,GOT(transfer_to_handler)
1071 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
1072 .long int_return - _start + EXC_OFF_SYS_RESET
1074 /* No FPU on MPC8xx. This exception is not supposed to happen.
1076 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
1078 /* I guess we could implement decrementer, and may have
1079 * to someday for timekeeping.
1081 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
1082 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
1083 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
1084 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
1085 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
1087 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
1088 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
1090 /* On the MPC8xx, this is a software emulation interrupt. It occurs
1091 * for all unimplemented and illegal instructions.
1093 STD_EXCEPTION(0x1000, PIT, PITException)
1095 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
1096 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
1097 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
1098 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
1100 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
1101 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
1102 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
1103 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
1104 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
1105 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
1106 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
1108 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
1109 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
1110 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
1111 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
1113 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
1115 .globl _end_of_vectors
1122 * This code finishes saving the registers to the exception frame
1123 * and jumps to the appropriate handler for the exception.
1124 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1126 .globl transfer_to_handler
1127 transfer_to_handler:
1137 andi. r23,r23,MSR_PR
1138 mfspr r23,SPRG3 /* if from user, fix up tss.regs */
1140 addi r24,r1,STACK_FRAME_OVERHEAD
1141 stw r24,PT_REGS(r23)
1142 2: addi r2,r23,-TSS /* set r2 to current */
1146 andi. r24,r23,0x3f00 /* get vector offset */
1150 mtspr SPRG2,r22 /* r1 is now kernel sp */
1152 addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
1156 bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
1158 lwz r24,0(r23) /* virtual address of handler */
1159 lwz r23,4(r23) /* where to go when done */
1164 rfi /* jump to handler, enable MMU */
1167 mfmsr r28 /* Disable interrupts */
1171 SYNC /* Some chip revs need this... */
1186 lwz r2,_NIP(r1) /* Restore environment */
1197 mfmsr r28 /* Disable interrupts */
1201 SYNC /* Some chip revs need this... */
1216 lwz r2,_NIP(r1) /* Restore environment */
1218 mtspr 990,r2 /* SRR2 */
1219 mtspr 991,r0 /* SRR3 */
1229 addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
1231 mfmsr r12 /* save msr */
1233 mtmsr r9 /* disable EE and CE */
1234 addi r10,r0,0x0001 /* enable data cache for unused memory */
1235 mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
1236 or r10,r10,r9 /* bit 31 in dccr */
1239 /* do loop for # of congruence classes. */
1240 lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
1241 ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1242 lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1243 ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1245 addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1246 add r11,r10,r11 /* add to get to other side of cache line */
1247 ..flush_dcache_loop:
1248 lwz r3,0(r10) /* least recently used side */
1249 lwz r3,0(r11) /* the other side */
1250 dccci r0,r11 /* invalidate both sides */
1251 addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1252 addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1253 bdnz ..flush_dcache_loop
1254 sync /* allow memory access to complete */
1255 mtdccr r9 /* restore dccr */
1256 mtmsr r12 /* restore msr */
1259 .globl icache_enable
1262 bl invalidate_icache
1265 addis r3,r0, 0x8000 /* set bit 0 */
1269 .globl icache_disable
1271 addis r3,r0, 0x0000 /* clear bit 0 */
1276 .globl icache_status
1279 srwi r3, r3, 31 /* >>31 => select bit 0 */
1282 .globl dcache_enable
1285 bl invalidate_dcache
1288 addis r3,r0, 0x8000 /* set bit 0 */
1292 .globl dcache_disable
1297 addis r3,r0, 0x0000 /* clear bit 0 */
1301 .globl dcache_status
1304 srwi r3, r3, 31 /* >>31 => select bit 0 */
1312 #if !defined(CONFIG_440)
1324 /*------------------------------------------------------------------------------- */
1325 /* Function: out16 */
1326 /* Description: Output 16 bits */
1327 /*------------------------------------------------------------------------------- */
1333 /*------------------------------------------------------------------------------- */
1334 /* Function: out16r */
1335 /* Description: Byte reverse and output 16 bits */
1336 /*------------------------------------------------------------------------------- */
1342 /*------------------------------------------------------------------------------- */
1343 /* Function: out32r */
1344 /* Description: Byte reverse and output 32 bits */
1345 /*------------------------------------------------------------------------------- */
1351 /*------------------------------------------------------------------------------- */
1352 /* Function: in16 */
1353 /* Description: Input 16 bits */
1354 /*------------------------------------------------------------------------------- */
1360 /*------------------------------------------------------------------------------- */
1361 /* Function: in16r */
1362 /* Description: Input 16 bits and byte reverse */
1363 /*------------------------------------------------------------------------------- */
1369 /*------------------------------------------------------------------------------- */
1370 /* Function: in32r */
1371 /* Description: Input 32 bits and byte reverse */
1372 /*------------------------------------------------------------------------------- */
1378 /*------------------------------------------------------------------------------- */
1379 /* Function: ppcDcbf */
1380 /* Description: Data Cache block flush */
1381 /* Input: r3 = effective address */
1383 /*------------------------------------------------------------------------------- */
1389 /*------------------------------------------------------------------------------- */
1390 /* Function: ppcDcbi */
1391 /* Description: Data Cache block Invalidate */
1392 /* Input: r3 = effective address */
1394 /*------------------------------------------------------------------------------- */
1400 /*------------------------------------------------------------------------------- */
1401 /* Function: ppcSync */
1402 /* Description: Processor Synchronize */
1405 /*------------------------------------------------------------------------------- */
1412 * void relocate_code (addr_sp, gd, addr_moni)
1414 * This "function" does not return, instead it continues in RAM
1415 * after relocating the monitor code.
1419 * r5 = length in bytes
1420 * r6 = cachelinesize
1422 .globl relocate_code
1424 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1425 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1426 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1428 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1429 * to speed up the boot process. Now this cache needs to be disabled.
1431 iccci 0,0 /* Invalidate inst cache */
1432 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1435 addi r1,r0,0x0000 /* TLB entry #0 */
1436 tlbre r0,r1,0x0002 /* Read contents */
1437 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1438 tlbwe r0,r1,0x0002 /* Save it out */
1442 mr r1, r3 /* Set new stack pointer */
1443 mr r9, r4 /* Save copy of Init Data pointer */
1444 mr r10, r5 /* Save copy of Destination Address */
1446 mr r3, r5 /* Destination Address */
1447 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1448 ori r4, r4, CFG_MONITOR_BASE@l
1449 lwz r5, GOT(__init_end)
1451 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
1456 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1462 /* First our own GOT */
1464 /* the the one used by the C code */
1474 beq cr1,4f /* In place copy is not necessary */
1475 beq 7f /* Protect against 0 count */
1494 * Now flush the cache: note that we must start from a cache aligned
1495 * address. Otherwise we might miss one cache line.
1499 beq 7f /* Always flush prefetch queue in any case */
1507 sync /* Wait for all dcbst to complete on bus */
1513 7: sync /* Wait for all icbi to complete on bus */
1517 * We are done. Do not return, instead branch to second part of board
1518 * initialization, now running from RAM.
1521 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1523 blr /* NEVER RETURNS! */
1528 * Relocation Function, r14 point to got2+0x8000
1530 * Adjust got2 pointers, no need to check for 0, this code
1531 * already puts a few entries in the table.
1533 li r0,__got2_entries@sectoff@l
1534 la r3,GOT(_GOT2_TABLE_)
1535 lwz r11,GOT(_GOT2_TABLE_)
1545 * Now adjust the fixups and the pointers to the fixups
1546 * in case we need to move ourselves again.
1548 2: li r0,__fixup_entries@sectoff@l
1549 lwz r3,GOT(_FIXUP_TABLE_)
1563 * Now clear BSS segment
1565 lwz r3,GOT(__bss_start)
1579 mr r3, r9 /* Init Data pointer */
1580 mr r4, r10 /* Destination Address */
1584 * Copy exception vector code to low memory
1587 * r7: source address, r8: end address, r9: target address
1592 lwz r8, GOT(_end_of_vectors)
1594 li r9, 0x100 /* reset vector always at 0x100 */
1597 bgelr /* return if r7>=r8 - just in case */
1599 mflr r4 /* save link register */
1609 * relocate `hdlr' and `int_return' entries
1611 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1612 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1615 addi r7, r7, 0x100 /* next exception vector */
1619 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1622 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1625 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1626 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1629 addi r7, r7, 0x100 /* next exception vector */
1633 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1634 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1637 addi r7, r7, 0x100 /* next exception vector */
1641 #if !defined(CONFIG_440)
1642 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1643 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1644 mtmsr r7 /* change MSR */
1647 b __440_msr_continue
1650 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1651 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1659 mtlr r4 /* restore link register */
1663 * Function: relocate entries for one exception vector
1666 lwz r0, 0(r7) /* hdlr ... */
1667 add r0, r0, r3 /* ... += dest_addr */
1670 lwz r0, 4(r7) /* int_return ... */
1671 add r0, r0, r3 /* ... += dest_addr */
1676 #if defined(CONFIG_440)
1677 /*----------------------------------------------------------------------------+
1679 +----------------------------------------------------------------------------*/
1680 function_prolog(dcbz_area)
1681 rlwinm. r5,r4,0,27,31
1682 rlwinm r5,r4,27,5,31
1691 function_epilog(dcbz_area)
1693 /*----------------------------------------------------------------------------+
1694 | dflush. Assume 32K at vector address is cachable.
1695 +----------------------------------------------------------------------------*/
1696 function_prolog(dflush)
1698 rlwinm r8,r9,0,15,13
1699 rlwinm r8,r8,0,17,15
1718 function_epilog(dflush)
1719 #endif /* CONFIG_440 */
1720 #endif /* CONFIG_NAND_SPL */
1722 /*------------------------------------------------------------------------------- */
1724 /* Description: Input 8 bits */
1725 /*------------------------------------------------------------------------------- */
1731 /*------------------------------------------------------------------------------- */
1732 /* Function: out8 */
1733 /* Description: Output 8 bits */
1734 /*------------------------------------------------------------------------------- */
1740 /*------------------------------------------------------------------------------- */
1741 /* Function: out32 */
1742 /* Description: Output 32 bits */
1743 /*------------------------------------------------------------------------------- */
1749 /*------------------------------------------------------------------------------- */
1750 /* Function: in32 */
1751 /* Description: Input 32 bits */
1752 /*------------------------------------------------------------------------------- */
1759 iccci r0,r0 /* for 405, iccci invalidates the */
1760 blr /* entire I cache */
1763 addi r6,0,0x0000 /* clear GPR 6 */
1764 /* Do loop for # of dcache congruence classes. */
1765 lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
1766 ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1767 /* NOTE: dccci invalidates both */
1768 mtctr r7 /* ways in the D cache */
1770 dccci 0,r6 /* invalidate line */
1771 addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1775 /**************************************************************************/
1776 /* PPC405EP specific stuff */
1777 /**************************************************************************/
1781 #ifdef CONFIG_BUBINGA
1783 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1784 * function) to support FPGA and NVRAM accesses below.
1787 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1788 ori r3,r3,GPIO0_OSRH@l
1789 lis r4,CFG_GPIO0_OSRH@h
1790 ori r4,r4,CFG_GPIO0_OSRH@l
1793 ori r3,r3,GPIO0_OSRL@l
1794 lis r4,CFG_GPIO0_OSRL@h
1795 ori r4,r4,CFG_GPIO0_OSRL@l
1798 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1799 ori r3,r3,GPIO0_ISR1H@l
1800 lis r4,CFG_GPIO0_ISR1H@h
1801 ori r4,r4,CFG_GPIO0_ISR1H@l
1803 lis r3,GPIO0_ISR1L@h
1804 ori r3,r3,GPIO0_ISR1L@l
1805 lis r4,CFG_GPIO0_ISR1L@h
1806 ori r4,r4,CFG_GPIO0_ISR1L@l
1809 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1810 ori r3,r3,GPIO0_TSRH@l
1811 lis r4,CFG_GPIO0_TSRH@h
1812 ori r4,r4,CFG_GPIO0_TSRH@l
1815 ori r3,r3,GPIO0_TSRL@l
1816 lis r4,CFG_GPIO0_TSRL@h
1817 ori r4,r4,CFG_GPIO0_TSRL@l
1820 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1821 ori r3,r3,GPIO0_TCR@l
1822 lis r4,CFG_GPIO0_TCR@h
1823 ori r4,r4,CFG_GPIO0_TCR@l
1826 li r3,pb1ap /* program EBC bank 1 for RTC access */
1828 lis r3,CFG_EBC_PB1AP@h
1829 ori r3,r3,CFG_EBC_PB1AP@l
1833 lis r3,CFG_EBC_PB1CR@h
1834 ori r3,r3,CFG_EBC_PB1CR@l
1837 li r3,pb1ap /* program EBC bank 1 for RTC access */
1839 lis r3,CFG_EBC_PB1AP@h
1840 ori r3,r3,CFG_EBC_PB1AP@l
1844 lis r3,CFG_EBC_PB1CR@h
1845 ori r3,r3,CFG_EBC_PB1CR@l
1848 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1850 lis r3,CFG_EBC_PB4AP@h
1851 ori r3,r3,CFG_EBC_PB4AP@l
1855 lis r3,CFG_EBC_PB4CR@h
1856 ori r3,r3,CFG_EBC_PB4CR@l
1860 #ifndef CFG_CPC0_PCI
1861 li r3,CPC0_PCI_HOST_CFG_EN
1862 #ifdef CONFIG_BUBINGA
1864 !-----------------------------------------------------------------------
1865 ! Check FPGA for PCI internal/external arbitration
1866 ! If board is set to internal arbitration, update cpc0_pci
1867 !-----------------------------------------------------------------------
1869 addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1870 ori r5,r5,FPGA_REG1@l
1871 lbz r5,0x0(r5) /* read to get PCI arb selection */
1872 andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1873 beq ..pci_cfg_set /* if not set, then bypass reg write*/
1875 ori r3,r3,CPC0_PCI_ARBIT_EN
1876 #else /* CFG_CPC0_PCI */
1878 #endif /* CFG_CPC0_PCI */
1880 mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1883 !-----------------------------------------------------------------------
1884 ! Check to see if chip is in bypass mode.
1885 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1886 ! CPU reset Otherwise, skip this step and keep going.
1887 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1888 ! will not be fast enough for the SDRAM (min 66MHz)
1889 !-----------------------------------------------------------------------
1891 mfdcr r5, CPC0_PLLMR1
1892 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1895 beq pll_done /* if SSCS =b'1' then PLL has */
1896 /* already been set */
1897 /* and CPU has been reset */
1898 /* so skip to next section */
1900 #ifdef CONFIG_BUBINGA
1902 !-----------------------------------------------------------------------
1903 ! Read NVRAM to get value to write in PLLMR.
1904 ! If value has not been correctly saved, write default value
1905 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1906 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1908 ! WARNING: This code assumes the first three words in the nvram_t
1909 ! structure in openbios.h. Changing the beginning of
1910 ! the structure will break this code.
1912 !-----------------------------------------------------------------------
1914 addis r3,0,NVRAM_BASE@h
1915 addi r3,r3,NVRAM_BASE@l
1918 addis r5,0,NVRVFY1@h
1919 addi r5,r5,NVRVFY1@l
1920 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1924 addis r5,0,NVRVFY2@h
1925 addi r5,r5,NVRVFY2@l
1926 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1928 addi r3,r3,8 /* Skip over conf_size */
1929 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1930 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1931 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1932 cmpi cr0,0,r5,1 /* See if PLL is locked */
1935 #endif /* CONFIG_BUBINGA */
1937 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1938 ori r3,r3,PLLMR0_DEFAULT@l /* */
1939 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1940 ori r4,r4,PLLMR1_DEFAULT@l /* */
1942 b pll_write /* Write the CPC0_PLLMR with new value */
1946 !-----------------------------------------------------------------------
1947 ! Clear Soft Reset Register
1948 ! This is needed to enable PCI if not booting from serial EPROM
1949 !-----------------------------------------------------------------------
1959 blr /* return to main code */
1962 !-----------------------------------------------------------------------------
1963 ! Function: pll_write
1964 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1966 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1968 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1969 ! 4. PLL Reset is cleared
1970 ! 5. Wait 100us for PLL to lock
1971 ! 6. A core reset is performed
1972 ! Input: r3 = Value to write to CPC0_PLLMR0
1973 ! Input: r4 = Value to write to CPC0_PLLMR1
1975 !-----------------------------------------------------------------------------
1980 ori r5,r5,0x0101 /* Stop the UART clocks */
1981 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1983 mfdcr r5, CPC0_PLLMR1
1984 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1985 mtdcr CPC0_PLLMR1,r5
1986 oris r5,r5,0x4000 /* Set PLL Reset */
1987 mtdcr CPC0_PLLMR1,r5
1989 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1990 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1991 oris r5,r5,0x4000 /* Set PLL Reset */
1992 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1993 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1994 mtdcr CPC0_PLLMR1,r5
1997 ! Wait min of 100us for PLL to lock.
1998 ! See CMOS 27E databook for more info.
1999 ! At 200MHz, that means waiting 20,000 instructions
2001 addi r3,0,20000 /* 2000 = 0x4e20 */
2006 oris r5,r5,0x8000 /* Enable PLL */
2007 mtdcr CPC0_PLLMR1,r5 /* Engage */
2010 * Reset CPU to guarantee timings are OK
2011 * Not sure if this is needed...
2014 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2015 /* execution will continue from the poweron */
2016 /* vector of 0xfffffffc */
2017 #endif /* CONFIG_405EP */
2019 #if defined(CONFIG_440)
2020 /*----------------------------------------------------------------------------+
2022 +----------------------------------------------------------------------------*/
2023 function_prolog(mttlb3)
2026 function_epilog(mttlb3)
2028 /*----------------------------------------------------------------------------+
2030 +----------------------------------------------------------------------------*/
2031 function_prolog(mftlb3)
2034 function_epilog(mftlb3)
2036 /*----------------------------------------------------------------------------+
2038 +----------------------------------------------------------------------------*/
2039 function_prolog(mttlb2)
2042 function_epilog(mttlb2)
2044 /*----------------------------------------------------------------------------+
2046 +----------------------------------------------------------------------------*/
2047 function_prolog(mftlb2)
2050 function_epilog(mftlb2)
2052 /*----------------------------------------------------------------------------+
2054 +----------------------------------------------------------------------------*/
2055 function_prolog(mttlb1)
2058 function_epilog(mttlb1)
2060 /*----------------------------------------------------------------------------+
2062 +----------------------------------------------------------------------------*/
2063 function_prolog(mftlb1)
2066 function_epilog(mftlb1)
2067 #endif /* CONFIG_440 */