2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
46 *-------------------------------------------------------------------------------
49 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 * The processor starts at 0xfffffffc and the code is executed
54 * in memory, but as long we don't jump around before relocating.
55 * board_init lies at a quite high address and when the cpu has
56 * jumped there, everything is ok.
57 * This works because the cpu gives the FLASH (CS0) the whole
58 * address space at startup, and board_init lies as a echo of
59 * the flash somewhere up there in the memorymap.
61 * board_init will change CS0 to be positioned at the correct
62 * address and (s)dram will be positioned at address 0
68 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
70 #include <ppc_asm.tmpl>
73 #include <asm/cache.h>
75 #include <asm/ppc4xx-isram.h>
77 #ifndef CONFIG_IDENT_STRING
78 #define CONFIG_IDENT_STRING ""
81 #ifdef CONFIG_SYS_INIT_DCACHE_CS
82 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
85 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
86 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
87 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
90 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
93 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
94 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
95 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
98 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
101 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
102 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
103 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
106 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
109 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
110 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
111 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
114 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
117 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
118 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
119 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
122 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
125 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
126 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
127 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
130 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
133 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
134 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
135 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
138 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
141 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
142 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
143 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
153 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
154 * used as temporary stack pointer for the primordial stack
156 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
157 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
158 EBC_BXAP_TWT_ENCODE(7) | \
159 EBC_BXAP_BCE_DISABLE | \
160 EBC_BXAP_BCT_2TRANS | \
161 EBC_BXAP_CSN_ENCODE(0) | \
162 EBC_BXAP_OEN_ENCODE(0) | \
163 EBC_BXAP_WBN_ENCODE(0) | \
164 EBC_BXAP_WBF_ENCODE(0) | \
165 EBC_BXAP_TH_ENCODE(2) | \
166 EBC_BXAP_RE_DISABLED | \
167 EBC_BXAP_SOR_NONDELAYED | \
168 EBC_BXAP_BEM_WRITEONLY | \
169 EBC_BXAP_PEN_DISABLED)
170 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
171 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
172 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
176 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
177 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
178 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
180 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
182 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
183 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
187 * Unless otherwise overriden, enable two 128MB cachable instruction regions
188 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
189 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
191 #if !defined(CONFIG_SYS_FLASH_BASE)
192 /* If not already defined, set it to the "last" 128MByte region */
193 # define CONFIG_SYS_FLASH_BASE 0xf8000000
195 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
196 # define CONFIG_SYS_ICACHE_SACR_VALUE \
197 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
198 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
199 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
200 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
202 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
203 # define CONFIG_SYS_DCACHE_SACR_VALUE \
205 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
207 #define function_prolog(func_name) .text; \
211 #define function_epilog(func_name) .type func_name,@function; \
212 .size func_name,.-func_name
214 /* We don't want the MMU yet.
217 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
220 .extern ext_bus_cntlr_init
221 #ifdef CONFIG_NAND_U_BOOT
222 .extern reconfig_tlb0
226 * Set up GOT: Global Offset Table
228 * Use r14 to access the GOT
230 #if !defined(CONFIG_NAND_SPL)
232 GOT_ENTRY(_GOT2_TABLE_)
233 GOT_ENTRY(_FIXUP_TABLE_)
236 GOT_ENTRY(_start_of_vectors)
237 GOT_ENTRY(_end_of_vectors)
238 GOT_ENTRY(transfer_to_handler)
240 GOT_ENTRY(__init_end)
242 GOT_ENTRY(__bss_start)
244 #endif /* CONFIG_NAND_SPL */
246 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
248 * NAND U-Boot image is started from offset 0
251 #if defined(CONFIG_440)
255 bl cpu_init_f /* run low-level CPU init code (from Flash) */
260 * 440 Startup -- on reset only the top 4k of the effective
261 * address space is mapped in by an entry in the instruction
262 * and data shadow TLB. The .bootpg section is located in the
263 * top 4k & does only what's necessary to map in the the rest
264 * of the boot rom. Once the boot rom is mapped in we can
265 * proceed with normal startup.
267 * NOTE: CS0 only covers the top 2MB of the effective address
271 #if defined(CONFIG_440)
272 #if !defined(CONFIG_NAND_SPL)
273 .section .bootpg,"ax"
277 /**************************************************************************/
279 /*--------------------------------------------------------------------+
280 | 440EPX BUP Change - Hardware team request
281 +--------------------------------------------------------------------*/
282 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
287 /*----------------------------------------------------------------+
288 | Core bug fix. Clear the esr
289 +-----------------------------------------------------------------*/
292 /*----------------------------------------------------------------*/
293 /* Clear and set up some registers. */
294 /*----------------------------------------------------------------*/
295 iccci r0,r0 /* NOTE: operands not used for 440 */
296 dccci r0,r0 /* NOTE: operands not used for 440 */
303 /* NOTE: 440GX adds machine check status regs */
304 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
311 /*----------------------------------------------------------------*/
313 /*----------------------------------------------------------------*/
314 /* Disable store gathering & broadcast, guarantee inst/data
315 * cache block touch, force load/store alignment
316 * (see errata 1.12: 440_33)
318 lis r1,0x0030 /* store gathering & broadcast disable */
319 ori r1,r1,0x6000 /* cache touch */
322 /*----------------------------------------------------------------*/
323 /* Initialize debug */
324 /*----------------------------------------------------------------*/
326 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
327 bne skip_debug_init /* if set, don't clear debug register */
340 mtspr dbsr,r1 /* Clear all valid bits */
343 #if defined (CONFIG_440SPE)
344 /*----------------------------------------------------------------+
345 | Initialize Core Configuration Reg1.
346 | a. ICDPEI: Record even parity. Normal operation.
347 | b. ICTPEI: Record even parity. Normal operation.
348 | c. DCTPEI: Record even parity. Normal operation.
349 | d. DCDPEI: Record even parity. Normal operation.
350 | e. DCUPEI: Record even parity. Normal operation.
351 | f. DCMPEI: Record even parity. Normal operation.
352 | g. FCOM: Normal operation
353 | h. MMUPEI: Record even parity. Normal operation.
354 | i. FFF: Flush only as much data as necessary.
355 | j. TCS: Timebase increments from CPU clock.
356 +-----------------------------------------------------------------*/
360 /*----------------------------------------------------------------+
361 | Reset the timebase.
362 | The previous write to CCR1 sets the timebase source.
363 +-----------------------------------------------------------------*/
368 /*----------------------------------------------------------------*/
369 /* Setup interrupt vectors */
370 /*----------------------------------------------------------------*/
371 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
373 mtspr ivor0,r1 /* Critical input */
375 mtspr ivor1,r1 /* Machine check */
377 mtspr ivor2,r1 /* Data storage */
379 mtspr ivor3,r1 /* Instruction storage */
381 mtspr ivor4,r1 /* External interrupt */
383 mtspr ivor5,r1 /* Alignment */
385 mtspr ivor6,r1 /* Program check */
387 mtspr ivor7,r1 /* Floating point unavailable */
389 mtspr ivor8,r1 /* System call */
391 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
393 mtspr ivor10,r1 /* Decrementer */
395 mtspr ivor13,r1 /* Data TLB error */
397 mtspr ivor14,r1 /* Instr TLB error */
399 mtspr ivor15,r1 /* Debug */
401 /*----------------------------------------------------------------*/
402 /* Configure cache regions */
403 /*----------------------------------------------------------------*/
421 /*----------------------------------------------------------------*/
422 /* Cache victim limits */
423 /*----------------------------------------------------------------*/
424 /* floors 0, ceiling max to use the entire cache -- nothing locked
431 /*----------------------------------------------------------------+
432 |Initialize MMUCR[STID] = 0.
433 +-----------------------------------------------------------------*/
440 /*----------------------------------------------------------------*/
441 /* Clear all TLB entries -- TID = 0, TS = 0 */
442 /*----------------------------------------------------------------*/
444 li r1,0x003f /* 64 TLB entries */
446 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
452 /*----------------------------------------------------------------*/
453 /* TLB entry setup -- step thru tlbtab */
454 /*----------------------------------------------------------------*/
455 #if defined(CONFIG_440SPE)
456 /*----------------------------------------------------------------*/
457 /* We have different TLB tables for revA and rev B of 440SPe */
458 /*----------------------------------------------------------------*/
470 bl tlbtab /* Get tlbtab pointer */
473 li r1,0x003f /* 64 TLB entries max */
480 beq 2f /* 0 marks end */
483 tlbwe r0,r4,0 /* TLB Word 0 */
484 tlbwe r1,r4,1 /* TLB Word 1 */
485 tlbwe r2,r4,2 /* TLB Word 2 */
486 addi r4,r4,1 /* Next TLB */
489 /*----------------------------------------------------------------*/
490 /* Continue from 'normal' start */
491 /*----------------------------------------------------------------*/
497 mtspr srr1,r0 /* Keep things disabled for now */
501 #endif /* CONFIG_440 */
504 * r3 - 1st arg to board_init(): IMMP pointer
505 * r4 - 2nd arg to board_init(): boot flag
507 #ifndef CONFIG_NAND_SPL
509 .long 0x27051956 /* U-Boot Magic Number */
510 .globl version_string
512 .ascii U_BOOT_VERSION
513 .ascii " (", __DATE__, " - ", __TIME__, ")"
514 .ascii CONFIG_IDENT_STRING, "\0"
516 . = EXC_OFF_SYS_RESET
517 .globl _start_of_vectors
520 /* Critical input. */
521 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
525 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
527 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
528 #endif /* CONFIG_440 */
530 /* Data Storage exception. */
531 STD_EXCEPTION(0x300, DataStorage, UnknownException)
533 /* Instruction Storage exception. */
534 STD_EXCEPTION(0x400, InstStorage, UnknownException)
536 /* External Interrupt exception. */
537 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
539 /* Alignment exception. */
542 EXCEPTION_PROLOG(SRR0, SRR1)
547 addi r3,r1,STACK_FRAME_OVERHEAD
549 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
550 lwz r6,GOT(transfer_to_handler)
554 .long AlignmentException - _start + _START_OFFSET
555 .long int_return - _start + _START_OFFSET
557 /* Program check exception */
560 EXCEPTION_PROLOG(SRR0, SRR1)
561 addi r3,r1,STACK_FRAME_OVERHEAD
563 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
564 lwz r6,GOT(transfer_to_handler)
568 .long ProgramCheckException - _start + _START_OFFSET
569 .long int_return - _start + _START_OFFSET
572 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
573 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
574 STD_EXCEPTION(0xa00, APU, UnknownException)
576 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
579 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
580 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
582 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
583 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
584 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
586 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
588 .globl _end_of_vectors
595 /*****************************************************************************/
596 #if defined(CONFIG_440)
598 /*----------------------------------------------------------------*/
599 /* Clear and set up some registers. */
600 /*----------------------------------------------------------------*/
603 mtspr dec,r0 /* prevent dec exceptions */
604 mtspr tbl,r0 /* prevent fit & wdt exceptions */
606 mtspr tsr,r1 /* clear all timer exception status */
607 mtspr tcr,r0 /* disable all */
608 mtspr esr,r0 /* clear exception syndrome register */
609 mtxer r0 /* clear integer exception register */
611 /*----------------------------------------------------------------*/
612 /* Debug setup -- some (not very good) ice's need an event*/
613 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
614 /* value you need in this case 0x8cff 0000 should do the trick */
615 /*----------------------------------------------------------------*/
616 #if defined(CONFIG_SYS_INIT_DBCR)
619 mtspr dbsr,r1 /* Clear all status bits */
620 lis r0,CONFIG_SYS_INIT_DBCR@h
621 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
626 /*----------------------------------------------------------------*/
627 /* Setup the internal SRAM */
628 /*----------------------------------------------------------------*/
631 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
632 /* Clear Dcache to use as RAM */
633 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
634 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
635 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
636 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
637 rlwinm. r5,r4,0,27,31
649 * Lock the init-ram/stack in d-cache, so that other regions
650 * may use d-cache as well
651 * Note, that this current implementation locks exactly 4k
652 * of d-cache, so please make sure that you don't define a
653 * bigger init-ram area. Take a look at the lwmon5 440EPx
654 * implementation as a reference.
658 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
674 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
676 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
677 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
678 /* not all PPC's have internal SRAM usable as L2-cache */
679 #if defined(CONFIG_440GX) || \
680 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
681 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
682 defined(CONFIG_460SX)
683 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
689 and r1,r1,r2 /* Disable parity check */
692 and r1,r1,r2 /* Disable pwr mgmt */
695 lis r1,0x8000 /* BAS = 8000_0000 */
696 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
697 ori r1,r1,0x0980 /* first 64k */
698 mtdcr ISRAM0_SB0CR,r1
700 ori r1,r1,0x0980 /* second 64k */
701 mtdcr ISRAM0_SB1CR,r1
703 ori r1,r1, 0x0980 /* third 64k */
704 mtdcr ISRAM0_SB2CR,r1
706 ori r1,r1, 0x0980 /* fourth 64k */
707 mtdcr ISRAM0_SB3CR,r1
708 #elif defined(CONFIG_440SPE)
709 lis r1,0x0000 /* BAS = 0000_0000 */
710 ori r1,r1,0x0984 /* first 64k */
711 mtdcr ISRAM0_SB0CR,r1
713 ori r1,r1,0x0984 /* second 64k */
714 mtdcr ISRAM0_SB1CR,r1
716 ori r1,r1, 0x0984 /* third 64k */
717 mtdcr ISRAM0_SB2CR,r1
719 ori r1,r1, 0x0984 /* fourth 64k */
720 mtdcr ISRAM0_SB3CR,r1
721 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
722 lis r1,0x4000 /* BAS = 8000_0000 */
723 ori r1,r1,0x4580 /* 16k */
724 mtdcr ISRAM0_SB0CR,r1
725 #elif defined(CONFIG_460SX)
726 lis r1,0x0000 /* BAS = 0000_0000 */
727 ori r1,r1,0x0B84 /* first 128k */
728 mtdcr ISRAM0_SB0CR,r1
730 ori r1,r1,0x0B84 /* second 128k */
731 mtdcr ISRAM0_SB1CR,r1
733 ori r1,r1, 0x0B84 /* third 128k */
734 mtdcr ISRAM0_SB2CR,r1
736 ori r1,r1, 0x0B84 /* fourth 128k */
737 mtdcr ISRAM0_SB3CR,r1
738 #elif defined(CONFIG_440GP)
739 ori r1,r1,0x0380 /* 8k rw */
740 mtdcr ISRAM0_SB0CR,r1
741 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
743 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
745 /*----------------------------------------------------------------*/
746 /* Setup the stack in internal SRAM */
747 /*----------------------------------------------------------------*/
748 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
749 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
752 stwu r0,-4(r1) /* Terminate call chain */
754 stwu r1,-8(r1) /* Save back chain and move SP */
755 lis r0,RESET_VECTOR@h /* Address of reset vector */
756 ori r0,r0, RESET_VECTOR@l
757 stwu r1,-8(r1) /* Save back chain and move SP */
758 stw r0,+12(r1) /* Save return addr (underflow vect) */
760 #ifdef CONFIG_NAND_SPL
761 bl nand_boot_common /* will not return */
765 bl cpu_init_f /* run low-level CPU init code (from Flash) */
769 #endif /* CONFIG_440 */
771 /*****************************************************************************/
773 /*----------------------------------------------------------------------- */
774 /* Set up some machine state registers. */
775 /*----------------------------------------------------------------------- */
776 addi r0,r0,0x0000 /* initialize r0 to zero */
777 mtspr esr,r0 /* clear Exception Syndrome Reg */
778 mttcr r0 /* timer control register */
779 mtexier r0 /* disable all interrupts */
780 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
781 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
782 mtdbsr r4 /* clear/reset the dbsr */
783 mtexisr r4 /* clear all pending interrupts */
785 mtexier r4 /* enable critical exceptions */
786 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
787 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
788 mtiocr r4 /* since bit not used) & DRC to latch */
789 /* data bus on rising edge of CAS */
790 /*----------------------------------------------------------------------- */
792 /*----------------------------------------------------------------------- */
794 /*----------------------------------------------------------------------- */
795 /* Invalidate i-cache and d-cache TAG arrays. */
796 /*----------------------------------------------------------------------- */
797 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
798 addi r4,0,1024 /* 1/4 of I-cache */
803 addic. r3,r3,-16 /* move back one cache line */
804 bne ..cloop /* loop back to do rest until r3 = 0 */
807 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
808 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
811 /* first copy IOP480 register base address into r3 */
812 addis r3,0,0x5000 /* IOP480 register base address hi */
813 /* ori r3,r3,0x0000 / IOP480 register base address lo */
816 /* use r4 as the working variable */
817 /* turn on CS3 (LOCCTL.7) */
818 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
819 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
820 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
823 #ifdef CONFIG_DASA_SIM
824 /* use r4 as the working variable */
825 /* turn on MA17 (LOCCTL.7) */
826 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
827 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
828 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
831 /* turn on MA16..13 (LCS0BRD.12 = 0) */
832 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
833 andi. r4,r4,0xefff /* make bit 12 = 0 */
834 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
836 /* make sure above stores all comlete before going on */
839 /* last thing, set local init status done bit (DEVINIT.31) */
840 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
841 oris r4,r4,0x8000 /* make bit 31 = 1 */
842 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
844 /* clear all pending interrupts and disable all interrupts */
845 li r4,-1 /* set p1 to 0xffffffff */
846 stw r4,0x1b0(r3) /* clear all pending interrupts */
847 stw r4,0x1b8(r3) /* clear all pending interrupts */
848 li r4,0 /* set r4 to 0 */
849 stw r4,0x1b4(r3) /* disable all interrupts */
850 stw r4,0x1bc(r3) /* disable all interrupts */
852 /* make sure above stores all comlete before going on */
855 /* Set-up icache cacheability. */
856 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
857 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
861 /* Set-up dcache cacheability. */
862 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
863 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
866 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
867 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
868 li r0, 0 /* Make room for stack frame header and */
869 stwu r0, -4(r1) /* clear final stack frame so that */
870 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
872 GET_GOT /* initialize GOT access */
874 bl board_init_f /* run first part of init code (from Flash) */
876 #endif /* CONFIG_IOP480 */
878 /*****************************************************************************/
879 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
880 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
881 defined(CONFIG_405EX) || defined(CONFIG_405)
882 /*----------------------------------------------------------------------- */
883 /* Clear and set up some registers. */
884 /*----------------------------------------------------------------------- */
886 #if !defined(CONFIG_405EX)
890 * On 405EX, completely clearing the SGR leads to PPC hangup
891 * upon PCIe configuration access. The PCIe memory regions
892 * need to be guarded!
899 mtesr r4 /* clear Exception Syndrome Reg */
900 mttcr r4 /* clear Timer Control Reg */
901 mtxer r4 /* clear Fixed-Point Exception Reg */
902 mtevpr r4 /* clear Exception Vector Prefix Reg */
903 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
904 /* dbsr is cleared by setting bits to 1) */
905 mtdbsr r4 /* clear/reset the dbsr */
907 /* Invalidate the i- and d-caches. */
911 /* Set-up icache cacheability. */
912 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
913 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
917 /* Set-up dcache cacheability. */
918 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
919 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
922 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
923 && !defined (CONFIG_XILINX_405)
924 /*----------------------------------------------------------------------- */
925 /* Tune the speed and size for flash CS0 */
926 /*----------------------------------------------------------------------- */
927 bl ext_bus_cntlr_init
930 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
932 * For boards that don't have OCM and can't use the data cache
933 * for their primordial stack, setup stack here directly after the
934 * SDRAM is initialized in ext_bus_cntlr_init.
936 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
937 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
939 li r0, 0 /* Make room for stack frame header and */
940 stwu r0, -4(r1) /* clear final stack frame so that */
941 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
943 * Set up a dummy frame to store reset vector as return address.
944 * this causes stack underflow to reset board.
946 stwu r1, -8(r1) /* Save back chain and move SP */
947 lis r0, RESET_VECTOR@h /* Address of reset vector */
948 ori r0, r0, RESET_VECTOR@l
949 stwu r1, -8(r1) /* Save back chain and move SP */
950 stw r0, +12(r1) /* Save return addr (underflow vect) */
951 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
953 #if defined(CONFIG_405EP)
954 /*----------------------------------------------------------------------- */
955 /* DMA Status, clear to come up clean */
956 /*----------------------------------------------------------------------- */
957 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
961 bl ppc405ep_init /* do ppc405ep specific init */
962 #endif /* CONFIG_405EP */
964 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
965 #if defined(CONFIG_405EZ)
966 /********************************************************************
967 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
968 *******************************************************************/
970 * We can map the OCM on the PLB3, so map it at
971 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
973 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
974 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
975 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
976 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
977 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
978 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
981 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
982 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
983 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
984 mtdcr ocmdscr1, r3 /* Set Data Side */
985 mtdcr ocmiscr1, r3 /* Set Instruction Side */
986 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
987 mtdcr ocmdscr2, r3 /* Set Data Side */
988 mtdcr ocmiscr2, r3 /* Set Instruction Side */
989 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
993 #else /* CONFIG_405EZ */
994 /********************************************************************
995 * Setup OCM - On Chip Memory
996 *******************************************************************/
1000 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
1001 mfdcr r4, ocmdscntl /* get data-side IRAM config */
1002 and r3, r3, r0 /* disable data-side IRAM */
1003 and r4, r4, r0 /* disable data-side IRAM */
1004 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
1005 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
1008 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1009 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1011 addis r4, 0, 0xC000 /* OCM data area enabled */
1014 #endif /* CONFIG_405EZ */
1017 /*----------------------------------------------------------------------- */
1018 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1019 /*----------------------------------------------------------------------- */
1020 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1023 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1024 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1029 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1030 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1034 * Enable the data cache for the 128MB storage access control region
1035 * at CONFIG_SYS_INIT_RAM_ADDR.
1038 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1039 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1043 * Preallocate data cache lines to be used to avoid a subsequent
1044 * cache miss and an ensuing machine check exception when exceptions
1049 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1050 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1052 lis r4, CONFIG_SYS_INIT_RAM_END@h
1053 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1056 * Convert the size, in bytes, to the number of cache lines/blocks
1059 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1060 srwi r5, r4, L1_CACHE_SHIFT
1066 /* Preallocate the computed number of cache blocks. */
1067 ..alloc_dcache_block:
1069 addi r3, r3, L1_CACHE_BYTES
1070 bdnz ..alloc_dcache_block
1074 * Load the initial stack pointer and data area and convert the size,
1075 * in bytes, to the number of words to initialize to a known value.
1077 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1078 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1080 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1081 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1084 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1085 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1087 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1088 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1095 * Make room for stack frame header and clear final stack frame so
1096 * that stack backtraces terminate cleanly.
1102 * Set up a dummy frame to store reset vector as return address.
1103 * this causes stack underflow to reset board.
1105 stwu r1, -8(r1) /* Save back chain and move SP */
1106 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1107 ori r0, r0, RESET_VECTOR@l
1108 stwu r1, -8(r1) /* Save back chain and move SP */
1109 stw r0, +12(r1) /* Save return addr (underflow vect) */
1111 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1112 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1117 /* Set up Stack at top of OCM */
1118 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1119 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1121 /* Set up a zeroized stack frame so that backtrace works right */
1127 * Set up a dummy frame to store reset vector as return address.
1128 * this causes stack underflow to reset board.
1130 stwu r1, -8(r1) /* Save back chain and move SP */
1131 lis r0, RESET_VECTOR@h /* Address of reset vector */
1132 ori r0, r0, RESET_VECTOR@l
1133 stwu r1, -8(r1) /* Save back chain and move SP */
1134 stw r0, +12(r1) /* Save return addr (underflow vect) */
1135 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1137 #ifdef CONFIG_NAND_SPL
1138 bl nand_boot_common /* will not return */
1140 GET_GOT /* initialize GOT access */
1142 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1144 /* NEVER RETURNS! */
1145 bl board_init_f /* run first part of init code (from Flash) */
1146 #endif /* CONFIG_NAND_SPL */
1148 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1149 /*----------------------------------------------------------------------- */
1152 #ifndef CONFIG_NAND_SPL
1154 * This code finishes saving the registers to the exception frame
1155 * and jumps to the appropriate handler for the exception.
1156 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1158 .globl transfer_to_handler
1159 transfer_to_handler:
1169 andi. r24,r23,0x3f00 /* get vector offset */
1173 mtspr SPRG2,r22 /* r1 is now kernel sp */
1174 lwz r24,0(r23) /* virtual address of handler */
1175 lwz r23,4(r23) /* where to go when done */
1180 rfi /* jump to handler, enable MMU */
1183 mfmsr r28 /* Disable interrupts */
1187 SYNC /* Some chip revs need this... */
1202 lwz r2,_NIP(r1) /* Restore environment */
1213 mfmsr r28 /* Disable interrupts */
1217 SYNC /* Some chip revs need this... */
1232 lwz r2,_NIP(r1) /* Restore environment */
1244 mfmsr r28 /* Disable interrupts */
1248 SYNC /* Some chip revs need this... */
1263 lwz r2,_NIP(r1) /* Restore environment */
1272 #endif /* CONFIG_440 */
1280 /*------------------------------------------------------------------------------- */
1281 /* Function: out16 */
1282 /* Description: Output 16 bits */
1283 /*------------------------------------------------------------------------------- */
1289 /*------------------------------------------------------------------------------- */
1290 /* Function: out16r */
1291 /* Description: Byte reverse and output 16 bits */
1292 /*------------------------------------------------------------------------------- */
1298 /*------------------------------------------------------------------------------- */
1299 /* Function: out32r */
1300 /* Description: Byte reverse and output 32 bits */
1301 /*------------------------------------------------------------------------------- */
1307 /*------------------------------------------------------------------------------- */
1308 /* Function: in16 */
1309 /* Description: Input 16 bits */
1310 /*------------------------------------------------------------------------------- */
1316 /*------------------------------------------------------------------------------- */
1317 /* Function: in16r */
1318 /* Description: Input 16 bits and byte reverse */
1319 /*------------------------------------------------------------------------------- */
1325 /*------------------------------------------------------------------------------- */
1326 /* Function: in32r */
1327 /* Description: Input 32 bits and byte reverse */
1328 /*------------------------------------------------------------------------------- */
1335 * void relocate_code (addr_sp, gd, addr_moni)
1337 * This "function" does not return, instead it continues in RAM
1338 * after relocating the monitor code.
1340 * r3 = Relocated stack pointer
1341 * r4 = Relocated global data pointer
1342 * r5 = Relocated text pointer
1344 .globl relocate_code
1346 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1348 * We need to flush the initial global data (gd_t) before the dcache
1349 * will be invalidated.
1352 /* Save registers */
1357 /* Flush initial global data range */
1359 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1360 bl flush_dcache_range
1362 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1364 * Undo the earlier data cache set-up for the primordial stack and
1365 * data area. First, invalidate the data cache and then disable data
1366 * cacheability for that area. Finally, restore the EBC values, if
1370 /* Invalidate the primordial stack and data area in cache */
1371 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1372 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1374 lis r4, CONFIG_SYS_INIT_RAM_END@h
1375 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1378 bl invalidate_dcache_range
1380 /* Disable cacheability for the region */
1382 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1383 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1387 /* Restore the EBC parameters */
1391 ori r3, r3, PBxAP_VAL@l
1397 ori r3, r3, PBxCR_VAL@l
1399 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1401 /* Restore registers */
1405 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1407 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1409 * Unlock the previously locked d-cache
1413 /* set TFLOOR/NFLOOR to 0 again */
1429 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1431 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1432 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1433 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1434 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1435 defined(CONFIG_460SX)
1437 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1438 * to speed up the boot process. Now this cache needs to be disabled.
1440 iccci 0,0 /* Invalidate inst cache */
1441 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1445 /* Clear all potential pending exceptions */
1448 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
1449 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1451 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1452 #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
1453 tlbre r0,r1,0x0002 /* Read contents */
1454 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1455 tlbwe r0,r1,0x0002 /* Save it out */
1458 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1459 mr r1, r3 /* Set new stack pointer */
1460 mr r9, r4 /* Save copy of Init Data pointer */
1461 mr r10, r5 /* Save copy of Destination Address */
1463 mr r3, r5 /* Destination Address */
1464 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1465 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1466 lwz r5, GOT(__init_end)
1468 li r6, L1_CACHE_BYTES /* Cache Line Size */
1473 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1479 /* First our own GOT */
1481 /* then the one used by the C code */
1491 beq cr1,4f /* In place copy is not necessary */
1492 beq 7f /* Protect against 0 count */
1511 * Now flush the cache: note that we must start from a cache aligned
1512 * address. Otherwise we might miss one cache line.
1516 beq 7f /* Always flush prefetch queue in any case */
1524 sync /* Wait for all dcbst to complete on bus */
1530 7: sync /* Wait for all icbi to complete on bus */
1534 * We are done. Do not return, instead branch to second part of board
1535 * initialization, now running from RAM.
1538 addi r0, r10, in_ram - _start + _START_OFFSET
1540 blr /* NEVER RETURNS! */
1545 * Relocation Function, r14 point to got2+0x8000
1547 * Adjust got2 pointers, no need to check for 0, this code
1548 * already puts a few entries in the table.
1550 li r0,__got2_entries@sectoff@l
1551 la r3,GOT(_GOT2_TABLE_)
1552 lwz r11,GOT(_GOT2_TABLE_)
1562 * Now adjust the fixups and the pointers to the fixups
1563 * in case we need to move ourselves again.
1565 2: li r0,__fixup_entries@sectoff@l
1566 lwz r3,GOT(_FIXUP_TABLE_)
1580 * Now clear BSS segment
1582 lwz r3,GOT(__bss_start)
1605 mr r3, r9 /* Init Data pointer */
1606 mr r4, r10 /* Destination Address */
1610 * Copy exception vector code to low memory
1613 * r7: source address, r8: end address, r9: target address
1617 lwz r7, GOT(_start_of_vectors)
1618 lwz r8, GOT(_end_of_vectors)
1620 li r9, 0x100 /* reset vector always at 0x100 */
1623 bgelr /* return if r7>=r8 - just in case */
1625 mflr r4 /* save link register */
1635 * relocate `hdlr' and `int_return' entries
1637 li r7, .L_MachineCheck - _start + _START_OFFSET
1638 li r8, Alignment - _start + _START_OFFSET
1641 addi r7, r7, 0x100 /* next exception vector */
1645 li r7, .L_Alignment - _start + _START_OFFSET
1648 li r7, .L_ProgramCheck - _start + _START_OFFSET
1652 li r7, .L_FPUnavailable - _start + _START_OFFSET
1655 li r7, .L_Decrementer - _start + _START_OFFSET
1658 li r7, .L_APU - _start + _START_OFFSET
1661 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1664 li r7, .L_DataTLBError - _start + _START_OFFSET
1666 #else /* CONFIG_440 */
1667 li r7, .L_PIT - _start + _START_OFFSET
1670 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1673 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1675 #endif /* CONFIG_440 */
1677 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1680 #if !defined(CONFIG_440)
1681 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1682 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1683 mtmsr r7 /* change MSR */
1686 b __440_msr_continue
1689 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1690 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1698 mtlr r4 /* restore link register */
1702 * Function: relocate entries for one exception vector
1705 lwz r0, 0(r7) /* hdlr ... */
1706 add r0, r0, r3 /* ... += dest_addr */
1709 lwz r0, 4(r7) /* int_return ... */
1710 add r0, r0, r3 /* ... += dest_addr */
1715 #if defined(CONFIG_440)
1716 /*----------------------------------------------------------------------------+
1718 +----------------------------------------------------------------------------*/
1719 function_prolog(dcbz_area)
1720 rlwinm. r5,r4,0,27,31
1721 rlwinm r5,r4,27,5,31
1730 function_epilog(dcbz_area)
1731 #endif /* CONFIG_440 */
1732 #endif /* CONFIG_NAND_SPL */
1734 /*------------------------------------------------------------------------------- */
1736 /* Description: Input 8 bits */
1737 /*------------------------------------------------------------------------------- */
1743 /*------------------------------------------------------------------------------- */
1744 /* Function: out8 */
1745 /* Description: Output 8 bits */
1746 /*------------------------------------------------------------------------------- */
1752 /*------------------------------------------------------------------------------- */
1753 /* Function: out32 */
1754 /* Description: Output 32 bits */
1755 /*------------------------------------------------------------------------------- */
1761 /*------------------------------------------------------------------------------- */
1762 /* Function: in32 */
1763 /* Description: Input 32 bits */
1764 /*------------------------------------------------------------------------------- */
1770 /**************************************************************************/
1771 /* PPC405EP specific stuff */
1772 /**************************************************************************/
1776 #ifdef CONFIG_BUBINGA
1778 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1779 * function) to support FPGA and NVRAM accesses below.
1782 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1783 ori r3,r3,GPIO0_OSRH@l
1784 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1785 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1788 ori r3,r3,GPIO0_OSRL@l
1789 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1790 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1793 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1794 ori r3,r3,GPIO0_ISR1H@l
1795 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1796 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1798 lis r3,GPIO0_ISR1L@h
1799 ori r3,r3,GPIO0_ISR1L@l
1800 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1801 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1804 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1805 ori r3,r3,GPIO0_TSRH@l
1806 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1807 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1810 ori r3,r3,GPIO0_TSRL@l
1811 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1812 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1815 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1816 ori r3,r3,GPIO0_TCR@l
1817 lis r4,CONFIG_SYS_GPIO0_TCR@h
1818 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1821 li r3,pb1ap /* program EBC bank 1 for RTC access */
1823 lis r3,CONFIG_SYS_EBC_PB1AP@h
1824 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1828 lis r3,CONFIG_SYS_EBC_PB1CR@h
1829 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1832 li r3,pb1ap /* program EBC bank 1 for RTC access */
1834 lis r3,CONFIG_SYS_EBC_PB1AP@h
1835 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1839 lis r3,CONFIG_SYS_EBC_PB1CR@h
1840 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1843 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1845 lis r3,CONFIG_SYS_EBC_PB4AP@h
1846 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1850 lis r3,CONFIG_SYS_EBC_PB4CR@h
1851 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1856 !-----------------------------------------------------------------------
1857 ! Check to see if chip is in bypass mode.
1858 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1859 ! CPU reset Otherwise, skip this step and keep going.
1860 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1861 ! will not be fast enough for the SDRAM (min 66MHz)
1862 !-----------------------------------------------------------------------
1864 mfdcr r5, CPC0_PLLMR1
1865 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1868 beq pll_done /* if SSCS =b'1' then PLL has */
1869 /* already been set */
1870 /* and CPU has been reset */
1871 /* so skip to next section */
1873 #ifdef CONFIG_BUBINGA
1875 !-----------------------------------------------------------------------
1876 ! Read NVRAM to get value to write in PLLMR.
1877 ! If value has not been correctly saved, write default value
1878 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1879 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1881 ! WARNING: This code assumes the first three words in the nvram_t
1882 ! structure in openbios.h. Changing the beginning of
1883 ! the structure will break this code.
1885 !-----------------------------------------------------------------------
1887 addis r3,0,NVRAM_BASE@h
1888 addi r3,r3,NVRAM_BASE@l
1891 addis r5,0,NVRVFY1@h
1892 addi r5,r5,NVRVFY1@l
1893 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1897 addis r5,0,NVRVFY2@h
1898 addi r5,r5,NVRVFY2@l
1899 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1901 addi r3,r3,8 /* Skip over conf_size */
1902 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1903 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1904 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1905 cmpi cr0,0,r5,1 /* See if PLL is locked */
1908 #endif /* CONFIG_BUBINGA */
1912 andi. r5, r4, CPC0_BOOT_SEP@l
1913 bne strap_1 /* serial eeprom present */
1914 addis r5,0,CPLD_REG0_ADDR@h
1915 ori r5,r5,CPLD_REG0_ADDR@l
1918 #endif /* CONFIG_TAIHU */
1920 #if defined(CONFIG_ZEUS)
1922 andi. r5, r4, CPC0_BOOT_SEP@l
1923 bne strap_1 /* serial eeprom present */
1930 mfdcr r3, CPC0_PLLMR0
1931 mfdcr r4, CPC0_PLLMR1
1935 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1936 ori r3,r3,PLLMR0_DEFAULT@l /* */
1937 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1938 ori r4,r4,PLLMR1_DEFAULT@l /* */
1943 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1944 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1945 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1946 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1949 mfdcr r3, CPC0_PLLMR0
1950 mfdcr r4, CPC0_PLLMR1
1951 #endif /* CONFIG_TAIHU */
1954 b pll_write /* Write the CPC0_PLLMR with new value */
1958 !-----------------------------------------------------------------------
1959 ! Clear Soft Reset Register
1960 ! This is needed to enable PCI if not booting from serial EPROM
1961 !-----------------------------------------------------------------------
1971 blr /* return to main code */
1974 !-----------------------------------------------------------------------------
1975 ! Function: pll_write
1976 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1978 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1980 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1981 ! 4. PLL Reset is cleared
1982 ! 5. Wait 100us for PLL to lock
1983 ! 6. A core reset is performed
1984 ! Input: r3 = Value to write to CPC0_PLLMR0
1985 ! Input: r4 = Value to write to CPC0_PLLMR1
1987 !-----------------------------------------------------------------------------
1992 ori r5,r5,0x0101 /* Stop the UART clocks */
1993 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1995 mfdcr r5, CPC0_PLLMR1
1996 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1997 mtdcr CPC0_PLLMR1,r5
1998 oris r5,r5,0x4000 /* Set PLL Reset */
1999 mtdcr CPC0_PLLMR1,r5
2001 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2002 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2003 oris r5,r5,0x4000 /* Set PLL Reset */
2004 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2005 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2006 mtdcr CPC0_PLLMR1,r5
2009 ! Wait min of 100us for PLL to lock.
2010 ! See CMOS 27E databook for more info.
2011 ! At 200MHz, that means waiting 20,000 instructions
2013 addi r3,0,20000 /* 2000 = 0x4e20 */
2018 oris r5,r5,0x8000 /* Enable PLL */
2019 mtdcr CPC0_PLLMR1,r5 /* Engage */
2022 * Reset CPU to guarantee timings are OK
2023 * Not sure if this is needed...
2026 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2027 /* execution will continue from the poweron */
2028 /* vector of 0xfffffffc */
2029 #endif /* CONFIG_405EP */
2031 #if defined(CONFIG_440)
2032 /*----------------------------------------------------------------------------+
2034 +----------------------------------------------------------------------------*/
2035 function_prolog(mttlb3)
2038 function_epilog(mttlb3)
2040 /*----------------------------------------------------------------------------+
2042 +----------------------------------------------------------------------------*/
2043 function_prolog(mftlb3)
2046 function_epilog(mftlb3)
2048 /*----------------------------------------------------------------------------+
2050 +----------------------------------------------------------------------------*/
2051 function_prolog(mttlb2)
2054 function_epilog(mttlb2)
2056 /*----------------------------------------------------------------------------+
2058 +----------------------------------------------------------------------------*/
2059 function_prolog(mftlb2)
2062 function_epilog(mftlb2)
2064 /*----------------------------------------------------------------------------+
2066 +----------------------------------------------------------------------------*/
2067 function_prolog(mttlb1)
2070 function_epilog(mttlb1)
2072 /*----------------------------------------------------------------------------+
2074 +----------------------------------------------------------------------------*/
2075 function_prolog(mftlb1)
2078 function_epilog(mftlb1)
2079 #endif /* CONFIG_440 */
2081 #if defined(CONFIG_NAND_SPL)
2083 * void nand_boot_relocate(dst, src, bytes)
2085 * r3 = Destination address to copy code to (in SDRAM)
2086 * r4 = Source address to copy code from
2087 * r5 = size to copy in bytes
2095 * Copy SPL from icache into SDRAM
2107 * Calculate "corrected" link register, so that we "continue"
2108 * in execution in destination range
2110 sub r3,r7,r6 /* r3 = src - dst */
2111 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2117 * First initialize SDRAM. It has to be available *before* calling
2120 lis r3,CONFIG_SYS_SDRAM_BASE@h
2121 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2125 * Now copy the 4k SPL code into SDRAM and continue execution
2128 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2129 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2130 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2131 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2132 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2133 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2134 bl nand_boot_relocate
2137 * We're running from SDRAM now!!!
2139 * It is necessary for 4xx systems to relocate from running at
2140 * the original location (0xfffffxxx) to somewhere else (SDRAM
2141 * preferably). This is because CS0 needs to be reconfigured for
2142 * NAND access. And we can't reconfigure this CS when currently
2143 * "running" from it.
2147 * Finally call nand_boot() to load main NAND U-Boot image from
2148 * NAND and jump to it.
2150 bl nand_boot /* will not return */
2151 #endif /* CONFIG_NAND_SPL */