2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*------------------------------------------------------------------------------+
27 * This source code has been made available to you by IBM on an AS-IS
28 * basis. Anyone receiving this source is licensed under IBM
29 * copyrights to use it in any way he or she deems fit, including
30 * copying it, modifying it, compiling it, and redistributing it either
31 * with or without modifications. No license under IBM patents or
32 * patent applications is to be implied by the copyright license.
34 * Any user of this software should understand that IBM cannot provide
35 * technical support for this software and will not be responsible for
36 * any consequences resulting from the use of this software.
38 * Any person who transfers this source code or any derivative work
39 * must include the IBM copyright notice, this paragraph, and the
40 * preceding two paragraphs in the transferred software.
42 * COPYRIGHT I B M CORPORATION 1995
43 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
44 *-------------------------------------------------------------------------------
47 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
50 * The processor starts at 0xfffffffc and the code is executed
52 * in memory, but as long we don't jump around before relocating.
53 * board_init lies at a quite high address and when the cpu has
54 * jumped there, everything is ok.
55 * This works because the cpu gives the FLASH (CS0) the whole
56 * address space at startup, and board_init lies as a echo of
57 * the flash somewhere up there in the memorymap.
59 * board_init will change CS0 to be positioned at the correct
60 * address and (s)dram will be positioned at address 0
67 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
69 #include <ppc_asm.tmpl>
72 #include <asm/cache.h>
75 #ifndef CONFIG_IDENT_STRING
76 #define CONFIG_IDENT_STRING ""
79 #ifdef CFG_INIT_DCACHE_CS
80 # if (CFG_INIT_DCACHE_CS == 0)
84 # if (CFG_INIT_DCACHE_CS == 1)
88 # if (CFG_INIT_DCACHE_CS == 2)
92 # if (CFG_INIT_DCACHE_CS == 3)
96 # if (CFG_INIT_DCACHE_CS == 4)
100 # if (CFG_INIT_DCACHE_CS == 5)
104 # if (CFG_INIT_DCACHE_CS == 6)
108 # if (CFG_INIT_DCACHE_CS == 7)
112 #endif /* CFG_INIT_DCACHE_CS */
114 #define function_prolog(func_name) .text; \
118 #define function_epilog(func_name) .type func_name,@function; \
119 .size func_name,.-func_name
121 /* We don't want the MMU yet.
124 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
127 .extern ext_bus_cntlr_init
129 #ifdef CONFIG_NAND_U_BOOT
130 .extern reconfig_tlb0
134 * Set up GOT: Global Offset Table
136 * Use r14 to access the GOT
138 #if !defined(CONFIG_NAND_SPL)
140 GOT_ENTRY(_GOT2_TABLE_)
141 GOT_ENTRY(_FIXUP_TABLE_)
144 GOT_ENTRY(_start_of_vectors)
145 GOT_ENTRY(_end_of_vectors)
146 GOT_ENTRY(transfer_to_handler)
148 GOT_ENTRY(__init_end)
150 GOT_ENTRY(__bss_start)
152 #endif /* CONFIG_NAND_SPL */
154 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
156 * NAND U-Boot image is started from offset 0
159 #if defined(CONFIG_440)
163 bl cpu_init_f /* run low-level CPU init code (from Flash) */
168 * 440 Startup -- on reset only the top 4k of the effective
169 * address space is mapped in by an entry in the instruction
170 * and data shadow TLB. The .bootpg section is located in the
171 * top 4k & does only what's necessary to map in the the rest
172 * of the boot rom. Once the boot rom is mapped in we can
173 * proceed with normal startup.
175 * NOTE: CS0 only covers the top 2MB of the effective address
179 #if defined(CONFIG_440)
180 #if !defined(CONFIG_NAND_SPL)
181 .section .bootpg,"ax"
185 /**************************************************************************/
187 /*--------------------------------------------------------------------+
188 | 440EPX BUP Change - Hardware team request
189 +--------------------------------------------------------------------*/
190 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
195 /*----------------------------------------------------------------+
196 | Core bug fix. Clear the esr
197 +-----------------------------------------------------------------*/
200 /*----------------------------------------------------------------*/
201 /* Clear and set up some registers. */
202 /*----------------------------------------------------------------*/
203 iccci r0,r0 /* NOTE: operands not used for 440 */
204 dccci r0,r0 /* NOTE: operands not used for 440 */
211 /* NOTE: 440GX adds machine check status regs */
212 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
219 /*----------------------------------------------------------------*/
221 /*----------------------------------------------------------------*/
222 /* Disable store gathering & broadcast, guarantee inst/data
223 * cache block touch, force load/store alignment
224 * (see errata 1.12: 440_33)
226 lis r1,0x0030 /* store gathering & broadcast disable */
227 ori r1,r1,0x6000 /* cache touch */
230 /*----------------------------------------------------------------*/
231 /* Initialize debug */
232 /*----------------------------------------------------------------*/
234 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
235 bne skip_debug_init /* if set, don't clear debug register */
248 mtspr dbsr,r1 /* Clear all valid bits */
251 #if defined (CONFIG_440SPE)
252 /*----------------------------------------------------------------+
253 | Initialize Core Configuration Reg1.
254 | a. ICDPEI: Record even parity. Normal operation.
255 | b. ICTPEI: Record even parity. Normal operation.
256 | c. DCTPEI: Record even parity. Normal operation.
257 | d. DCDPEI: Record even parity. Normal operation.
258 | e. DCUPEI: Record even parity. Normal operation.
259 | f. DCMPEI: Record even parity. Normal operation.
260 | g. FCOM: Normal operation
261 | h. MMUPEI: Record even parity. Normal operation.
262 | i. FFF: Flush only as much data as necessary.
263 | j. TCS: Timebase increments from CPU clock.
264 +-----------------------------------------------------------------*/
268 /*----------------------------------------------------------------+
269 | Reset the timebase.
270 | The previous write to CCR1 sets the timebase source.
271 +-----------------------------------------------------------------*/
276 /*----------------------------------------------------------------*/
277 /* Setup interrupt vectors */
278 /*----------------------------------------------------------------*/
279 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
281 mtspr ivor0,r1 /* Critical input */
283 mtspr ivor1,r1 /* Machine check */
285 mtspr ivor2,r1 /* Data storage */
287 mtspr ivor3,r1 /* Instruction storage */
289 mtspr ivor4,r1 /* External interrupt */
291 mtspr ivor5,r1 /* Alignment */
293 mtspr ivor6,r1 /* Program check */
295 mtspr ivor7,r1 /* Floating point unavailable */
297 mtspr ivor8,r1 /* System call */
299 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
301 mtspr ivor10,r1 /* Decrementer */
303 mtspr ivor13,r1 /* Data TLB error */
305 mtspr ivor14,r1 /* Instr TLB error */
307 mtspr ivor15,r1 /* Debug */
309 /*----------------------------------------------------------------*/
310 /* Configure cache regions */
311 /*----------------------------------------------------------------*/
329 /*----------------------------------------------------------------*/
330 /* Cache victim limits */
331 /*----------------------------------------------------------------*/
332 /* floors 0, ceiling max to use the entire cache -- nothing locked
339 /*----------------------------------------------------------------+
340 |Initialize MMUCR[STID] = 0.
341 +-----------------------------------------------------------------*/
348 /*----------------------------------------------------------------*/
349 /* Clear all TLB entries -- TID = 0, TS = 0 */
350 /*----------------------------------------------------------------*/
352 li r1,0x003f /* 64 TLB entries */
354 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
360 /*----------------------------------------------------------------*/
361 /* TLB entry setup -- step thru tlbtab */
362 /*----------------------------------------------------------------*/
363 #if defined(CONFIG_440SPE)
364 /*----------------------------------------------------------------*/
365 /* We have different TLB tables for revA and rev B of 440SPe */
366 /*----------------------------------------------------------------*/
378 bl tlbtab /* Get tlbtab pointer */
381 li r1,0x003f /* 64 TLB entries max */
388 beq 2f /* 0 marks end */
391 tlbwe r0,r4,0 /* TLB Word 0 */
392 tlbwe r1,r4,1 /* TLB Word 1 */
393 tlbwe r2,r4,2 /* TLB Word 2 */
394 addi r4,r4,1 /* Next TLB */
397 /*----------------------------------------------------------------*/
398 /* Continue from 'normal' start */
399 /*----------------------------------------------------------------*/
402 #if defined(CONFIG_NAND_SPL)
403 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
405 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
410 and r1,r1,r2 /* Disable parity check */
413 and r1,r1,r2 /* Disable pwr mgmt */
416 #if defined(CONFIG_440EP)
418 * On 440EP with no internal SRAM, we setup SDRAM very early
419 * and copy the NAND_SPL to SDRAM and jump to it
421 /* Clear Dcache to use as RAM */
422 addis r3,r0,CFG_INIT_RAM_ADDR@h
423 ori r3,r3,CFG_INIT_RAM_ADDR@l
424 addis r4,r0,CFG_INIT_RAM_END@h
425 ori r4,r4,CFG_INIT_RAM_END@l
426 rlwinm. r5,r4,0,27,31
436 /*----------------------------------------------------------------*/
437 /* Setup the stack in internal SRAM */
438 /*----------------------------------------------------------------*/
439 lis r1,CFG_INIT_RAM_ADDR@h
440 ori r1,r1,CFG_INIT_SP_OFFSET@l
443 stwu r0,-4(r1) /* Terminate call chain */
445 stwu r1,-8(r1) /* Save back chain and move SP */
446 lis r0,RESET_VECTOR@h /* Address of reset vector */
447 ori r0,r0, RESET_VECTOR@l
448 stwu r1,-8(r1) /* Save back chain and move SP */
449 stw r0,+12(r1) /* Save return addr (underflow vect) */
453 #endif /* CONFIG_440EP */
456 * Copy SPL from cache into internal SRAM
458 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
460 lis r2,CFG_NAND_BOOT_SPL_SRC@h
461 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
462 lis r3,CFG_NAND_BOOT_SPL_DST@h
463 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
470 * Jump to code in RAM
474 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
475 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
484 #endif /* CONFIG_NAND_SPL */
490 mtspr srr1,r0 /* Keep things disabled for now */
494 #endif /* CONFIG_440 */
497 * r3 - 1st arg to board_init(): IMMP pointer
498 * r4 - 2nd arg to board_init(): boot flag
500 #ifndef CONFIG_NAND_SPL
502 .long 0x27051956 /* U-Boot Magic Number */
503 .globl version_string
505 .ascii U_BOOT_VERSION
506 .ascii " (", __DATE__, " - ", __TIME__, ")"
507 .ascii CONFIG_IDENT_STRING, "\0"
509 . = EXC_OFF_SYS_RESET
510 .globl _start_of_vectors
513 /* Critical input. */
514 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
518 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
520 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
521 #endif /* CONFIG_440 */
523 /* Data Storage exception. */
524 STD_EXCEPTION(0x300, DataStorage, UnknownException)
526 /* Instruction Storage exception. */
527 STD_EXCEPTION(0x400, InstStorage, UnknownException)
529 /* External Interrupt exception. */
530 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
532 /* Alignment exception. */
535 EXCEPTION_PROLOG(SRR0, SRR1)
540 addi r3,r1,STACK_FRAME_OVERHEAD
542 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
543 lwz r6,GOT(transfer_to_handler)
547 .long AlignmentException - _start + _START_OFFSET
548 .long int_return - _start + _START_OFFSET
550 /* Program check exception */
553 EXCEPTION_PROLOG(SRR0, SRR1)
554 addi r3,r1,STACK_FRAME_OVERHEAD
556 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
557 lwz r6,GOT(transfer_to_handler)
561 .long ProgramCheckException - _start + _START_OFFSET
562 .long int_return - _start + _START_OFFSET
565 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
566 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
567 STD_EXCEPTION(0xa00, APU, UnknownException)
569 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
572 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
573 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
575 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
576 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
577 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
579 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
581 .globl _end_of_vectors
588 /*****************************************************************************/
589 #if defined(CONFIG_440)
591 /*----------------------------------------------------------------*/
592 /* Clear and set up some registers. */
593 /*----------------------------------------------------------------*/
596 mtspr dec,r0 /* prevent dec exceptions */
597 mtspr tbl,r0 /* prevent fit & wdt exceptions */
599 mtspr tsr,r1 /* clear all timer exception status */
600 mtspr tcr,r0 /* disable all */
601 mtspr esr,r0 /* clear exception syndrome register */
602 mtxer r0 /* clear integer exception register */
604 /*----------------------------------------------------------------*/
605 /* Debug setup -- some (not very good) ice's need an event*/
606 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
607 /* value you need in this case 0x8cff 0000 should do the trick */
608 /*----------------------------------------------------------------*/
609 #if defined(CFG_INIT_DBCR)
612 mtspr dbsr,r1 /* Clear all status bits */
613 lis r0,CFG_INIT_DBCR@h
614 ori r0,r0,CFG_INIT_DBCR@l
619 /*----------------------------------------------------------------*/
620 /* Setup the internal SRAM */
621 /*----------------------------------------------------------------*/
624 #ifdef CFG_INIT_RAM_DCACHE
625 /* Clear Dcache to use as RAM */
626 addis r3,r0,CFG_INIT_RAM_ADDR@h
627 ori r3,r3,CFG_INIT_RAM_ADDR@l
628 addis r4,r0,CFG_INIT_RAM_END@h
629 ori r4,r4,CFG_INIT_RAM_END@l
630 rlwinm. r5,r4,0,27,31
640 #endif /* CFG_INIT_RAM_DCACHE */
642 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
643 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
644 /* not all PPC's have internal SRAM usable as L2-cache */
645 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
646 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
652 and r1,r1,r2 /* Disable parity check */
655 and r1,r1,r2 /* Disable pwr mgmt */
658 lis r1,0x8000 /* BAS = 8000_0000 */
659 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
660 ori r1,r1,0x0980 /* first 64k */
661 mtdcr isram0_sb0cr,r1
663 ori r1,r1,0x0980 /* second 64k */
664 mtdcr isram0_sb1cr,r1
666 ori r1,r1, 0x0980 /* third 64k */
667 mtdcr isram0_sb2cr,r1
669 ori r1,r1, 0x0980 /* fourth 64k */
670 mtdcr isram0_sb3cr,r1
671 #elif defined(CONFIG_440SPE)
672 lis r1,0x0000 /* BAS = 0000_0000 */
673 ori r1,r1,0x0984 /* first 64k */
674 mtdcr isram0_sb0cr,r1
676 ori r1,r1,0x0984 /* second 64k */
677 mtdcr isram0_sb1cr,r1
679 ori r1,r1, 0x0984 /* third 64k */
680 mtdcr isram0_sb2cr,r1
682 ori r1,r1, 0x0984 /* fourth 64k */
683 mtdcr isram0_sb3cr,r1
684 #elif defined(CONFIG_440GP)
685 ori r1,r1,0x0380 /* 8k rw */
686 mtdcr isram0_sb0cr,r1
687 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
689 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
691 /*----------------------------------------------------------------*/
692 /* Setup the stack in internal SRAM */
693 /*----------------------------------------------------------------*/
694 lis r1,CFG_INIT_RAM_ADDR@h
695 ori r1,r1,CFG_INIT_SP_OFFSET@l
698 stwu r0,-4(r1) /* Terminate call chain */
700 stwu r1,-8(r1) /* Save back chain and move SP */
701 lis r0,RESET_VECTOR@h /* Address of reset vector */
702 ori r0,r0, RESET_VECTOR@l
703 stwu r1,-8(r1) /* Save back chain and move SP */
704 stw r0,+12(r1) /* Save return addr (underflow vect) */
706 #ifdef CONFIG_NAND_SPL
707 bl nand_boot /* will not return */
711 bl cpu_init_f /* run low-level CPU init code (from Flash) */
715 #endif /* CONFIG_440 */
717 /*****************************************************************************/
719 /*----------------------------------------------------------------------- */
720 /* Set up some machine state registers. */
721 /*----------------------------------------------------------------------- */
722 addi r0,r0,0x0000 /* initialize r0 to zero */
723 mtspr esr,r0 /* clear Exception Syndrome Reg */
724 mttcr r0 /* timer control register */
725 mtexier r0 /* disable all interrupts */
726 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
727 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
728 mtdbsr r4 /* clear/reset the dbsr */
729 mtexisr r4 /* clear all pending interrupts */
731 mtexier r4 /* enable critical exceptions */
732 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
733 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
734 mtiocr r4 /* since bit not used) & DRC to latch */
735 /* data bus on rising edge of CAS */
736 /*----------------------------------------------------------------------- */
738 /*----------------------------------------------------------------------- */
740 /*----------------------------------------------------------------------- */
741 /* Invalidate i-cache and d-cache TAG arrays. */
742 /*----------------------------------------------------------------------- */
743 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
744 addi r4,0,1024 /* 1/4 of I-cache */
749 addic. r3,r3,-16 /* move back one cache line */
750 bne ..cloop /* loop back to do rest until r3 = 0 */
753 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
754 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
757 /* first copy IOP480 register base address into r3 */
758 addis r3,0,0x5000 /* IOP480 register base address hi */
759 /* ori r3,r3,0x0000 / IOP480 register base address lo */
762 /* use r4 as the working variable */
763 /* turn on CS3 (LOCCTL.7) */
764 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
765 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
766 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
769 #ifdef CONFIG_DASA_SIM
770 /* use r4 as the working variable */
771 /* turn on MA17 (LOCCTL.7) */
772 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
773 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
774 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
777 /* turn on MA16..13 (LCS0BRD.12 = 0) */
778 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
779 andi. r4,r4,0xefff /* make bit 12 = 0 */
780 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
782 /* make sure above stores all comlete before going on */
785 /* last thing, set local init status done bit (DEVINIT.31) */
786 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
787 oris r4,r4,0x8000 /* make bit 31 = 1 */
788 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
790 /* clear all pending interrupts and disable all interrupts */
791 li r4,-1 /* set p1 to 0xffffffff */
792 stw r4,0x1b0(r3) /* clear all pending interrupts */
793 stw r4,0x1b8(r3) /* clear all pending interrupts */
794 li r4,0 /* set r4 to 0 */
795 stw r4,0x1b4(r3) /* disable all interrupts */
796 stw r4,0x1bc(r3) /* disable all interrupts */
798 /* make sure above stores all comlete before going on */
801 /*----------------------------------------------------------------------- */
802 /* Enable two 128MB cachable regions. */
803 /*----------------------------------------------------------------------- */
806 mticcr r1 /* instruction cache */
810 mtdccr r1 /* data cache */
812 addis r1,r0,CFG_INIT_RAM_ADDR@h
813 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
814 li r0, 0 /* Make room for stack frame header and */
815 stwu r0, -4(r1) /* clear final stack frame so that */
816 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
818 GET_GOT /* initialize GOT access */
820 bl board_init_f /* run first part of init code (from Flash) */
822 #endif /* CONFIG_IOP480 */
824 /*****************************************************************************/
825 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
826 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
828 /*----------------------------------------------------------------------- */
829 /* Clear and set up some registers. */
830 /*----------------------------------------------------------------------- */
834 mtesr r4 /* clear Exception Syndrome Reg */
835 mttcr r4 /* clear Timer Control Reg */
836 mtxer r4 /* clear Fixed-Point Exception Reg */
837 mtevpr r4 /* clear Exception Vector Prefix Reg */
838 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
839 /* dbsr is cleared by setting bits to 1) */
840 mtdbsr r4 /* clear/reset the dbsr */
842 /*----------------------------------------------------------------------- */
843 /* Invalidate I and D caches. Enable I cache for defined memory regions */
844 /* to speed things up. Leave the D cache disabled for now. It will be */
845 /* enabled/left disabled later based on user selected menu options. */
846 /* Be aware that the I cache may be disabled later based on the menu */
847 /* options as well. See miscLib/main.c. */
848 /*----------------------------------------------------------------------- */
852 /*----------------------------------------------------------------------- */
853 /* Enable two 128MB cachable regions. */
854 /*----------------------------------------------------------------------- */
857 mticcr r4 /* instruction cache */
862 mtdccr r4 /* data cache */
864 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
865 /*----------------------------------------------------------------------- */
866 /* Tune the speed and size for flash CS0 */
867 /*----------------------------------------------------------------------- */
868 bl ext_bus_cntlr_init
871 #if defined(CONFIG_405EP)
872 /*----------------------------------------------------------------------- */
873 /* DMA Status, clear to come up clean */
874 /*----------------------------------------------------------------------- */
875 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
879 bl ppc405ep_init /* do ppc405ep specific init */
880 #endif /* CONFIG_405EP */
882 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
883 #if defined(CONFIG_405EZ)
884 /********************************************************************
885 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
886 *******************************************************************/
888 * We can map the OCM on the PLB3, so map it at
889 * CFG_OCM_DATA_ADDR + 0x8000
891 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
892 ori r3,r3,CFG_OCM_DATA_ADDR@l
893 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
894 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
895 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
896 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
899 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
900 ori r3,r3,CFG_OCM_DATA_ADDR@l
901 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
902 mtdcr ocmdscr1, r3 /* Set Data Side */
903 mtdcr ocmiscr1, r3 /* Set Instruction Side */
904 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
905 mtdcr ocmdscr2, r3 /* Set Data Side */
906 mtdcr ocmiscr2, r3 /* Set Instruction Side */
907 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
911 #else /* CONFIG_405EZ */
912 /********************************************************************
913 * Setup OCM - On Chip Memory
914 *******************************************************************/
918 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
919 mfdcr r4, ocmdscntl /* get data-side IRAM config */
920 and r3, r3, r0 /* disable data-side IRAM */
921 and r4, r4, r0 /* disable data-side IRAM */
922 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
923 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
926 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
927 ori r3,r3,CFG_OCM_DATA_ADDR@l
929 addis r4, 0, 0xC000 /* OCM data area enabled */
932 #endif /* CONFIG_405EZ */
935 #ifdef CONFIG_NAND_SPL
937 * Copy SPL from cache into internal SRAM
939 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
941 lis r2,CFG_NAND_BOOT_SPL_SRC@h
942 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
943 lis r3,CFG_NAND_BOOT_SPL_DST@h
944 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
951 * Jump to code in RAM
955 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
956 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
965 #endif /* CONFIG_NAND_SPL */
967 /*----------------------------------------------------------------------- */
968 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
969 /*----------------------------------------------------------------------- */
970 #ifdef CFG_INIT_DCACHE_CS
971 /*----------------------------------------------------------------------- */
972 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
973 /* used as temporary stack pointer for stage0 */
974 /*----------------------------------------------------------------------- */
987 /* turn on data chache for this region */
991 /* set stack pointer and clear stack to known value */
993 lis r1,CFG_INIT_RAM_ADDR@h
994 ori r1,r1,CFG_INIT_SP_OFFSET@l
996 li r4,2048 /* we store 2048 words to stack */
999 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
1000 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
1002 lis r4,0xdead /* we store 0xdeaddead in the stack */
1009 li r0, 0 /* Make room for stack frame header and */
1010 stwu r0, -4(r1) /* clear final stack frame so that */
1011 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1013 * Set up a dummy frame to store reset vector as return address.
1014 * this causes stack underflow to reset board.
1016 stwu r1, -8(r1) /* Save back chain and move SP */
1017 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1018 ori r0, r0, RESET_VECTOR@l
1019 stwu r1, -8(r1) /* Save back chain and move SP */
1020 stw r0, +12(r1) /* Save return addr (underflow vect) */
1022 #elif defined(CFG_TEMP_STACK_OCM) && \
1023 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1028 /* Set up Stack at top of OCM */
1029 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1030 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1032 /* Set up a zeroized stack frame so that backtrace works right */
1038 * Set up a dummy frame to store reset vector as return address.
1039 * this causes stack underflow to reset board.
1041 stwu r1, -8(r1) /* Save back chain and move SP */
1042 lis r0, RESET_VECTOR@h /* Address of reset vector */
1043 ori r0, r0, RESET_VECTOR@l
1044 stwu r1, -8(r1) /* Save back chain and move SP */
1045 stw r0, +12(r1) /* Save return addr (underflow vect) */
1046 #endif /* CFG_INIT_DCACHE_CS */
1048 /*----------------------------------------------------------------------- */
1049 /* Initialize SDRAM Controller */
1050 /*----------------------------------------------------------------------- */
1054 * Setup temporary stack pointer only for boards
1055 * that do not use SDRAM SPD I2C stuff since it
1056 * is already initialized to use DCACHE or OCM
1059 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
1060 lis r1, CFG_INIT_RAM_ADDR@h
1061 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
1063 li r0, 0 /* Make room for stack frame header and */
1064 stwu r0, -4(r1) /* clear final stack frame so that */
1065 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1067 * Set up a dummy frame to store reset vector as return address.
1068 * this causes stack underflow to reset board.
1070 stwu r1, -8(r1) /* Save back chain and move SP */
1071 lis r0, RESET_VECTOR@h /* Address of reset vector */
1072 ori r0, r0, RESET_VECTOR@l
1073 stwu r1, -8(r1) /* Save back chain and move SP */
1074 stw r0, +12(r1) /* Save return addr (underflow vect) */
1075 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
1077 #ifdef CONFIG_NAND_SPL
1078 bl nand_boot /* will not return */
1080 GET_GOT /* initialize GOT access */
1082 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1084 /* NEVER RETURNS! */
1085 bl board_init_f /* run first part of init code (from Flash) */
1086 #endif /* CONFIG_NAND_SPL */
1088 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1089 /*----------------------------------------------------------------------- */
1092 #ifndef CONFIG_NAND_SPL
1094 * This code finishes saving the registers to the exception frame
1095 * and jumps to the appropriate handler for the exception.
1096 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1098 .globl transfer_to_handler
1099 transfer_to_handler:
1109 andi. r24,r23,0x3f00 /* get vector offset */
1113 mtspr SPRG2,r22 /* r1 is now kernel sp */
1114 lwz r24,0(r23) /* virtual address of handler */
1115 lwz r23,4(r23) /* where to go when done */
1120 rfi /* jump to handler, enable MMU */
1123 mfmsr r28 /* Disable interrupts */
1127 SYNC /* Some chip revs need this... */
1142 lwz r2,_NIP(r1) /* Restore environment */
1153 mfmsr r28 /* Disable interrupts */
1157 SYNC /* Some chip revs need this... */
1172 lwz r2,_NIP(r1) /* Restore environment */
1184 mfmsr r28 /* Disable interrupts */
1188 SYNC /* Some chip revs need this... */
1203 lwz r2,_NIP(r1) /* Restore environment */
1212 #endif /* CONFIG_440 */
1218 * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
1219 * although for some cache-ralated calls stubs have to be provided to satisfy
1220 * symbols resolution.
1224 .globl dcache_disable
1228 .globl dcache_status
1233 addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
1235 mfmsr r12 /* save msr */
1237 mtmsr r9 /* disable EE and CE */
1238 addi r10,r0,0x0001 /* enable data cache for unused memory */
1239 mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
1240 or r10,r10,r9 /* bit 31 in dccr */
1243 /* do loop for # of congruence classes. */
1244 lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
1245 ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1246 lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1247 ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1249 addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1250 add r11,r10,r11 /* add to get to other side of cache line */
1251 ..flush_dcache_loop:
1252 lwz r3,0(r10) /* least recently used side */
1253 lwz r3,0(r11) /* the other side */
1254 dccci r0,r11 /* invalidate both sides */
1255 addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1256 addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1257 bdnz ..flush_dcache_loop
1258 sync /* allow memory access to complete */
1259 mtdccr r9 /* restore dccr */
1260 mtmsr r12 /* restore msr */
1263 .globl icache_enable
1266 bl invalidate_icache
1269 addis r3,r0, 0x8000 /* set bit 0 */
1273 .globl icache_disable
1275 addis r3,r0, 0x0000 /* clear bit 0 */
1280 .globl icache_status
1283 srwi r3, r3, 31 /* >>31 => select bit 0 */
1286 .globl dcache_enable
1289 bl invalidate_dcache
1292 addis r3,r0, 0x8000 /* set bit 0 */
1296 .globl dcache_disable
1301 addis r3,r0, 0x0000 /* clear bit 0 */
1305 .globl dcache_status
1308 srwi r3, r3, 31 /* >>31 => select bit 0 */
1317 /*------------------------------------------------------------------------------- */
1318 /* Function: out16 */
1319 /* Description: Output 16 bits */
1320 /*------------------------------------------------------------------------------- */
1326 /*------------------------------------------------------------------------------- */
1327 /* Function: out16r */
1328 /* Description: Byte reverse and output 16 bits */
1329 /*------------------------------------------------------------------------------- */
1335 /*------------------------------------------------------------------------------- */
1336 /* Function: out32r */
1337 /* Description: Byte reverse and output 32 bits */
1338 /*------------------------------------------------------------------------------- */
1344 /*------------------------------------------------------------------------------- */
1345 /* Function: in16 */
1346 /* Description: Input 16 bits */
1347 /*------------------------------------------------------------------------------- */
1353 /*------------------------------------------------------------------------------- */
1354 /* Function: in16r */
1355 /* Description: Input 16 bits and byte reverse */
1356 /*------------------------------------------------------------------------------- */
1362 /*------------------------------------------------------------------------------- */
1363 /* Function: in32r */
1364 /* Description: Input 32 bits and byte reverse */
1365 /*------------------------------------------------------------------------------- */
1371 /*------------------------------------------------------------------------------- */
1372 /* Function: ppcDcbf */
1373 /* Description: Data Cache block flush */
1374 /* Input: r3 = effective address */
1376 /*------------------------------------------------------------------------------- */
1382 /*------------------------------------------------------------------------------- */
1383 /* Function: ppcDcbi */
1384 /* Description: Data Cache block Invalidate */
1385 /* Input: r3 = effective address */
1387 /*------------------------------------------------------------------------------- */
1393 /*------------------------------------------------------------------------------- */
1394 /* Function: ppcSync */
1395 /* Description: Processor Synchronize */
1398 /*------------------------------------------------------------------------------- */
1405 * void relocate_code (addr_sp, gd, addr_moni)
1407 * This "function" does not return, instead it continues in RAM
1408 * after relocating the monitor code.
1412 * r5 = length in bytes
1413 * r6 = cachelinesize
1415 .globl relocate_code
1417 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1418 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1419 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1421 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1422 * to speed up the boot process. Now this cache needs to be disabled.
1424 iccci 0,0 /* Invalidate inst cache */
1425 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1428 addi r1,r0,0x0000 /* TLB entry #0 */
1429 tlbre r0,r1,0x0002 /* Read contents */
1430 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1431 tlbwe r0,r1,0x0002 /* Save it out */
1435 mr r1, r3 /* Set new stack pointer */
1436 mr r9, r4 /* Save copy of Init Data pointer */
1437 mr r10, r5 /* Save copy of Destination Address */
1439 mr r3, r5 /* Destination Address */
1440 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1441 ori r4, r4, CFG_MONITOR_BASE@l
1442 lwz r5, GOT(__init_end)
1444 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
1449 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1455 /* First our own GOT */
1457 /* the the one used by the C code */
1467 beq cr1,4f /* In place copy is not necessary */
1468 beq 7f /* Protect against 0 count */
1487 * Now flush the cache: note that we must start from a cache aligned
1488 * address. Otherwise we might miss one cache line.
1492 beq 7f /* Always flush prefetch queue in any case */
1500 sync /* Wait for all dcbst to complete on bus */
1506 7: sync /* Wait for all icbi to complete on bus */
1510 * We are done. Do not return, instead branch to second part of board
1511 * initialization, now running from RAM.
1514 addi r0, r10, in_ram - _start + _START_OFFSET
1516 blr /* NEVER RETURNS! */
1521 * Relocation Function, r14 point to got2+0x8000
1523 * Adjust got2 pointers, no need to check for 0, this code
1524 * already puts a few entries in the table.
1526 li r0,__got2_entries@sectoff@l
1527 la r3,GOT(_GOT2_TABLE_)
1528 lwz r11,GOT(_GOT2_TABLE_)
1538 * Now adjust the fixups and the pointers to the fixups
1539 * in case we need to move ourselves again.
1541 2: li r0,__fixup_entries@sectoff@l
1542 lwz r3,GOT(_FIXUP_TABLE_)
1556 * Now clear BSS segment
1558 lwz r3,GOT(__bss_start)
1572 mr r3, r9 /* Init Data pointer */
1573 mr r4, r10 /* Destination Address */
1577 * Copy exception vector code to low memory
1580 * r7: source address, r8: end address, r9: target address
1584 lwz r7, GOT(_start_of_vectors)
1585 lwz r8, GOT(_end_of_vectors)
1587 li r9, 0x100 /* reset vector always at 0x100 */
1590 bgelr /* return if r7>=r8 - just in case */
1592 mflr r4 /* save link register */
1602 * relocate `hdlr' and `int_return' entries
1604 li r7, .L_MachineCheck - _start + _START_OFFSET
1605 li r8, Alignment - _start + _START_OFFSET
1608 addi r7, r7, 0x100 /* next exception vector */
1612 li r7, .L_Alignment - _start + _START_OFFSET
1615 li r7, .L_ProgramCheck - _start + _START_OFFSET
1619 li r7, .L_FPUnavailable - _start + _START_OFFSET
1622 li r7, .L_Decrementer - _start + _START_OFFSET
1625 li r7, .L_APU - _start + _START_OFFSET
1628 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1631 li r7, .L_DataTLBError - _start + _START_OFFSET
1633 #else /* CONFIG_440 */
1634 li r7, .L_PIT - _start + _START_OFFSET
1637 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1640 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1642 #endif /* CONFIG_440 */
1644 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1647 #if !defined(CONFIG_440)
1648 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1649 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1650 mtmsr r7 /* change MSR */
1653 b __440_msr_continue
1656 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1657 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1665 mtlr r4 /* restore link register */
1669 * Function: relocate entries for one exception vector
1672 lwz r0, 0(r7) /* hdlr ... */
1673 add r0, r0, r3 /* ... += dest_addr */
1676 lwz r0, 4(r7) /* int_return ... */
1677 add r0, r0, r3 /* ... += dest_addr */
1682 #if defined(CONFIG_440)
1683 /*----------------------------------------------------------------------------+
1685 +----------------------------------------------------------------------------*/
1686 function_prolog(dcbz_area)
1687 rlwinm. r5,r4,0,27,31
1688 rlwinm r5,r4,27,5,31
1697 function_epilog(dcbz_area)
1699 /*----------------------------------------------------------------------------+
1700 | dflush. Assume 32K at vector address is cachable.
1701 +----------------------------------------------------------------------------*/
1702 function_prolog(dflush)
1704 rlwinm r8,r9,0,15,13
1705 rlwinm r8,r8,0,17,15
1724 function_epilog(dflush)
1725 #endif /* CONFIG_440 */
1726 #endif /* CONFIG_NAND_SPL */
1728 /*------------------------------------------------------------------------------- */
1730 /* Description: Input 8 bits */
1731 /*------------------------------------------------------------------------------- */
1737 /*------------------------------------------------------------------------------- */
1738 /* Function: out8 */
1739 /* Description: Output 8 bits */
1740 /*------------------------------------------------------------------------------- */
1746 /*------------------------------------------------------------------------------- */
1747 /* Function: out32 */
1748 /* Description: Output 32 bits */
1749 /*------------------------------------------------------------------------------- */
1755 /*------------------------------------------------------------------------------- */
1756 /* Function: in32 */
1757 /* Description: Input 32 bits */
1758 /*------------------------------------------------------------------------------- */
1765 iccci r0,r0 /* for 405, iccci invalidates the */
1766 blr /* entire I cache */
1769 addi r6,0,0x0000 /* clear GPR 6 */
1770 /* Do loop for # of dcache congruence classes. */
1771 lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
1772 ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1773 /* NOTE: dccci invalidates both */
1774 mtctr r7 /* ways in the D cache */
1776 dccci 0,r6 /* invalidate line */
1777 addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1781 /**************************************************************************/
1782 /* PPC405EP specific stuff */
1783 /**************************************************************************/
1787 #ifdef CONFIG_BUBINGA
1789 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1790 * function) to support FPGA and NVRAM accesses below.
1793 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1794 ori r3,r3,GPIO0_OSRH@l
1795 lis r4,CFG_GPIO0_OSRH@h
1796 ori r4,r4,CFG_GPIO0_OSRH@l
1799 ori r3,r3,GPIO0_OSRL@l
1800 lis r4,CFG_GPIO0_OSRL@h
1801 ori r4,r4,CFG_GPIO0_OSRL@l
1804 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1805 ori r3,r3,GPIO0_ISR1H@l
1806 lis r4,CFG_GPIO0_ISR1H@h
1807 ori r4,r4,CFG_GPIO0_ISR1H@l
1809 lis r3,GPIO0_ISR1L@h
1810 ori r3,r3,GPIO0_ISR1L@l
1811 lis r4,CFG_GPIO0_ISR1L@h
1812 ori r4,r4,CFG_GPIO0_ISR1L@l
1815 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1816 ori r3,r3,GPIO0_TSRH@l
1817 lis r4,CFG_GPIO0_TSRH@h
1818 ori r4,r4,CFG_GPIO0_TSRH@l
1821 ori r3,r3,GPIO0_TSRL@l
1822 lis r4,CFG_GPIO0_TSRL@h
1823 ori r4,r4,CFG_GPIO0_TSRL@l
1826 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1827 ori r3,r3,GPIO0_TCR@l
1828 lis r4,CFG_GPIO0_TCR@h
1829 ori r4,r4,CFG_GPIO0_TCR@l
1832 li r3,pb1ap /* program EBC bank 1 for RTC access */
1834 lis r3,CFG_EBC_PB1AP@h
1835 ori r3,r3,CFG_EBC_PB1AP@l
1839 lis r3,CFG_EBC_PB1CR@h
1840 ori r3,r3,CFG_EBC_PB1CR@l
1843 li r3,pb1ap /* program EBC bank 1 for RTC access */
1845 lis r3,CFG_EBC_PB1AP@h
1846 ori r3,r3,CFG_EBC_PB1AP@l
1850 lis r3,CFG_EBC_PB1CR@h
1851 ori r3,r3,CFG_EBC_PB1CR@l
1854 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1856 lis r3,CFG_EBC_PB4AP@h
1857 ori r3,r3,CFG_EBC_PB4AP@l
1861 lis r3,CFG_EBC_PB4CR@h
1862 ori r3,r3,CFG_EBC_PB4CR@l
1866 #ifndef CFG_CPC0_PCI
1867 li r3,CPC0_PCI_HOST_CFG_EN
1868 #ifdef CONFIG_BUBINGA
1870 !-----------------------------------------------------------------------
1871 ! Check FPGA for PCI internal/external arbitration
1872 ! If board is set to internal arbitration, update cpc0_pci
1873 !-----------------------------------------------------------------------
1875 addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1876 ori r5,r5,FPGA_REG1@l
1877 lbz r5,0x0(r5) /* read to get PCI arb selection */
1878 andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1879 beq ..pci_cfg_set /* if not set, then bypass reg write*/
1881 ori r3,r3,CPC0_PCI_ARBIT_EN
1882 #else /* CFG_CPC0_PCI */
1884 #endif /* CFG_CPC0_PCI */
1886 mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1889 !-----------------------------------------------------------------------
1890 ! Check to see if chip is in bypass mode.
1891 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1892 ! CPU reset Otherwise, skip this step and keep going.
1893 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1894 ! will not be fast enough for the SDRAM (min 66MHz)
1895 !-----------------------------------------------------------------------
1897 mfdcr r5, CPC0_PLLMR1
1898 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1901 beq pll_done /* if SSCS =b'1' then PLL has */
1902 /* already been set */
1903 /* and CPU has been reset */
1904 /* so skip to next section */
1906 #ifdef CONFIG_BUBINGA
1908 !-----------------------------------------------------------------------
1909 ! Read NVRAM to get value to write in PLLMR.
1910 ! If value has not been correctly saved, write default value
1911 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1912 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1914 ! WARNING: This code assumes the first three words in the nvram_t
1915 ! structure in openbios.h. Changing the beginning of
1916 ! the structure will break this code.
1918 !-----------------------------------------------------------------------
1920 addis r3,0,NVRAM_BASE@h
1921 addi r3,r3,NVRAM_BASE@l
1924 addis r5,0,NVRVFY1@h
1925 addi r5,r5,NVRVFY1@l
1926 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1930 addis r5,0,NVRVFY2@h
1931 addi r5,r5,NVRVFY2@l
1932 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1934 addi r3,r3,8 /* Skip over conf_size */
1935 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1936 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1937 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1938 cmpi cr0,0,r5,1 /* See if PLL is locked */
1941 #endif /* CONFIG_BUBINGA */
1943 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1944 ori r3,r3,PLLMR0_DEFAULT@l /* */
1945 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1946 ori r4,r4,PLLMR1_DEFAULT@l /* */
1948 b pll_write /* Write the CPC0_PLLMR with new value */
1952 !-----------------------------------------------------------------------
1953 ! Clear Soft Reset Register
1954 ! This is needed to enable PCI if not booting from serial EPROM
1955 !-----------------------------------------------------------------------
1965 blr /* return to main code */
1968 !-----------------------------------------------------------------------------
1969 ! Function: pll_write
1970 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1972 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1974 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1975 ! 4. PLL Reset is cleared
1976 ! 5. Wait 100us for PLL to lock
1977 ! 6. A core reset is performed
1978 ! Input: r3 = Value to write to CPC0_PLLMR0
1979 ! Input: r4 = Value to write to CPC0_PLLMR1
1981 !-----------------------------------------------------------------------------
1986 ori r5,r5,0x0101 /* Stop the UART clocks */
1987 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1989 mfdcr r5, CPC0_PLLMR1
1990 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1991 mtdcr CPC0_PLLMR1,r5
1992 oris r5,r5,0x4000 /* Set PLL Reset */
1993 mtdcr CPC0_PLLMR1,r5
1995 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1996 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1997 oris r5,r5,0x4000 /* Set PLL Reset */
1998 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1999 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2000 mtdcr CPC0_PLLMR1,r5
2003 ! Wait min of 100us for PLL to lock.
2004 ! See CMOS 27E databook for more info.
2005 ! At 200MHz, that means waiting 20,000 instructions
2007 addi r3,0,20000 /* 2000 = 0x4e20 */
2012 oris r5,r5,0x8000 /* Enable PLL */
2013 mtdcr CPC0_PLLMR1,r5 /* Engage */
2016 * Reset CPU to guarantee timings are OK
2017 * Not sure if this is needed...
2020 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2021 /* execution will continue from the poweron */
2022 /* vector of 0xfffffffc */
2023 #endif /* CONFIG_405EP */
2025 #if defined(CONFIG_440)
2026 /*----------------------------------------------------------------------------+
2028 +----------------------------------------------------------------------------*/
2029 function_prolog(mttlb3)
2032 function_epilog(mttlb3)
2034 /*----------------------------------------------------------------------------+
2036 +----------------------------------------------------------------------------*/
2037 function_prolog(mftlb3)
2040 function_epilog(mftlb3)
2042 /*----------------------------------------------------------------------------+
2044 +----------------------------------------------------------------------------*/
2045 function_prolog(mttlb2)
2048 function_epilog(mttlb2)
2050 /*----------------------------------------------------------------------------+
2052 +----------------------------------------------------------------------------*/
2053 function_prolog(mftlb2)
2056 function_epilog(mftlb2)
2058 /*----------------------------------------------------------------------------+
2060 +----------------------------------------------------------------------------*/
2061 function_prolog(mttlb1)
2064 function_epilog(mttlb1)
2066 /*----------------------------------------------------------------------------+
2068 +----------------------------------------------------------------------------*/
2069 function_prolog(mftlb1)
2072 function_epilog(mftlb1)
2073 #endif /* CONFIG_440 */