git.sur5r.net Git - u-boot/blob - cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Zuepke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34 .globl _start
  35 _start: b       reset
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction: .word undefined_instruction
  45 _software_interrupt:    .word software_interrupt
  46 _prefetch_abort:        .word prefetch_abort
  47 _data_abort:            .word data_abort
  48 _not_used:              .word not_used
  49 _irq:                   .word irq
  50 _fiq:                   .word fiq
  51
  52         .balignl 16,0xdeadbeef
  53
  54
  55 /*
  56  * Startup Code (reset vector)
  57  *
  58  * do important init only if we don't start from RAM!
  59  * - relocate armboot to ram
  60  * - setup stack
  61  * - jump to second stage
  62  */
  63
  64 _TEXT_BASE:
  65         .word   TEXT_BASE
  66
  67 .globl _armboot_start
  68 _armboot_start:
  69         .word _start
  70
  71 /*
  72  * Note: _armboot_end_data and _armboot_end are defined
  73  * by the (board-dependent) linker script.
  74  * _armboot_end_data is the first usable FLASH address after armboot
  75  */
  76 .globl _armboot_end_data
  77 _armboot_end_data:
  78         .word armboot_end_data
  79 .globl _armboot_end
  80 _armboot_end:
  81         .word armboot_end
  82
  83 /*
  84  * This is defined in the board specific linker script
  85  */
  86 .globl _bss_start
  87 _bss_start:
  88         .word bss_start
  89
  90 .globl _bss_end
  91 _bss_end:
  92         .word bss_end
  93
  94 #ifdef CONFIG_USE_IRQ
  95 /* IRQ stack memory (calculated at run-time) */
  96 .globl IRQ_STACK_START
  97 IRQ_STACK_START:
  98         .word   0x0badc0de
  99
 100 /* IRQ stack memory (calculated at run-time) */
 101 .globl FIQ_STACK_START
 102 FIQ_STACK_START:
 103         .word 0x0badc0de
 104 #endif
 105
 106
 107 /****************************************************************************/
 108 /*                                                                          */
 109 /* the actual reset code                                                    */
 110 /*                                                                          */
 111 /****************************************************************************/
 112
 113 reset:
 114         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 115         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 116         orr     r0,r0,#0x13
 117         msr     cpsr,r0
 118
 119         /*
 120          * we do sys-critical inits only at reboot,
 121          * not when booting from ram!
 122          */
 123 #ifdef CONFIG_INIT_CRITICAL
 124         bl      cpu_init_crit           /* we do sys-critical inits         */
 125 #endif
 126
 127 relocate:                               /* relocate U-Boot to RAM           */
 128         adr     r0, _start              /* r0 <- current position of code   */
 129         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 130         cmp     r0, r1                  /* don't reloc during debug         */
 131         beq     stack_setup
 132
 133         ldr     r2, _armboot_start
 134         ldr     r3, _armboot_end
 135         sub     r2, r3, r2              /* r2 <- size of armboot            */
 136         add     r2, r0, r2              /* r2 <- source end address         */
 137
 138 copy_loop:
 139         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 140         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 141         cmp     r0, r2                  /* until source end addreee [r2]    */
 142         ble     copy_loop
 143
 144         /* Set up the stack                                                 */
 145 stack_setup:
 146         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 147         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 148         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 149 #ifdef CONFIG_USE_IRQ
 150         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 151 #endif
 152         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 153
 154 clear_bss:
 155
 156         ldr     r0, _bss_start          /* find start of bss segment        */
 157         add     r0, r0, #4              /* start at first byte of bss       */
 158         ldr     r1, _bss_end            /* stop here                        */
 159         mov     r2, #0x00000000         /* clear                            */
 160
 161 clbss_l:str     r2, [r0]                /* clear loop...                    */
 162         add     r0, r0, #4
 163         cmp     r0, r1
 164         bne     clbss_l
 165
 166
 167         ldr     pc, _start_armboot
 168
 169 _start_armboot: .word start_armboot
 170
 171
 172 /****************************************************************************/
 173 /*                                                                          */
 174 /* CPU_init_critical registers                                              */
 175 /*                                                                          */
 176 /* - setup important registers                                              */
 177 /* - setup memory timing                                                    */
 178 /*                                                                          */
 179 /****************************************************************************/
 180
 181 /* Interrupt-Controller base address                                        */
 182 IC_BASE:           .word           0x40d00000
 183 #define ICMR    0x04
 184
 185 /* Reset-Controller */
 186 RST_BASE:       .word   0x40f00030
 187 #define RCSR    0x00
 188
 189 /* Operating System Timer */
 190 OSTIMER_BASE:   .word   0x40a00000
 191 #define OSMR3   0x0C
 192 #define OSCR    0x10
 193 #define OWER    0x18
 194 #define OIER    0x1C
 195
 196 /* Clock Manager Registers                                                  */
 197 #ifdef CFG_CPUSPEED
 198 CC_BASE:        .word   0x41300000
 199 #define CCCR    0x00
 200 cpuspeed:       .word   CFG_CPUSPEED
 201 #else
 202 #error "You have to define CFG_CPUSPEED!!"
 203 #endif
 204
 205
 206         /* RS: ???                                                          */
 207         .macro CPWAIT
 208         mrc  p15,0,r0,c2,c0,0
 209         mov  r0,r0
 210         sub  pc,pc,#4
 211         .endm
 212
 213
 214 cpu_init_crit:
 215
 216         /* mask all IRQs                                                    */
 217         ldr     r0, IC_BASE
 218         mov     r1, #0x00
 219         str     r1, [r0, #ICMR]
 220
 221 #if defined(CFG_CPUSPEED)
 222
 223         /* set clock speed */
 224         ldr     r0, CC_BASE
 225         ldr     r1, cpuspeed
 226         str     r1, [r0, #CCCR]
 227         mov     r0, #2
 228         mcr     p14, 0, r0, c6, c0, 0
 229
 230 setspeed_done:
 231 #endif
 232
 233         /*
 234          * before relocating, we have to setup RAM timing
 235          * because memory timing is board-dependend, you will
 236          * find a memsetup.S in your board directory.
 237          */
 238         mov     ip,     lr
 239         bl      memsetup
 240         mov     lr,     ip
 241
 242         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 243
 244         ldr     r0, =0x2001             /* enable access to all coproc.     */
 245         mcr     p15, 0, r0, c15, c1, 0
 246         CPWAIT
 247
 248         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 249         CPWAIT
 250
 251         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 252         CPWAIT
 253
 254         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 255         CPWAIT
 256
 257         /* Enable the Icache                                                */
 258 /*
 259         mrc     p15, 0, r0, c1, c0, 0
 260         orr     r0, r0, #0x1800
 261         mcr     p15, 0, r0, c1, c0, 0
 262         CPWAIT
 263 */
 264         mov     pc, lr
 265
 266
 267 /****************************************************************************/
 268 /*                                                                          */
 269 /* Interrupt handling                                                       */
 270 /*                                                                          */
 271 /****************************************************************************/
 272
 273 /* IRQ stack frame                                                          */
 274
 275 #define S_FRAME_SIZE    72
 276
 277 #define S_OLD_R0        68
 278 #define S_PSR           64
 279 #define S_PC            60
 280 #define S_LR            56
 281 #define S_SP            52
 282
 283 #define S_IP            48
 284 #define S_FP            44
 285 #define S_R10           40
 286 #define S_R9            36
 287 #define S_R8            32
 288 #define S_R7            28
 289 #define S_R6            24
 290 #define S_R5            20
 291 #define S_R4            16
 292 #define S_R3            12
 293 #define S_R2            8
 294 #define S_R1            4
 295 #define S_R0            0
 296
 297 #define MODE_SVC 0x13
 298
 299         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 300
 301         .macro  bad_save_user_regs
 302         sub     sp, sp, #S_FRAME_SIZE
 303         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 304         add     r8, sp, #S_PC
 305
 306         ldr     r2, _armboot_end
 307         add     r2, r2, #CONFIG_STACKSIZE
 308         sub     r2, r2, #8
 309         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 310         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 311
 312         add     r5, sp, #S_SP
 313         mov     r1, lr
 314         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 315         mov     r0, sp
 316         .endm
 317
 318
 319         /* use irq_save_user_regs / irq_restore_user_regs for                */
 320         /* IRQ/FIQ handling                                                  */
 321
 322         .macro  irq_save_user_regs
 323         sub     sp, sp, #S_FRAME_SIZE
 324         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 325         add     r8, sp, #S_PC
 326         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 327         str     lr, [r8, #0]                    /* Save calling PC           */
 328         mrs     r6, spsr
 329         str     r6, [r8, #4]                    /* Save CPSR                 */
 330         str     r0, [r8, #8]                    /* Save OLD_R0               */
 331         mov     r0, sp
 332         .endm
 333
 334         .macro  irq_restore_user_regs
 335         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 336         mov     r0, r0
 337         ldr     lr, [sp, #S_PC]                 @ Get PC
 338         add     sp, sp, #S_FRAME_SIZE
 339         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 340         .endm
 341
 342         .macro get_bad_stack
 343         ldr     r13, _armboot_end               @ setup our mode stack
 344         add     r13, r13, #CONFIG_STACKSIZE     @ resides at top of normal stack
 345         sub     r13, r13, #8
 346
 347         str     lr, [r13]                       @ save caller lr / spsr
 348         mrs     lr, spsr
 349         str     lr, [r13, #4]
 350
 351         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 352         msr     spsr_c, r13
 353         mov     lr, pc
 354         movs    pc, lr
 355         .endm
 356
 357         .macro get_irq_stack                    @ setup IRQ stack
 358         ldr     sp, IRQ_STACK_START
 359         .endm
 360
 361         .macro get_fiq_stack                    @ setup FIQ stack
 362         ldr     sp, FIQ_STACK_START
 363         .endm
 364
 365
 366 /****************************************************************************/
 367 /*                                                                          */
 368 /* exception handlers                                                       */
 369 /*                                                                          */
 370 /****************************************************************************/
 371
 372         .align  5
 373 undefined_instruction:
 374         get_bad_stack
 375         bad_save_user_regs
 376         bl      do_undefined_instruction
 377
 378         .align  5
 379 software_interrupt:
 380         get_bad_stack
 381         bad_save_user_regs
 382         bl      do_software_interrupt
 383
 384         .align  5
 385 prefetch_abort:
 386         get_bad_stack
 387         bad_save_user_regs
 388         bl      do_prefetch_abort
 389
 390         .align  5
 391 data_abort:
 392         get_bad_stack
 393         bad_save_user_regs
 394         bl      do_data_abort
 395
 396         .align  5
 397 not_used:
 398         get_bad_stack
 399         bad_save_user_regs
 400         bl      do_not_used
 401
 402 #ifdef CONFIG_USE_IRQ
 403
 404         .align  5
 405 irq:
 406         get_irq_stack
 407         irq_save_user_regs
 408         bl      do_irq
 409         irq_restore_user_regs
 410
 411         .align  5
 412 fiq:
 413         get_fiq_stack
 414         irq_save_user_regs              /* someone ought to write a more    */
 415         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 416         irq_restore_user_regs
 417
 418 #else
 419
 420         .align  5
 421 irq:
 422         get_bad_stack
 423         bad_save_user_regs
 424         bl      do_irq
 425
 426         .align  5
 427 fiq:
 428         get_bad_stack
 429         bad_save_user_regs
 430         bl      do_fiq
 431
 432 #endif
 433
 434 /****************************************************************************/
 435 /*                                                                          */
 436 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 437 /* perform a watchdog timeout for a soft reset.                             */
 438 /*                                                                          */
 439 /****************************************************************************/
 440
 441         .align  5
 442 .globl reset_cpu
 443
 444         /* FIXME: this code is PXA250 specific. How is this handled on      */
 445         /*        other XScale processors?                                  */
 446
 447 reset_cpu:
 448
 449         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 450
 451         ldr     r0, OSTIMER_BASE
 452         ldr     r1, [r0, #OWER]
 453         orr     r1, r1, #0x0001                 /* bit0: WME                */
 454         str     r1, [r0, #OWER]
 455
 456         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 457         /* the match register as well.                                      */
 458
 459         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 460         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 461         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 462         str     r1, [r0, #OSMR3]
 463
 464 reset_endless:
 465
 466         b       reset_endless