2 * Startup Code for S3C44B0 CPU-core
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42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
48 add pc, pc, #0x0c000000
50 .balignl 16,0xdeadbeef
54 *************************************************************************
56 * Startup Code (reset vector)
58 * do important init only if we don't start from memory!
59 * relocate u-boot to ram
61 * jump to second stage
63 *************************************************************************
74 * These are defined in the board-specific linker script.
85 /* IRQ stack memory (calculated at run-time) */
86 .globl IRQ_STACK_START
90 /* IRQ stack memory (calculated at run-time) */
91 .globl FIQ_STACK_START
98 * the actual reset code
103 * set the cpu to SVC32 mode
111 * we do sys-critical inits only at reboot,
112 * not when booting from ram!
115 #ifdef CONFIG_INIT_CRITICAL
118 * before relocating, we have to setup RAM timing
119 * because memory timing is board-dependend, you will
120 * find a memsetup.S in your board directory.
125 relocate: /* relocate U-Boot to RAM */
126 adr r0, _start /* r0 <- current position of code */
127 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
128 cmp r0, r1 /* don't reloc during debug */
131 ldr r2, _armboot_start
133 sub r2, r3, r2 /* r2 <- size of armboot */
134 add r2, r0, r2 /* r2 <- source end address */
137 ldmia r0!, {r3-r10} /* copy from source address [r0] */
138 stmia r1!, {r3-r10} /* copy to target address [r1] */
139 cmp r0, r2 /* until source end addreee [r2] */
143 now copy to sram the interrupt vector
155 /* Set up the stack */
157 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
158 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
159 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
160 #ifdef CONFIG_USE_IRQ
161 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
163 sub sp, r0, #12 /* leave 3 words for abort-stack */
165 ldr pc, _start_armboot
167 _start_armboot: .word start_armboot
171 *************************************************************************
173 * CPU_init_critical registers
175 * setup important registers
176 * setup memory timing
178 *************************************************************************
181 #define INTCON (0x01c00000+0x200000)
182 #define INTMSK (0x01c00000+0x20000c)
183 #define LOCKTIME (0x01c00000+0x18000c)
184 #define PLLCON (0x01c00000+0x180000)
185 #define CLKCON (0x01c00000+0x180004)
186 #define WTCON (0x01c00000+0x130000)
188 /* disable watch dog */
194 * mask all IRQs by clearing all bits in the INTMRs
204 /* Set Clock Control Register */
211 #if CONFIG_S3C44B0_CLOCK_SPEED==66
212 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
213 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
214 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
216 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
228 /*************************************************/
229 /* interrupt vectors */
230 /*************************************************/
233 b undefined_instruction
241 /*************************************************/
243 undefined_instruction:
260 /* we *should* never reach this */