2 * Startup Code for S3C44B0 CPU-core
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42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
48 add pc, pc, #0x0c000000
50 .balignl 16,0xdeadbeef
54 *************************************************************************
56 * Startup Code (reset vector)
58 * do important init only if we don't start from memory!
59 * relocate u-boot to ram
61 * jump to second stage
63 *************************************************************************
74 * Note: _armboot_end_data and _armboot_end are defined
75 * by the (board-dependent) linker script.
76 * _armboot_end_data is the first usable FLASH address after armboot
78 .globl _armboot_end_data
80 .word armboot_end_data
86 /* IRQ stack memory (calculated at run-time) */
87 .globl IRQ_STACK_START
91 /* IRQ stack memory (calculated at run-time) */
92 .globl FIQ_STACK_START
99 * the actual reset code
104 * set the cpu to SVC32 mode
112 * we do sys-critical inits only at reboot,
113 * not when booting from ram!
116 #ifdef CONFIG_INIT_CRITICAL
119 * before relocating, we have to setup RAM timing
120 * because memory timing is board-dependend, you will
121 * find a memsetup.S in your board directory.
126 relocate: /* relocate U-Boot to RAM */
127 adr r0, _start /* r0 <- current position of code */
128 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
129 cmp r0, r1 /* don't reloc during debug */
132 ldr r2, _armboot_start
134 sub r2, r3, r2 /* r2 <- size of armboot */
135 add r2, r0, r2 /* r2 <- source end address */
138 ldmia r0!, {r3-r10} /* copy from source address [r0] */
139 stmia r1!, {r3-r10} /* copy to target address [r1] */
140 cmp r0, r2 /* until source end addreee [r2] */
144 now copy to sram the interrupt vector
156 /* Set up the stack */
158 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
159 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
160 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
161 #ifdef CONFIG_USE_IRQ
162 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
164 sub sp, r0, #12 /* leave 3 words for abort-stack */
166 ldr pc, _start_armboot
168 _start_armboot: .word start_armboot
172 *************************************************************************
174 * CPU_init_critical registers
176 * setup important registers
177 * setup memory timing
179 *************************************************************************
182 #define INTCON (0x01c00000+0x200000)
183 #define INTMSK (0x01c00000+0x20000c)
184 #define LOCKTIME (0x01c00000+0x18000c)
185 #define PLLCON (0x01c00000+0x180000)
186 #define CLKCON (0x01c00000+0x180004)
187 #define WTCON (0x01c00000+0x130000)
189 /* disable watch dog */
195 * mask all IRQs by clearing all bits in the INTMRs
205 /* Set Clock Control Register */
212 #if CONFIG_S3C44B0_CLOCK_SPEED==66
213 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
214 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
215 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
217 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
229 /*************************************************/
230 /* interrupt vectors */
231 /*************************************************/
234 b undefined_instruction
242 /*************************************************/
244 undefined_instruction:
261 /* we *should* never reach this */