2 * armboot - Startup Code for SA1100 CPU
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 *************************************************************************
36 * Jump vector table as in table 3.1 in [1]
38 *************************************************************************
44 ldr pc, _undefined_instruction
45 ldr pc, _software_interrupt
46 ldr pc, _prefetch_abort
52 _undefined_instruction: .word undefined_instruction
53 _software_interrupt: .word software_interrupt
54 _prefetch_abort: .word prefetch_abort
55 _data_abort: .word data_abort
56 _not_used: .word not_used
60 .balignl 16,0xdeadbeef
64 *************************************************************************
66 * Startup Code (reset vector)
68 * do important init only if we don't start from memory!
69 * relocate armboot to ram
71 * jump to second stage
73 *************************************************************************
84 * These are defined in the board-specific linker script.
95 /* IRQ stack memory (calculated at run-time) */
96 .globl IRQ_STACK_START
100 /* IRQ stack memory (calculated at run-time) */
101 .globl FIQ_STACK_START
108 * the actual reset code
113 * set the cpu to SVC32 mode
121 * we do sys-critical inits only at reboot,
122 * not when booting from ram!
124 #ifdef CONFIG_INIT_CRITICAL
128 relocate: /* relocate U-Boot to RAM */
129 adr r0, _start /* r0 <- current position of code */
130 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
131 cmp r0, r1 /* don't reloc during debug */
134 ldr r2, _armboot_start
136 sub r2, r3, r2 /* r2 <- size of armboot */
137 add r2, r0, r2 /* r2 <- source end address */
140 ldmia r0!, {r3-r10} /* copy from source address [r0] */
141 stmia r1!, {r3-r10} /* copy to target address [r1] */
142 cmp r0, r2 /* until source end addreee [r2] */
145 /* Set up the stack */
147 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
148 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
149 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
150 #ifdef CONFIG_USE_IRQ
151 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
153 sub sp, r0, #12 /* leave 3 words for abort-stack */
156 ldr r0, _bss_start /* find start of bss segment */
157 add r0, r0, #4 /* start at first byte of bss */
158 ldr r1, _bss_end /* stop here */
159 mov r2, #0x00000000 /* clear */
161 clbss_l:str r2, [r0] /* clear loop... */
166 ldr pc, _start_armboot
168 _start_armboot: .word start_armboot
172 *************************************************************************
174 * CPU_init_critical registers
176 * setup important registers
177 * setup memory timing
179 *************************************************************************
183 /* Interupt-Controller base address */
184 IC_BASE: .word 0x90050000
188 /* Reset-Controller */
189 RST_BASE: .word 0x90030000
195 PWR_BASE: .word 0x90020000
198 cpuspeed: .word CFG_CPUSPEED
209 /* set clock speed */
215 * before relocating, we have to setup RAM timing
216 * because memory timing is board-dependend, you will
217 * find a memsetup.S in your board directory.
224 * disable MMU stuff and enable I-cache
227 bic r0, r0, #0x00002000 @ clear bit 13 (X)
228 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
229 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
230 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
234 * flush v4 I/D caches
237 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
238 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
244 *************************************************************************
248 *************************************************************************
254 #define S_FRAME_SIZE 72
276 #define MODE_SVC 0x13
280 * use bad_save_user_regs for abort/prefetch/undef/swi ...
281 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
284 .macro bad_save_user_regs
285 sub sp, sp, #S_FRAME_SIZE
286 stmia sp, {r0 - r12} @ Calling r0-r12
289 ldr r2, _armboot_start
290 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
291 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
292 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
293 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
297 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
301 .macro irq_save_user_regs
302 sub sp, sp, #S_FRAME_SIZE
303 stmia sp, {r0 - r12} @ Calling r0-r12
305 stmdb r8, {sp, lr}^ @ Calling SP, LR
306 str lr, [r8, #0] @ Save calling PC
308 str r6, [r8, #4] @ Save CPSR
309 str r0, [r8, #8] @ Save OLD_R0
313 .macro irq_restore_user_regs
314 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
316 ldr lr, [sp, #S_PC] @ Get PC
317 add sp, sp, #S_FRAME_SIZE
318 subs pc, lr, #4 @ return & move spsr_svc into cpsr
322 ldr r13, _armboot_start @ setup our mode stack
323 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
324 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
326 str lr, [r13] @ save caller lr / spsr
330 mov r13, #MODE_SVC @ prepare SVC-Mode
336 .macro get_irq_stack @ setup IRQ stack
337 ldr sp, IRQ_STACK_START
340 .macro get_fiq_stack @ setup FIQ stack
341 ldr sp, FIQ_STACK_START
348 undefined_instruction:
351 bl do_undefined_instruction
357 bl do_software_interrupt
377 #ifdef CONFIG_USE_IRQ
384 irq_restore_user_regs
389 /* someone ought to write a more effiction fiq_save_user_regs */
392 irq_restore_user_regs
414 mov r1, #0x0 @ set bit 3-0 ...
415 str r1, [r0, #RCSR] @ ... to clear in RCSR
417 str r1, [r0, #RSRR] @ and perform reset
418 b reset_cpu @ silly, but repeat endlessly