3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
5 STiH407 based platforms.
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
12 encompasses the glue registers
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
14 for the powerdown and softreset lines of the usb3 IP
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
17 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
20 - pinctl-names : A pinctrl state named "default" must be defined
22 - pinctrl-0 : Pin control group
24 - ranges : allows valid 1:1 translation between child's address space and
25 parent's address space
28 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
31 NB: The dr_mode property is NOT optional for this driver, as the default value
32 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are
33 either "host" or "device".
37 st_dwc3: dwc3@8f94000 {
39 compatible = "st,stih407-dwc3";
40 reg = <0x08f94000 0x1000>, <0x110 0x4>;
41 reg-names = "reg-glue", "syscfg-reg";
42 st,syscfg = <&syscfg_core>;
43 resets = <&powerdown STIH407_USB3_POWERDOWN>,
44 <&softreset STIH407_MIPHY2_SOFTRESET>;
45 reset-names = "powerdown", "softreset";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_usb3>;
53 compatible = "snps,dwc3";
54 reg = <0x09900000 0x100000>;
55 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
57 phy-names = "usb2-phy", "usb3-phy";
58 phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;