1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
10 @title Open On-Chip Debugger (openocd)
11 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
12 @subtitle @value{UPDATED}
14 @vskip 0pt plus 1filll
19 @node Top, About, , (dir)
22 This is edition @value{EDITION} of the openocd manual for version
23 @value{VERSION}, @value{UPDATED}
26 * About:: About Openocd.
28 * Building:: Building Openocd
29 * Running:: Running Openocd
30 * Configuration:: Openocd Configuration.
31 * Commands:: Openocd Commands
32 * Sample Scripts:: Sample Target Scripts
33 * GDB and Openocd:: Using GDB and Openocd
34 * FAQ:: Frequently Asked Questions
35 * License:: GNU Free Documentation License
43 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
44 and boundary-scan testing for embedded target devices. The targets are interfaced
45 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
46 connection types in the future.
48 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
49 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
50 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
51 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
53 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
54 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
55 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
61 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
62 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
63 Others interested in improving the state of free and open debug and testing technology
64 are welcome to participate.
66 Other developers have contributed support for additional targets and flashes as well
67 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
71 @cindex building openocd
73 You can download the current SVN version with SVN client of your choice from the
74 following repositories:
76 (@uref{svn://svn.berlios.de/openocd/trunk})
80 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
82 Using the SVN command line client, you could use the following command to fetch the
83 latest version (make sure there is no (non-svn) directory called "openocd" in the
87 svn checkout svn://svn.berlios.de/openocd/trunk
90 Building the OpenOCD requires a recent version of the GNU autotools.
91 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
92 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
93 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
94 paths, resulting in obscure dependency errors (This is an observation I've gathered
95 from the logs of one user - correct me if I'm wrong).
97 You further need the appropriate driver files, if you want to build support for
98 a FTDI FT2232 based interface:
100 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
101 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
102 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
103 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
106 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
107 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
109 In general, the D2XX driver provides superior performance (several times as fast),
110 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
111 a kernel module, only a user space library.
113 To build OpenOCD (on both Linux and Cygwin), use the following commands:
117 Bootstrap generates the configure script, and prepares building on your system.
121 Configure generates the Makefiles used to build OpenOCD
125 Make builds the OpenOCD, and places the final executable in ./src/
127 The configure script takes several options, specifying which JTAG interfaces
134 --enable-parport_ppdev
136 --enable-amtjtagaccel
138 --enable-ft2232_ftd2xx
139 @footnote{Using the latest D2XX drivers from FTDI and following their installation
140 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
143 --enable-ft2232_libftdi
145 --with-ftd2xx=/path/to/d2xx/
148 If you want to access the parallel port using the PPDEV interface you have to specify
149 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
150 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
151 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
153 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
154 absolute path containing no spaces.
156 Linux users should copy the various parts of the D2XX package to the appropriate
157 locations, i.e. /usr/include, /usr/lib.
161 @cindex running openocd
162 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
163 Run with @option{--help} or @option{-h} to view the available command line arguments.
165 It reads its configuration by default from the file openocd.cfg located in the current
166 working directory. This may be overwritten with the @option{-f <configfile>} command line
169 To enable debug output (when reporting problems or working on OpenOCD itself), use
170 the @option{-d} command line switch. This sets the debug_level to "3", outputting
171 the most information, including debug messages. The default setting is "2", outputting
172 only informational messages, warnings and errors. You can also change this setting
173 from within a telnet or gdb session (@option{debug_level <n>}).
175 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
178 @chapter Configuration
179 @cindex configuration
180 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
181 by default from the file openocd.cfg in the current directory. A different configuration
182 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
184 The configuration file is used to specify on which ports the daemon listens for new
185 connections, the JTAG interface used to connect to the target, the layout of the JTAG
186 chain, the targets that should be debugged, and connected flashes.
188 @section Daemon configuration
191 @item @b{telnet_port} <@var{number}>
193 Port on which to listen for incoming telnet connections
194 @item @b{gdb_port} <@var{number}>
196 First port on which to listen for incoming GDB connections. The GDB port for the
197 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
198 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
200 Configures what openocd will do when gdb detaches from the daeman.
201 Default behaviour is <@var{resume}>
202 @item @b{gdb_memory_map} <@var{enable|disable}>
203 @cindex gdb_memory_map
204 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
205 requested. gdb will then know when to set hardware breakpoints, and program flash
206 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
207 for flash programming to work.
208 Default behaviour is <@var{disable}>
209 @item @b{gdb_flash_program} <@var{enable|disable}>
210 @cindex gdb_flash_program
211 Set to <@var{enable}> so that openocd will program the flash memory when a
212 vFlash packet is received.
213 Default behaviour is <@var{disable}>
214 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
215 @cindex daemon_startup
216 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
217 if it should just attach to the target.
220 @section JTAG interface configuration
223 @item @b{interface} <@var{name}>
225 Use the interface driver <@var{name}> to connect to the target. Currently supported
229 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
233 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
238 FTDI FT2232 based devices using either the open-source libftdi or the binary only
239 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
240 platform. The libftdi uses libusb, and should be portable to all systems that provide
245 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
250 @item @b{jtag_speed} <@var{number}>
252 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
253 speed. The actual effect of this option depends on the JTAG interface used.
256 @item wiggler: maximum speed / @var{number}
257 @item ft2232: 6MHz / (@var{number}+1)
258 @item amt jtagaccel: 8 / 2**@var{number}
261 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
262 especially true for synthesized cores (-S).
264 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
266 The configuration of the reset signals available on the JTAG interface AND the target.
267 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
268 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
269 @samp{srst_only} or @samp{trst_and_srst}.
270 [@var{combination}] is an optional value specifying broken reset signal implementations.
271 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
272 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
273 that the system is reset together with the test logic (only hypothetical, I haven't
274 seen hardware with such a bug, and can be worked around).
276 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
277 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
278 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
279 (default) and @samp{srst_push_pull} for the system reset. These values only affect
280 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
282 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
284 Describes the devices that form the JTAG daisy chain, with the first device being
285 the one closest to TDO. The parameters are the length of the instruction register
286 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
287 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
288 The IDCODE instruction will in future be used to query devices for their JTAG
289 identification code. This line is the same for all ARM7 and ARM9 devices.
290 Other devices, like CPLDs, require different parameters. An example configuration
291 line for a Xilinx XC9500 CPLD would look like this:
293 jtag_device 8 0x01 0x0e3 0xfe
295 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
296 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
297 The IDCODE instruction is 0xfe.
299 @item @b{jtag_nsrst_delay} <@var{ms}>
300 @cindex jtag_nsrst_delay
301 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
302 starting new JTAG operations.
303 @item @b{jtag_ntrst_delay} <@var{ms}>
304 @cindex jtag_ntrst_delay
305 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
306 starting new JTAG operations.
308 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
309 or on-chip features) keep a reset line asserted for some time after the external reset
313 @section parport options
316 @item @b{parport_port} <@var{number}>
318 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
319 the @file{/dev/parport} device
321 When using PPDEV to access the parallel port, use the number of the parallel port:
322 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
323 you may encounter a problem.
324 @item @b{parport_cable} <@var{name}>
325 @cindex parport_cable
326 The layout of the parallel port cable used to connect to the target.
327 Currently supported cables are
331 Original Wiggler layout, also supported by several clones, such
332 as the Olimex ARM-JTAG
333 @item old_amt_wiggler
334 @cindex old_amt_wiggler
335 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
336 version available from the website uses the original Wiggler layout ('@var{wiggler}')
339 Describes the connection of the Amontec Chameleon's CPLD when operated in
340 configuration mode. This is only used to program the Chameleon itself, not
344 Xilinx Parallel cable III.
347 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
348 This is also the layout used by the HollyGates design
349 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
354 @item @b{parport_write_on_exit} <@var{on|off}>
355 @cindex parport_write_on_exit
356 This will configure the parallel driver to write a known value to the parallel
357 interface on exiting openocd
360 @section amt_jtagaccel options
362 @item @b{parport_port} <@var{number}>
364 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
365 @file{/dev/parport} device
367 @section ft2232 options
370 @item @b{ft2232_device_desc} <@var{description}>
371 @cindex ft2232_device_desc
372 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
373 default value is used. This setting is only valid if compiled with FTD2XX support.
374 @item @b{ft2232_layout} <@var{name}>
375 @cindex ft2232_layout
376 The layout of the FT2232 GPIO signals used to control output-enables and reset
377 signals. Valid layouts are
380 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
382 Amontec JTAGkey and JTAGkey-tiny
388 American Microsystems M5960
390 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
391 SRST signals on external connector
395 Hitex STM32 Performance Stick
397 Tin Can Tools Flyswatter
399 egnite Software turtelizer2
404 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
405 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
406 default values are used. This command is not available on Windows.
407 @item @b{ft2232_latency} <@var{ms}>
408 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
409 ft2232_read() fails to return the expected number of bytes. This can be caused by
410 USB communication delays and has proved hard to reproduce and debug. Setting the
411 FT2232 latency timer to a larger value increases delays for short USB packages but it
412 also reduces the risk of timeouts before receiving the expected number of bytes.
413 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
416 @section ep93xx options
417 @cindex ep93xx options
418 Currently, there are no options available for the ep93xx interface.
421 @section Target configuration
424 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
427 Defines a target that should be debugged. Currently supported types are:
440 If you want to use a target board that is not on this list, see Adding a new
443 Endianess may be @option{little} or @option{big}.
445 The reset_mode specifies what should happen to the target when a reset occurs:
449 Immediately request a target halt after reset. This allows targets to be debugged
450 from the very first instruction. This is only possible with targets and JTAG
451 interfaces that correctly implement the reset signals.
454 Similar to @option{reset_halt}, but executes the script file defined to handle the
455 'reset' event for the target. Like @option{reset_halt} this only works with
456 correct reset implementations.
459 Simply let the target run after a reset.
462 Let the target run for some time (default: 1s), and then request halt.
465 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
466 to run for some time, then halted, and the @option{reset} event script is executed.
469 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
470 completely independent (like the LPC2000 series), or where the JTAG interface is
471 unavailable for some time during startup (like the STR7 series), you can't use
472 @option{reset_halt} or @option{reset_init}.
474 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
475 @cindex target_script
476 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
478 TODO: describe exact semantic of events
479 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
480 @cindex run_and_halt_time
481 The amount of time the debugger should wait after releasing reset before it asserts
482 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
484 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
485 <@var{backup}|@var{nobackup}>
487 Specifies a working area for the debugger to use. This may be used to speed-up
488 downloads to target memory and flash operations, or to perform otherwise unavailable
489 operations (some coprocessor operations on ARM7/9 systems, for example). The last
490 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
491 a working_area that doesn't need to be backed up, as that slows down operation.
494 @subsection arm7tdmi options
495 @cindex arm7tdmi options
496 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
497 The arm7tdmi target definition requires at least one additional argument, specifying
498 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
499 The optional [@var{variant}] parameter has been removed in recent versions.
500 The correct feature set is determined at runtime.
502 @subsection arm720t options
503 @cindex arm720t options
504 ARM720t options are similar to ARM7TDMI options.
506 @subsection arm9tdmi options
507 @cindex arm9tdmi options
508 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
509 @option{arm920t}, @option{arm922t} and @option{arm940t}.
510 This enables the hardware single-stepping support found on these cores.
512 @subsection arm920t options
513 @cindex arm920t options
514 ARM920t options are similar to ARM9TDMI options.
516 @subsection arm966e options
517 @cindex arm966e options
518 ARM966e options are similar to ARM9TDMI options.
520 @subsection xscale options
521 @cindex xscale options
522 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
523 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
525 @section Flash configuration
526 @cindex Flash configuration
529 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
530 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
532 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
533 and <@var{bus_width}> bytes using the selected flash <driver>.
535 @item @b{flash autoerase} <@option{on}|@option{off}>
536 @cindex flash autoerase
537 auto erase flash banks prior to writing. Currently only works when using
538 @option{flash write_image} command. Default is @option{off}.
541 @subsection lpc2000 options
542 @cindex lpc2000 options
544 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
545 <@var{clock}> [@var{calc_checksum}]
546 LPC flashes don't require the chip and bus width to be specified. Additional
547 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
548 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
549 of the target this flash belongs to (first is 0), the frequency at which the core
550 is currently running (in kHz - must be an integral number), and the optional keyword
551 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
554 @subsection cfi options
557 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
559 CFI flashes require the number of the target they're connected to as an additional
560 argument. The CFI driver makes use of a working area (specified for the target)
561 to significantly speed up operation.
563 @var{chip_width} and @var{bus_width} are specified in bytes.
565 @subsection at91sam7 options
566 @cindex at91sam7 options
568 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
569 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
570 reading the chip-id and type.
572 @subsection str7 options
575 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
576 variant can be either STR71x, STR73x or STR75x.
578 @subsection str9 options
581 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
582 The str9 needs the flash controller to be configured prior to Flash programming, eg.
584 str9x flash_config 0 4 2 0 0x80000
586 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
588 @subsection str9 options (str9xpec driver)
590 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
591 Before using the flash commands the turbo mode will need enabling using str9xpec
592 @option{enable_turbo} <@var{num>.}
594 Only use this driver for locking/unlocking the device or configuring the option bytes.
595 Use the standard str9 driver for programming.
597 @subsection stellaris (LM3Sxxx) options
598 @cindex stellaris (LM3Sxxx) options
600 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
601 stellaris flash plugin only require the @var{target#}.
603 @subsection stm32x options
604 @cindex stm32x options
606 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
607 stm32x flash plugin only require the @var{target#}.
613 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
614 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
615 is available from both the telnet interface and a GDB session. To issue commands to the
616 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
617 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
623 @item @b{sleep} <@var{msec}>
625 Wait for n milliseconds before resuming. Useful in connection with script files
626 (@var{script} command and @var{target_script} configuration).
630 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
632 @item @b{debug_level} [@var{n}]
634 Display or adjust debug level to n<0-3>
636 @item @b{log_output} <@var{file}>
638 Redirect logging to <file> (default: stderr)
640 @item @b{script} <@var{file}>
642 Execute commands from <file>
646 @subsection Target state handling
648 @item @b{poll} [@option{on}|@option{off}]
650 Poll the target for its current state. If the target is in debug mode, architecture
651 specific information about the current state are printed. An optional parameter
652 allows continuous polling to be enabled and disabled.
656 Send a halt request to the target. The debugger signals the debug request,
657 and waits for the target to enter debug mode.
659 @item @b{resume} [@var{address}]
661 Resume the target at its current code position, or at an optional address.
663 @item @b{step} [@var{address}]
665 Single-step the target at its current code position, or at an optional address.
667 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
668 |@option{run_and_init}]
670 Do a hard-reset. The optional parameter specifies what should happen after the reset.
671 This optional parameter overwrites the setting specified in the configuration file,
672 making the new behaviour the default for the @option{reset} command.
679 Immediately halt the target (works only with certain configurations).
682 Immediately halt the target, and execute the reset script (works only with certain
685 @cindex reset run_and_halt
686 Let the target run for a certain amount of time, then request a halt.
688 @cindex reset run_and_init
689 Let the target run for a certain amount of time, then request a halt. Execute the
690 reset script once the target entered debug mode.
694 @subsection Memory access commands
695 These commands allow accesses of a specific size to the memory system:
697 @item @b{mdw} <@var{addr}> [@var{count}]
700 @item @b{mdh} <@var{addr}> [@var{count}]
702 display memory half-words
703 @item @b{mdb} <@var{addr}> [@var{count}]
706 @item @b{mww} <@var{addr}> <@var{value}>
709 @item @b{mwh} <@var{addr}> <@var{value}>
711 write memory half-word
712 @item @b{mwb} <@var{addr}> <@var{value}>
716 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
718 Load image <@var{file}> to target memory at <@var{address}>
719 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
721 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
722 (binary) <@var{file}>.
723 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
725 Verify <@var{file}> to target memory starting at <@var{address}>.
726 This will first attempt using a crc checksum, if this fails it will try a binary compare.
727 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
729 Load binary <@var{file}> to target memory at <@var{address}>
730 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
732 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
733 (binary) <@var{file}>.
736 @subsection Flash commands
737 @cindex Flash commands
739 @item @b{flash banks}
741 List configured flash banks
742 @item @b{flash info} <@var{num}>
744 Print info about flash bank <@option{num}>
745 @item @b{flash probe} <@var{num}>
747 Identify the flash, or validate the parameters of the configured flash. Operation
748 depends on the flash type.
749 @item @b{flash erase_check} <@var{num}>
750 @cindex flash erase_check
751 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
752 updates the erase state information displayed by @option{flash info}. That means you have
753 to issue an @option{erase_check} command after erasing or programming the device to get
755 @item @b{flash protect_check} <@var{num}>
756 @cindex flash protect_check
757 Check protection state of sectors in flash bank <num>.
759 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
761 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
762 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
763 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
764 the CFI driver). This command was replaced by the new command
765 @option{flash erase_sector} using the same syntax.
766 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
767 @cindex flash erase_sector
768 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
769 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
770 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
772 @item @b{flash erase_address} <@var{address}> <@var{length}>
773 @cindex flash erase_address
774 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
775 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
777 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
778 bytes from the beginning of the bank. This command was replaced by the new command
779 @option{flash write_binary} using the same syntax.
780 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
781 @cindex flash write_binary
782 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
783 <@option{offset}> bytes from the beginning of the bank.
784 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
785 @cindex flash write_image
786 Write the image <@var{file}> to the current target's flash bank(s). A relocation
787 [@var{offset}] can be specified and the file [@var{type}] can be specified
788 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
789 (ELF file) or @option{s19} (Motorola s19).
790 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
791 @cindex flash protect
792 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
793 <@var{last}> of @option{flash bank} <@var{num}>.
794 @item @b{flash auto_erase} <@var{on}|@var{off}>
795 @cindex flash auto_erase
796 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
797 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
801 @section Target Specific Commands
802 @cindex Target Specific Commands
804 @subsection AT91SAM7 specific commands
805 @cindex AT91SAM7 specific commands
806 The flash configuration is deduced from the chip identification register. The flash
807 controller handles erases automatically on a page (128/265 byte) basis so erase is
808 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
809 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
810 that can be erased separatly.Only an EraseAll command is supported by the controller
811 for each flash plane and this is called with
813 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
814 bulk erase flash planes first_plane to last_plane.
815 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
816 @cindex at91sam7 gpnvm
817 set or clear a gpnvm bit for the processor
820 @subsection STR9 specific commands
821 @cindex STR9 specific commands
822 These are flash specific commands when using the str9xpec driver.
824 @item @b{str9xpec enable_turbo} <@var{num}>
825 @cindex str9xpec enable_turbo
826 enable turbo mode, simply this will remove the str9 from the chain and talk
827 directly to the embedded flash controller.
828 @item @b{str9xpec disable_turbo} <@var{num}>
829 @cindex str9xpec disable_turbo
830 restore the str9 into jtag chain.
831 @item @b{str9xpec lock} <@var{num}>
832 @cindex str9xpec lock
833 lock str9 device. The str9 will only respond to an unlock command that will
835 @item @b{str9xpec unlock} <@var{num}>
836 @cindex str9xpec unlock
838 @item @b{str9xpec options_read} <@var{num}>
839 @cindex str9xpec options_read
840 read str9 option bytes.
841 @item @b{str9xpec options_write} <@var{num}>
842 @cindex str9xpec options_write
843 write str9 option bytes.
846 @subsection STR9 configuration
847 @cindex STR9 configuration
849 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
850 <@var{BBADR}> <@var{NBBADR}>
851 @cindex str9x flash_config
852 Configure str9 flash controller.
854 eg. str9x flash_config 0 4 2 0 0x80000
856 BBSR - Boot Bank Size register
857 NBBSR - Non Boot Bank Size register
858 BBADR - Boot Bank Start Address register
859 NBBADR - Boot Bank Start Address register
863 @subsection STR9 option byte configuration
864 @cindex STR9 option byte configuration
866 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
867 @cindex str9xpec options_cmap
868 configure str9 boot bank.
869 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
870 @cindex str9xpec options_lvdthd
871 configure str9 lvd threshold.
872 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
873 @cindex str9xpec options_lvdsel
874 configure str9 lvd source.
875 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
876 @cindex str9xpec options_lvdwarn
877 configure str9 lvd reset warning source.
880 @subsection STM32x specific commands
881 @cindex STM32x specific commands
883 These are flash specific commands when using the stm32x driver.
885 @item @b{stm32x lock} <@var{num}>
888 @item @b{stm32x unlock} <@var{num}>
889 @cindex stm32x unlock
891 @item @b{stm32x options_read} <@var{num}>
892 @cindex stm32x options_read
893 read stm32 option bytes.
894 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
895 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
896 @cindex stm32x options_write
897 write stm32 option bytes.
898 @item @b{stm32x mass_erase} <@var{num}>
899 @cindex stm32x mass_erase
900 mass erase flash memory.
904 @section Architecture Specific Commands
905 @cindex Architecture Specific Commands
907 @subsection ARMV4/5 specific commands
908 @cindex ARMV4/5 specific commands
910 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
911 or Intel XScale (XScale isn't supported yet).
913 @item @b{armv4_5 reg}
915 Display a list of all banked core registers, fetching the current value from every
916 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
918 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
919 @cindex armv4_5 core_mode
920 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
921 The target is resumed in the currently set @option{core_mode}.
924 @subsection ARM7/9 specific commands
925 @cindex ARM7/9 specific commands
927 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
928 ARM920t or ARM926EJ-S.
930 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
931 @cindex arm7_9 sw_bkpts
932 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
933 one of the watchpoint registers to implement software breakpoints. Disabling
934 SW Bkpts frees that register again.
935 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
936 @cindex arm7_9 force_hw_bkpts
937 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
938 breakpoints are turned into hardware breakpoints.
939 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
941 Enable use of the DBGRQ bit to force entry into debug mode. This should be
942 safe for all but ARM7TDMI--S cores (like Philips LPC).
943 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
944 @cindex arm7_9 fast_writes [DEPRECATED]
945 See @option{arm7_9 fast_memory_access} instead.
946 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
947 @cindex arm7_9 fast_memory_access
948 Allow the OpenOCD to read and write memory without checking completion of
949 the operation. This provides a huge speed increase, especially with USB JTAG
950 cables (FT2232), but might be unsafe if used with targets running at a very low
951 speed, like the 32kHz startup clock of an AT91RM9200.
952 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
953 @cindex arm7_9 dcc_downloads
954 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
955 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
956 unsafe, especially with targets running at a very low speed. This command was introduced
957 with OpenOCD rev. 60.
960 @subsection ARM920T specific commands
961 @cindex ARM920T specific commands
964 @item @b{arm920t cache_info}
965 @cindex arm920t cache_info
966 Print information about the caches found. This allows you to see if your target
967 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
968 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
969 @cindex arm920t md<bhw>_phys
970 Display memory at physical address addr.
971 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
972 @cindex arm920t mw<bhw>_phys
973 Write memory at physical address addr.
974 @item @b{arm920t read_cache} <@var{filename}>
975 @cindex arm920t read_cache
976 Dump the content of ICache and DCache to a file.
977 @item @b{arm920t read_mmu} <@var{filename}>
978 @cindex arm920t read_mmu
979 Dump the content of the ITLB and DTLB to a file.
980 @item @b{arm920t virt2phys} <@var{VA}>
981 @cindex arm920t virt2phys
982 Translate a virtual address to a physical address.
986 @section Debug commands
987 @cindex Debug commands
988 The following commands give direct access to the core, and are most likely
989 only useful while debugging the OpenOCD.
991 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
992 @cindex arm7_9 write_xpsr
993 Immediately write either the current program status register (CPSR) or the saved
994 program status register (SPSR), without changing the register cache (as displayed
995 by the @option{reg} and @option{armv4_5 reg} commands).
996 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
997 <@var{0=cpsr},@var{1=spsr}>
998 @cindex arm7_9 write_xpsr_im8
999 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1000 operation (similar to @option{write_xpsr}).
1001 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1002 @cindex arm7_9 write_core_reg
1003 Write a core register, without changing the register cache (as displayed by the
1004 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1005 encoding of the [M4:M0] bits of the PSR.
1009 @section JTAG commands
1010 @cindex JTAG commands
1012 @item @b{scan_chain}
1014 Print current scan chain configuration.
1015 @item @b{jtag_reset}
1017 Toggle reset lines <@var{trst}> <@var{srst}>.
1018 @item @b{endstate} <@var{tap_state}>
1020 Finish JTAG operations in <@var{tap_state}>.
1021 @item @b{runtest} <@var{num_cycles}>
1023 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1024 @item @b{statemove} [@var{tap_state}]
1026 Move to current endstate or [@var{tap_state}]
1029 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1032 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1033 @item @b{verify_ircapture}
1034 @cindex verify_ircapture
1035 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1038 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1041 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1044 @node Sample Scripts
1045 @chapter Sample Scripts
1048 This page will collect some script examples for different CPUs.
1050 The configuration script can be divided in the following section:
1052 @item daemon configuration
1054 @item jtag scan chain
1055 @item target configuration
1056 @item flash configuration
1059 Detailed information about each section can be found at OpenOCD configuration
1061 @section OMAP5912 Flash Debug
1062 @cindex OMAP5912 Flash Debug
1063 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1064 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1065 - (@uref{http://www.spectrumdigital.com}).
1066 @subsection Openocd config
1068 #daemon configuration
1075 parport_cable wiggler
1078 #use combined on interfaces or targets that can't set TRST/SRST separately
1079 reset_config trst_and_srst
1082 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1083 jtag_device 38 0x0 0x0 0x0
1084 jtag_device 4 0x1 0x0 0xe
1085 jtag_device 8 0x0 0x0 0x0
1087 #target configuration
1088 daemon_startup reset
1090 #target <type> <endianness> <reset mode> <chainpos> <variant>
1091 target arm926ejs little run_and_init 1 arm926ejs
1092 target_script 0 reset omap5912_osk.init
1093 run_and_halt_time 0 30
1095 # omap5912 lcd frame buffer as working area
1096 working_area 0 0x20000000 0x3e800 nobackup
1098 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1099 flash bank cfi 0x00000000 0x1000000 2 2 0
1102 @subsection Openocd init
1114 mww 0xfffec808 0x000000f5
1115 mww 0xfffec808 0x000000a0
1117 mww 0xfffeb048 0x0000aaaa
1119 mww 0xfffeb048 0x00005555
1128 @section STR71x Script
1129 @cindex STR71x Script
1130 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1132 #daemon configuration
1138 ft2232_device_desc "Amontec JTAGkey A"
1139 ft2232_layout jtagkey
1140 ft2232_vid_pid 0x0403 0xcff8
1143 #use combined on interfaces or targets that can't set TRST/SRST separately
1144 reset_config trst_and_srst srst_pulls_trst
1147 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1148 jtag_device 4 0x1 0xf 0xe
1150 #target configuration
1151 daemon_startup reset
1153 #target <type> <startup mode>
1154 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1155 target arm7tdmi little run_and_halt 0 arm7tdmi
1156 run_and_halt_time 0 30
1158 working_area 0 0x2000C000 0x4000 nobackup
1160 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1161 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1164 @section STR750 Script
1165 @cindex STR750 Script
1166 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1168 #daemon configuration
1174 ft2232_device_desc "Amontec JTAGkey A"
1175 ft2232_layout jtagkey
1176 ft2232_vid_pid 0x0403 0xcff8
1179 #use combined on interfaces or targets that can't set TRST/SRST separately
1180 #reset_config trst_and_srst srst_pulls_trst
1181 reset_config trst_and_srst srst_pulls_trst
1184 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1185 jtag_device 4 0x1 0xf 0xe
1187 #jtag nTRST and nSRST delay
1188 jtag_nsrst_delay 500
1189 jtag_ntrst_delay 500
1191 #target configuration
1192 daemon_startup reset
1194 #target <type> <startup mode>
1195 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1196 target arm7tdmi little run_and_halt 0 arm7tdmi
1197 run_and_halt_time 0 30
1199 working_area 0 0x40000000 0x4000 nobackup
1201 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1202 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1205 @section STR912 Script
1206 @cindex STR912 Script
1207 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1209 #daemon configuration
1215 ft2232_device_desc "Amontec JTAGkey A"
1216 ft2232_layout jtagkey
1219 #use combined on interfaces or targets that can't set TRST/SRST separately
1220 reset_config trst_and_srst
1223 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1224 jtag_device 8 0x1 0x1 0xfe
1225 jtag_device 4 0x1 0xf 0xe
1226 jtag_device 5 0x1 0x1 0x1e
1228 #target configuration
1229 daemon_startup reset
1231 #target <type> <startup mode>
1232 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1233 target arm966e little reset_halt 1 arm966e
1234 run_and_halt_time 0 30
1236 working_area 0 0x50000000 16384 nobackup
1238 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1239 flash bank str9x 0x00000000 0x00080000 0 0 0
1242 @section STR912 comstick
1243 @cindex STR912 comstick Script
1244 The following script was used with a Hitex STR9 Comstick:
1246 #daemon configuration
1252 ft2232_device_desc "STR9-comStick A"
1253 ft2232_layout comstick
1256 jtag_nsrst_delay 100
1257 jtag_ntrst_delay 100
1259 #use combined on interfaces or targets that can't set TRST/SRST separately
1260 reset_config trst_and_srst
1263 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1264 jtag_device 8 0x1 0x1 0xfe
1265 jtag_device 4 0x1 0xf 0xe
1266 jtag_device 5 0x1 0x1 0x1e
1268 #target configuration
1269 daemon_startup reset
1271 #target <type> <startup mode>
1272 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1273 target arm966e little reset_halt 1 arm966e
1274 run_and_halt_time 0 30
1276 working_area 0 0x50000000 16384 nobackup
1278 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1279 flash bank str9x 0x00000000 0x00080000 0 0 0
1282 @section STM32x Script
1283 @cindex STM32x Script
1284 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1286 #daemon configuration
1292 ft2232_device_desc "Amontec JTAGkey A"
1293 ft2232_layout jtagkey
1296 jtag_nsrst_delay 100
1297 jtag_ntrst_delay 100
1299 #use combined on interfaces or targets that can't set TRST/SRST separately
1300 reset_config trst_and_srst
1303 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1304 jtag_device 4 0x1 0xf 0xe
1305 jtag_device 5 0x1 0x1 0x1e
1307 #target configuration
1308 daemon_startup reset
1310 #target <type> <startup mode>
1311 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1312 target cortex_m3 little run_and_halt 0
1313 run_and_halt_time 0 30
1315 working_area 0 0x20000000 16384 nobackup
1317 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1318 flash bank stm32x 0x08000000 0x00020000 0 0 0
1321 @section STM32x Performance Stick
1322 @cindex STM32x Performance Stick Script
1323 The following script was used with the Hitex STM32 Performance Stick
1325 #daemon configuration
1331 ft2232_device_desc "STM32-PerformanceStick A"
1332 ft2232_layout stm32stick
1335 jtag_nsrst_delay 100
1336 jtag_ntrst_delay 100
1338 #use combined on interfaces or targets that can't set TRST/SRST separately
1339 reset_config trst_and_srst
1342 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1343 jtag_device 4 0x1 0xf 0xe
1344 jtag_device 5 0x1 0x1 0x1e
1345 jtag_device 4 0x1 0xf 0xe
1347 #target configuration
1348 daemon_startup reset
1350 #target <type> <startup mode>
1351 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1352 target cortex_m3 little run_and_halt 0
1353 run_and_halt_time 0 30
1355 working_area 0 0x20000000 16384 nobackup
1357 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1358 flash bank stm32x 0x08000000 0x00020000 0 0 0
1361 @section LPC2129 Script
1362 @cindex LPC2129 Script
1363 The following script was used with an wiggler PP and a LPC-2129 cpu:
1365 #daemon configuration
1372 parport_cable wiggler
1375 #use combined on interfaces or targets that can't set TRST/SRST separately
1376 reset_config trst_and_srst srst_pulls_trst
1379 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1380 jtag_device 4 0x1 0xf 0xe
1382 #target configuration
1383 daemon_startup reset
1385 #target <type> <startup mode>
1386 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1387 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1388 run_and_halt_time 0 30
1390 working_area 0 0x40000000 0x4000 nobackup
1392 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1393 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1396 @section LPC2148 Script
1397 @cindex LPC2148 Script
1398 The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
1400 #daemon configuration
1406 ft2232_device_desc "Amontec JTAGkey A"
1407 ft2232_layout jtagkey
1408 ft2232_vid_pid 0x0403 0xcff8
1411 #use combined on interfaces or targets that can't set TRST/SRST separately
1412 reset_config trst_and_srst srst_pulls_trst
1415 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1416 jtag_device 4 0x1 0xf 0xe
1418 #target configuration
1419 daemon_startup reset
1421 #target <type> <startup mode>
1422 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1423 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1424 run_and_halt_time 0 30
1426 working_area 0 0x40000000 0x8000 nobackup
1428 #flash configuration
1429 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1432 @section LPC2294 Script
1433 @cindex LPC2294 Script
1434 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1436 #daemon configuration
1442 ft2232_device_desc "Amontec JTAGkey A"
1443 ft2232_layout jtagkey
1444 ft2232_vid_pid 0x0403 0xcff8
1447 #use combined on interfaces or targets that can't set TRST/SRST separately
1448 reset_config trst_and_srst srst_pulls_trst
1451 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1452 jtag_device 4 0x1 0xf 0xe
1454 #target configuration
1455 daemon_startup reset
1457 #target <type> <startup mode>
1458 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1459 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1460 run_and_halt_time 0 30
1462 working_area 0 0x40000000 0x4000 nobackup
1464 #flash configuration
1465 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1468 @section AT91R40008 Script
1469 @cindex AT91R40008 Script
1470 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1472 #daemon configuration
1478 ft2232_device_desc "Amontec JTAGkey A"
1479 ft2232_layout jtagkey
1480 ft2232_vid_pid 0x0403 0xcff8
1482 jtag_nsrst_delay 200
1483 jtag_ntrst_delay 200
1485 #use combined on interfaces or targets that can't set TRST/SRST separately
1486 reset_config srst_only srst_pulls_trst
1489 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1490 jtag_device 4 0x1 0xf 0xe
1492 #target configuration
1493 daemon_startup reset
1495 #target <type> <startup mode>
1496 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1497 target arm7tdmi little run_and_halt 0 arm7tdmi
1498 run_and_halt_time 0 30
1501 @section AT91SAM7s Script
1502 @cindex AT91SAM7s Script
1503 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1505 #daemon configuration
1511 ft2232_device_desc "Olimex OpenOCD JTAG A"
1512 ft2232_layout olimex-jtag
1513 ft2232_vid_pid 0x15BA 0x0003
1515 jtag_nsrst_delay 200
1516 jtag_ntrst_delay 200
1518 #use combined on interfaces or targets that can't set TRST/SRST separately
1519 reset_config srst_only srst_pulls_trst
1522 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1523 jtag_device 4 0x1 0xf 0xe
1525 #target configuration
1526 daemon_startup reset
1528 #target <type> <startup mode>
1529 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1530 target arm7tdmi little run_and_halt 0 arm7tdmi
1531 run_and_halt_time 0 30
1533 # flash-options AT91
1534 working_area 0 0x00200000 0x4000 nobackup
1535 flash bank at91sam7 0 0 0 0 0
1538 # erase command (telnet-interface) for complete flash:
1539 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1540 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1541 # set/clear NVM-Bits:
1542 # at91sam7 gpnvm <num> <bit> <set|clear>
1543 # disable locking from SAM-BA:
1544 # flash protect 0 0 1 off
1547 @section XSCALE IXP42x Script
1548 @cindex XSCALE IXP42x Script
1549 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1551 #daemon configuration
1557 ft2232_device_desc "Amontec JTAGkey A"
1558 ft2232_layout jtagkey
1559 ft2232_vid_pid 0x0403 0xcff8
1561 jtag_nsrst_delay 200
1562 jtag_ntrst_delay 200
1564 #use combined on interfaces or targets that can't set TRST/SRST separately
1565 reset_config srst_only srst_pulls_trst
1568 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1569 jtag_device 7 0x1 0x7f 0x7e
1571 #target configuration
1572 daemon_startup reset
1574 #target <type> <startup mode>
1575 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1576 target xscale big run_and_halt 0 IXP42x
1577 run_and_halt_time 0 30
1580 @section Cirrus Logic EP9301 Script
1581 @cindex Cirrus Logic EP9301 Script
1582 The following script was used with FT2232 based JTAG interfaces and a
1583 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1585 #daemon configuration
1593 #ft2232_device_desc "Olimex OpenOCD JTAG"
1594 #ft2232_layout olimex-jtag
1595 #ft2232_vid_pid 0x15ba 0x0003
1597 #Amontec JTAGkey (and JTAGkey-Tiny)
1598 #Serial is only necessary if more than one JTAGkey is connected
1599 ft2232_device_desc "Amontec JTAGkey A"
1600 #ft2232_serial AMTJKV31
1601 #ft2232_serial T1P3S2W8
1602 ft2232_layout jtagkey
1603 ft2232_vid_pid 0x0403 0xcff8
1605 #wiggler/parallel port interface
1608 #parport_cable wiggler
1611 reset_config trst_and_srst
1614 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1615 jtag_device 4 0x1 0xf 0xe
1617 jtag_nsrst_delay 100
1618 jtag_ntrst_delay 100
1620 #target configuration
1621 daemon_startup attach
1623 #target <type> <endianess> <reset mode>
1624 target arm920t little reset_halt 0
1625 working_area 0 0x80014000 0x1000 backup
1627 #flash configuration
1628 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1629 flash bank cfi 0x60000000 0x1000000 2 2 0
1632 @section Hilscher netX 100 / 500 Script
1633 @cindex Hilscher netX 100 / 500 Script
1634 The following script was used with an Amontec JTAGkey and a Hilscher
1637 #daemon configuration
1643 ft2232_device_desc "Amontec JTAGkey A"
1644 ft2232_layout jtagkey
1645 ft2232_vid_pid 0x0403 0xcff8
1648 #use combined on interfaces or targets that can't set TRST/SRST separately
1649 reset_config trst_and_srst
1652 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1653 jtag_device 4 0x1 0xf 0xe
1655 jtag_nsrst_delay 100
1656 jtag_ntrst_delay 100
1658 #target configuration
1659 daemon_startup reset
1661 #target <type> <endianness> <startup mode> <chainpos> <variant>
1662 target arm926ejs little run_and_halt 0 arm926ejs
1663 run_and_halt_time 0 500
1666 @section Marvell/Intel PXA270 Script
1667 @cindex Marvell/Intel PXA270 Script
1669 # config for Intel PXA270
1670 # not, as of 2007-06-22, openocd only works with the
1671 # libftd2xx library from ftdi. libftdi does not work.
1677 ft2232_layout olimex-jtag
1678 ft2232_vid_pid 0x15BA 0x0003
1679 ft2232_device_desc "Olimex OpenOCD JTAG"
1681 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1682 # the rest of the needed delays are built into the openocd program
1683 jtag_nsrst_delay 260
1684 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1685 # the rest of the needed delays are built into the openocd program
1688 #use combined on interfaces or targets that can't set TRST/SRST separately
1689 reset_config trst_and_srst separate
1692 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1693 jtag_device 7 0x1 0x7f 0x7e
1695 #target configuration
1696 daemon_startup reset
1698 target xscale little reset_halt 0 pxa27x
1700 # maps to PXA internal RAM. If you are using a PXA255
1701 # you must initialize SDRAM or leave this option off
1702 working_area 0 0x5c000000 0x10000 nobackup
1704 run_and_halt_time 0 30
1706 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1707 # works for P30 flash
1708 flash bank cfi 0x00000000 0x1000000 2 4 0
1711 @node GDB and Openocd
1712 @chapter GDB and Openocd
1713 @cindex GDB and Openocd
1714 Openocd complies with the remote gdbserver protocol, and as such can be used
1715 to debug remote targets.
1717 @section Connecting to gdb
1718 @cindex Connecting to gdb
1719 A connection is typically started as follows:
1721 target remote localhost:3333
1723 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1725 To see a list of available openocd commands type @option{monitor help} on the
1728 Openocd supports the gdb @option{qSupported} packet, this enables information
1729 to be sent by the gdb server (openocd) to gdb. Typical information includes
1730 packet size and device memory map.
1732 Previous versions of openocd required the following gdb options to increase
1733 the packet size and speed up gdb communication.
1735 set remote memory-write-packet-size 1024
1736 set remote memory-write-packet-size fixed
1737 set remote memory-read-packet-size 1024
1738 set remote memory-read-packet-size fixed
1740 This is now handled in the @option{qSupported} PacketSize.
1742 @section Programming using gdb
1743 @cindex Programming using gdb
1745 By default the target memory map is not sent to gdb, this can be enabled by
1746 the following openocd config option:
1748 gdb_memory_map enable
1750 For this to function correctly a valid flash config must also be configured
1751 in openocd. For speed also configure a valid working area.
1753 Informing gdb of the memory map of the target will enable gdb to protect any
1754 flash area of the target and use hardware breakpoints by default. This means
1755 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1758 To view the configured memory map in gdb, use the gdb command @option{info mem}
1759 All other unasigned addresses within gdb are treated as ram.
1761 If @option{gdb_flash_program enable} is also used, gdb will be able to
1762 program any flash memory using the vFlash interface.
1764 gdb will look at the target memory map when a load command is given, if any
1765 areas to be programmed lie within the target flash area the vFlash packets
1768 Incase the target needs configuring before gdb programming, a script can be executed.
1770 target_script 0 gdb_program_config config.script
1773 To verify any flash programming the gdb command @option{compare-sections}
1780 @item OpenOCD complains about a missing cygwin1.dll
1782 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1783 claims to come with all the necessary dlls. When using Cygwin, try launching
1784 the OpenOCD from the Cygwin shell.
1786 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1787 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1788 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1790 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1791 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1792 software breakpoints consume one of the two available hardware breakpoints,
1793 and are therefor disabled by default. If your code is running from RAM, you
1794 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1795 your code resides in Flash, you can't use software breakpoints, but you can force
1796 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1798 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1799 and works sometimes fine.
1801 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1802 clock at the time you're programming the flash. If you've specified the crystal's
1803 frequency, make sure the PLL is disabled, if you've specified the full core speed
1804 (e.g. 60MHz), make sure the PLL is enabled.
1806 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1807 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1808 out while waiting for end of scan, rtck was disabled".
1810 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1811 settings in your PC Bios (ECP, EPP, and different versions of those).
1813 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1814 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1815 memory read caused data abort".
1817 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1818 beyond the last valid frame. It might be possible to prevent this by setting up
1819 a proper "initial" stack frame, if you happen to know what exactly has to
1820 be done, feel free to add this here.
1822 @item I get the following message in the OpenOCD console (or log file):
1823 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1825 This warning doesn't indicate any serious problem, as long as you don't want to
1826 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1827 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1828 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1829 independently. With this setup, it's not possible to halt the core right out of
1830 reset, everything else should work fine.
1832 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1833 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1834 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1835 quit with an error message. Is there a stability issue with OpenOCD?
1837 No, this is not a stability issue concering OpenOCD. Most users have solved
1838 this issue by simply using a self-powered USB Hub, which they connect their
1839 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1840 supply stable enough for the Amontec JTAGkey to be operated.
1842 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1843 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1844 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1845 What does that mean and what might be the reason for this?
1847 First of all, the reason might be the USB power supply. Try using a self-powered
1848 hub instead of a direct connection to your computer. Secondly, the error code 4
1849 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1850 Chip ran into some sort of error - this points us to a USB problem.
1852 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1853 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1854 What does that mean and what might be the reason for this?
1856 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1857 has closed the connection to OpenOCD. This might be a GDB issue.
1859 @item In the configuration file in the section where flash device configurations
1860 are described, there is a parameter for specifying the clock frequency for
1861 LPC2000 internal flash devices (e.g.
1862 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1863 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1864 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1865 Is it possible to specify real numbers for the clock frequency?
1867 No. The clock frequency specified here must be given as an integral number.
1868 However, this clock frequency is used by the In-Application-Programming (IAP)
1869 routines of the LPC2000 family only, which seems to be very tolerant concerning
1870 the given clock frequency, so a slight difference between the specified clock
1871 frequency and the actual clock frequency will not cause any trouble.
1873 @item Do I have to keep a specific order for the commands in the configuration file?
1875 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1876 listed for the JTAG scan chain must be given in the right order (jtag_device),
1877 with the device closest to the TDO-Pin being listed first. In general,
1878 whenever objects of the same type exist which require an index number, then
1879 these objects must be given in the right order (jtag_devices, targets and flash
1880 banks - a target references a jtag_device and a flash bank references a target).
1882 @item Sometimes my debugging session terminates with an error. When I look into the
1883 log file, I can see these error messages: Error: arm7_9_common.c:561
1884 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP