1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD
55 * Developers:: OpenOCD Developers
56 * Building OpenOCD:: Building OpenOCD From SVN
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * NAND Flash Commands:: NAND Flash Commands
69 * General Commands:: General Commands
70 * JTAG Commands:: JTAG Commands
71 * Sample Scripts:: Sample Target Scripts
73 * GDB and OpenOCD:: Using GDB and OpenOCD
74 * Tcl Scripting API:: Tcl Scripting API
75 * Upgrading:: Deprecated/Removed Commands
76 * Target Library:: Target Library
77 * FAQ:: Frequently Asked Questions
78 * Tcl Crash Course:: Tcl Crash Course
79 * License:: GNU Free Documentation License
80 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
81 @comment case issue with ``Index.html'' and ``index.html''
82 @comment Occurs when creating ``--html --no-split'' output
83 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
84 * OpenOCD Concept Index:: Concept Index
85 * OpenOCD Command Index:: Command Index
92 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
93 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
94 Since that time, the project has grown into an active open-source project,
95 supported by a diverse community of software and hardware developers from
98 @section What is OpenOCD?
100 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
101 in-system programming and boundary-scan testing for embedded target
104 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
105 with the JTAG (IEEE 1149.1) compliant taps on your target board.
107 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
108 based, parallel port based, and other standalone boxes that run
109 OpenOCD internally. @xref{JTAG Hardware Dongles}.
111 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
112 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
113 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
114 debugged via the GDB protocol.
116 @b{Flash Programing:} Flash writing is supported for external CFI
117 compatible NOR flashes (Intel and AMD/Spansion command set) and several
118 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
119 STM32x). Preliminary support for various NAND flash controllers
120 (LPC3180, Orion, S3C24xx, more) controller is included.
122 @section OpenOCD Web Site
124 The OpenOCD web site provides the latest public news from the community:
126 @uref{http://openocd.berlios.de/web/}
130 @chapter OpenOCD Developer Resources
133 If you are interested in improving the state of OpenOCD's debugging and
134 testing support, new contributions will be welcome. Motivated developers
135 can produce new target, flash or interface drivers, improve the
136 documentation, as well as more conventional bug fixes and enhancements.
138 The resources in this chapter are available for developers wishing to explore
139 or expand the OpenOCD source code.
141 @section OpenOCD Subversion Repository
143 The ``Building From Source'' section provides instructions to retrieve
144 and and build the latest version of the OpenOCD source code.
145 @xref{Building OpenOCD}.
147 Developers that want to contribute patches to the OpenOCD system are
148 @b{strongly} encouraged to base their work off of the most recent trunk
149 revision. Patches created against older versions may require additional
150 work from their submitter in order to be updated for newer releases.
152 @section Doxygen Developer Manual
154 During the development of the 0.2.0 release, the OpenOCD project began
155 providing a Doxygen reference manual. This document contains more
156 technical information about the software internals, development
157 processes, and similar documentation:
159 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
161 This document is a work-in-progress, but contributions would be welcome
162 to fill in the gaps. All of the source files are provided in-tree,
163 listed in the Doxyfile configuration in the top of the repository trunk.
165 @section OpenOCD Developer Mailing List
167 The OpenOCD Developer Mailing List provides the primary means of
168 communication between developers:
170 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
172 All drivers developers are enouraged to also subscribe to the list of
173 SVN commits to keep pace with the ongoing changes:
175 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
177 @node Building OpenOCD
178 @chapter Building OpenOCD
181 @section Pre-Built Tools
182 If you are interested in getting actual work done rather than building
183 OpenOCD, then check if your interface supplier provides binaries for
184 you. Chances are that that binary is from some SVN version that is more
185 stable than SVN trunk where bleeding edge development takes place.
187 @section Packagers Please Read!
189 You are a @b{PACKAGER} of OpenOCD if you
192 @item @b{Sell dongles} and include pre-built binaries
193 @item @b{Supply tools} i.e.: A complete development solution
194 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
195 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
198 As a @b{PACKAGER}, you will experience first reports of most issues.
199 When you fix those problems for your users, your solution may help
200 prevent hundreds (if not thousands) of other questions from other users.
202 If something does not work for you, please work to inform the OpenOCD
203 developers know how to improve the system or documentation to avoid
204 future problems, and follow-up to help us ensure the issue will be fully
205 resolved in our future releases.
207 That said, the OpenOCD developers would also like you to follow a few
211 @item @b{Always build with printer ports enabled.}
212 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
216 @item @b{Why YES to LIBFTDI + LIBUSB?}
218 @item @b{LESS} work - libusb perhaps already there
219 @item @b{LESS} work - identical code, multiple platforms
220 @item @b{MORE} dongles are supported
221 @item @b{MORE} platforms are supported
222 @item @b{MORE} complete solution
224 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
226 @item @b{LESS} speed - some say it is slower
227 @item @b{LESS} complex to distribute (external dependencies)
231 @section Building From Source
233 You can download the current SVN version with an SVN client of your choice from the
234 following repositories:
236 @uref{svn://svn.berlios.de/openocd/trunk}
240 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
242 Using the SVN command line client, you can use the following command to fetch the
243 latest version (make sure there is no (non-svn) directory called "openocd" in the
247 svn checkout svn://svn.berlios.de/openocd/trunk openocd
250 Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
251 For building on Windows,
252 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
253 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
254 paths, resulting in obscure dependency errors (This is an observation I've gathered
255 from the logs of one user - correct me if I'm wrong).
257 You further need the appropriate driver files, if you want to build support for
258 a FTDI FT2232 based interface:
261 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
262 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
263 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
264 homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
267 libftdi is supported under Windows. Do not use versions earlier than 0.14.
269 In general, the D2XX driver provides superior performance (several times as fast),
270 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
271 a kernel module, only a user space library.
273 To build OpenOCD (on both Linux and Cygwin), use the following commands:
279 Bootstrap generates the configure script, and prepares building on your system.
282 ./configure [options, see below]
285 Configure generates the Makefiles used to build OpenOCD.
292 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
294 The configure script takes several options, specifying which JTAG interfaces
295 should be included (among other things):
299 @option{--enable-parport} - Enable building the PC parallel port driver.
301 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
303 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
305 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
307 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
309 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
311 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
313 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
315 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
317 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
319 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
321 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
323 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
325 @option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
327 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
329 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
331 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
333 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
335 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
337 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
339 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
341 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
343 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
345 @option{--enable-dummy} - Enable building the dummy port driver.
348 @section Parallel Port Dongles
350 If you want to access the parallel port using the PPDEV interface you have to specify
351 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
352 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
353 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
355 The same is true for the @option{--enable-parport_giveio} option, you have to
356 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
358 @section FT2232C Based USB Dongles
360 There are 2 methods of using the FTD2232, either (1) using the
361 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
362 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
364 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
365 TAR.GZ file. You must unpack them ``some where'' convient. As of this
366 writing (12/26/2008) FTDICHIP does not supply means to install these
367 files ``in an appropriate place'' As a result, there are two
368 ``./configure'' options that help.
370 Below is an example build process:
372 1) Check out the latest version of ``openocd'' from SVN.
374 2) Download & unpack either the Windows or Linux FTD2xx drivers
375 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
378 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
379 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
382 3) Configure with these options:
385 Cygwin FTDICHIP solution:
386 ./configure --prefix=/home/duane/mytools \
387 --enable-ft2232_ftd2xx \
388 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
390 Linux FTDICHIP solution:
391 ./configure --prefix=/home/duane/mytools \
392 --enable-ft2232_ftd2xx \
393 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
395 Cygwin/Linux LIBFTDI solution:
397 1a) For Windows: The Windows port of LIBUSB is in place.
398 1b) For Linux: libusb has been built/installed and is in place.
400 2) And libftdi has been built and installed
401 Note: libftdi - relies upon libusb.
403 ./configure --prefix=/home/duane/mytools \
404 --enable-ft2232_libftdi
408 4) Then just type ``make'', and perhaps ``make install''.
411 @section Miscellaneous Configure Options
415 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
417 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
420 @option{--enable-release} - Enable building of an OpenOCD release, generally
421 this is for developers. It simply omits the svn version string when the
422 openocd @option{-v} is executed.
425 @node JTAG Hardware Dongles
426 @chapter JTAG Hardware Dongles
435 Defined: @b{dongle}: A small device that plugins into a computer and serves as
436 an adapter .... [snip]
438 In the OpenOCD case, this generally refers to @b{a small adapater} one
439 attaches to your computer via USB or the Parallel Printer Port. The
440 execption being the Zylin ZY1000 which is a small box you attach via
441 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
442 require any drivers to be installed on the developer PC. It also has
443 a built in web interface. It supports RTCK/RCLK or adaptive clocking
444 and has a built in relay to power cycle targets remotely.
447 @section Choosing a Dongle
449 There are three things you should keep in mind when choosing a dongle.
452 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
453 @item @b{Connection} Printer Ports - Does your computer have one?
454 @item @b{Connection} Is that long printer bit-bang cable practical?
455 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
458 @section Stand alone Systems
460 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
461 dongle, but a standalone box. The ZY1000 has the advantage that it does
462 not require any drivers installed on the developer PC. It also has
463 a built in web interface. It supports RTCK/RCLK or adaptive clocking
464 and has a built in relay to power cycle targets remotely.
466 @section USB FT2232 Based
468 There are many USB JTAG dongles on the market, many of them are based
469 on a chip from ``Future Technology Devices International'' (FTDI)
470 known as the FTDI FT2232.
472 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
474 As of 28/Nov/2008, the following are supported:
478 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
480 @* See: @url{http://www.amontec.com/jtagkey.shtml}
482 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
484 @* See: @url{http://www.signalyzer.com}
485 @item @b{evb_lm3s811}
486 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
487 @item @b{olimex-jtag}
488 @* See: @url{http://www.olimex.com}
490 @* See: @url{http://www.tincantools.com}
491 @item @b{turtelizer2}
492 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
494 @* Link: @url{http://www.hitex.com/index.php?id=383}
496 @* Link @url{http://www.hitex.com/stm32-stick}
497 @item @b{axm0432_jtag}
498 @* Axiom AXM-0432 Link @url{http://www.axman.com}
501 @section USB JLINK based
502 There are several OEM versions of the Segger @b{JLINK} adapter. It is
503 an example of a micro controller based JTAG adapter, it uses an
504 AT91SAM764 internally.
507 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
508 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
509 @item @b{SEGGER JLINK}
510 @* Link: @url{http://www.segger.com/jlink.html}
512 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
515 @section USB RLINK based
516 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
519 @item @b{Raisonance RLink}
520 @* Link: @url{http://www.raisonance.com/products/RLink.php}
521 @item @b{STM32 Primer}
522 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
523 @item @b{STM32 Primer2}
524 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
530 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
532 @item @b{USB - Presto}
533 @* Link: @url{http://tools.asix.net/prg_presto.htm}
535 @item @b{Versaloon-Link}
536 @* Link: @url{http://www.simonqian.com/en/Versaloon}
538 @item @b{ARM-JTAG-EW}
539 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
542 @section IBM PC Parallel Printer Port Based
544 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
545 and the MacGraigor Wiggler. There are many clones and variations of
550 @item @b{Wiggler} - There are many clones of this.
551 @* Link: @url{http://www.macraigor.com/wiggler.htm}
553 @item @b{DLC5} - From XILINX - There are many clones of this
554 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
555 produced, PDF schematics are easily found and it is easy to make.
557 @item @b{Amontec - JTAG Accelerator}
558 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
561 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
564 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
566 @item @b{Wiggler_ntrst_inverted}
567 @* Yet another variation - See the source code, src/jtag/parport.c
569 @item @b{old_amt_wiggler}
570 @* Unknown - probably not on the market today
573 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
576 @* Link: @url{http://www.amontec.com/chameleon.shtml}
582 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
585 @* From ST Microsystems, link:
586 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
587 Title: FlashLINK JTAG programing cable for PSD and uPSD
595 @* An EP93xx based Linux machine using the GPIO pins directly.
598 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
604 @cindex running OpenOCD
606 @cindex --debug_level
610 The @option{--help} option shows:
614 --help | -h display this help
615 --version | -v display OpenOCD version
616 --file | -f use configuration file <name>
617 --search | -s dir to search for config files and scripts
618 --debug | -d set debug level <0-3>
619 --log_output | -l redirect log output to file <name>
620 --command | -c run <command>
621 --pipe | -p use pipes when talking to gdb
624 By default OpenOCD reads the file configuration file ``openocd.cfg''
625 in the current directory. To specify a different (or multiple)
626 configuration file, you can use the ``-f'' option. For example:
629 openocd -f config1.cfg -f config2.cfg -f config3.cfg
632 Once started, OpenOCD runs as a daemon, waiting for connections from
633 clients (Telnet, GDB, Other).
635 If you are having problems, you can enable internal debug messages via
638 Also it is possible to interleave commands w/config scripts using the
639 @option{-c} command line switch.
641 To enable debug output (when reporting problems or working on OpenOCD
642 itself), use the @option{-d} command line switch. This sets the
643 @option{debug_level} to "3", outputting the most information,
644 including debug messages. The default setting is "2", outputting only
645 informational messages, warnings and errors. You can also change this
646 setting from within a telnet or gdb session using @option{debug_level
647 <n>} @xref{debug_level}.
649 You can redirect all output from the daemon to a file using the
650 @option{-l <logfile>} switch.
652 Search paths for config/script files can be added to OpenOCD by using
653 the @option{-s <search>} switch. The current directory and the OpenOCD
654 target library is in the search path by default.
656 For details on the @option{-p} option. @xref{Connecting to GDB}.
658 Note! OpenOCD will launch the GDB & telnet server even if it can not
659 establish a connection with the target. In general, it is possible for
660 the JTAG controller to be unresponsive until the target is set up
661 correctly via e.g. GDB monitor commands in a GDB init script.
663 @node Simple Configuration Files
664 @chapter Simple Configuration Files
665 @cindex configuration
668 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
671 @item A small openocd.cfg file which ``sources'' other configuration files
672 @item A monolithic openocd.cfg file
673 @item Many -f filename options on the command line
674 @item Your Mixed Solution
677 @section Small configuration file method
679 This is the preferred method. It is simple and works well for many
680 people. The developers of OpenOCD would encourage you to use this
681 method. If you create a new configuration please email new
682 configurations to the development list.
684 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
687 source [find interface/signalyzer.cfg]
689 # GDB can also flash my flash!
690 gdb_memory_map enable
691 gdb_flash_program enable
693 source [find target/sam7x256.cfg]
696 There are many example configuration scripts you can work with. You
697 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
701 @item @b{board} - eval board level configurations
702 @item @b{interface} - specific dongle configurations
703 @item @b{target} - the target chips
704 @item @b{tcl} - helper scripts
705 @item @b{xscale} - things specific to the xscale.
708 Look first in the ``boards'' area, then the ``targets'' area. Often a board
709 configuration is a good example to work from.
711 @section Many -f filename options
712 Some believe this is a wonderful solution, others find it painful.
714 You can use a series of ``-f filename'' options on the command line,
715 OpenOCD will read each filename in sequence, for example:
718 openocd -f file1.cfg -f file2.cfg -f file2.cfg
721 You can also intermix various commands with the ``-c'' command line
724 @section Monolithic file
725 The ``Monolithic File'' dispenses with all ``source'' statements and
726 puts everything in one self contained (monolithic) file. This is not
729 Please try to ``source'' various files or use the multiple -f
732 @section Advice for you
733 Often, one uses a ``mixed approach''. Where possible, please try to
734 ``source'' common things, and if needed cut/paste parts of the
735 standard distribution configuration files as needed.
737 @b{REMEMBER:} The ``important parts'' of your configuration file are:
740 @item @b{Interface} - Defines the dongle
741 @item @b{Taps} - Defines the JTAG Taps
742 @item @b{GDB Targets} - What GDB talks to
743 @item @b{Flash Programing} - Very Helpful
746 Some key things you should look at and understand are:
749 @item The reset configuration of your debug environment as a whole
750 @item Is there a ``work area'' that OpenOCD can use?
751 @* For ARM - work areas mean up to 10x faster downloads.
752 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
753 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
758 @node Config File Guidelines
759 @chapter Config File Guidelines
761 This section/chapter is aimed at developers and integrators of
762 OpenOCD. These are guidelines for creating new boards and new target
763 configurations as of 28/Nov/2008.
765 However, you, the user of OpenOCD, should be somewhat familiar with
766 this section as it should help explain some of the internals of what
767 you might be looking at.
769 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
773 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
775 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
776 contain initialization items that are specific to a board - for
777 example: The SDRAM initialization sequence for the board, or the type
778 of external flash and what address it is found at. Any initialization
779 sequence to enable that external flash or SDRAM should be found in the
780 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
781 a CPU and an FPGA or CPLD.
783 @* Think chip. The ``target'' directory represents a JTAG tap (or
784 chip) OpenOCD should control, not a board. Two common types of targets
785 are ARM chips and FPGA or CPLD chips.
788 @b{If needed...} The user in their ``openocd.cfg'' file or the board
789 file might override a specific feature in any of the above files by
790 setting a variable or two before sourcing the target file. Or adding
791 various commands specific to their situation.
793 @section Interface Config Files
795 The user should be able to source one of these files via a command like this:
798 source [find interface/FOOBAR.cfg]
800 openocd -f interface/FOOBAR.cfg
803 A preconfigured interface file should exist for every interface in use
804 today, that said, perhaps some interfaces have only been used by the
805 sole developer who created it.
807 @b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
808 tcl_platform(platform), it should be called jim_platform (because it
809 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
810 ``cygwin'' or ``mingw''
812 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
814 @section Board Config Files
816 @b{Note: BOARD directory NEW as of 28/nov/2008}
818 The user should be able to source one of these files via a command like this:
821 source [find board/FOOBAR.cfg]
823 openocd -f board/FOOBAR.cfg
827 The board file should contain one or more @t{source [find
828 target/FOO.cfg]} statements along with any board specific things.
830 In summary the board files should contain (if present)
833 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
834 @item SDRAM configuration (size, speed, etc.
835 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
836 @item Multiple TARGET source statements
837 @item All things that are not ``inside a chip''
838 @item Things inside a chip go in a 'target' file
841 @section Target Config Files
843 The user should be able to source one of these files via a command like this:
846 source [find target/FOOBAR.cfg]
848 openocd -f target/FOOBAR.cfg
851 In summary the target files should contain
856 @item Reset configuration
858 @item CPU/Chip/CPU-Core specific features
862 @subsection Important variable names
864 By default, the end user should never need to set these
865 variables. However, if the user needs to override a setting they only
866 need to set the variable in a simple way.
870 @* This gives a name to the overall chip, and is used as part of the
871 tap identifier dotted name.
873 @* By default little - unless the chip or board is not normally used that way.
875 @* When OpenOCD examines the JTAG chain, it will attempt to identify
876 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
877 to verify the tap id number verses configuration file and may issue an
878 error or warning like this. The hope is that this will help to pinpoint
879 problems in OpenOCD configurations.
882 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
883 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
884 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
885 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
888 @item @b{_TARGETNAME}
889 @* By convention, this variable is created by the target configuration
890 script. The board configuration file may make use of this variable to
891 configure things like a ``reset init'' script, or other things
892 specific to that board and that target.
894 If the chip has 2 targets, use the names @b{_TARGETNAME0},
895 @b{_TARGETNAME1}, ... etc.
897 @b{Remember:} The ``board file'' may include multiple targets.
899 At no time should the name ``target0'' (the default target name if
900 none was specified) be used. The name ``target0'' is a hard coded name
901 - the next target on the board will be some other number.
902 In the same way, avoid using target numbers even when they are
903 permitted; use the right target name(s) for your board.
905 The user (or board file) should reasonably be able to:
908 source [find target/FOO.cfg]
909 $_TARGETNAME configure ... FOO specific parameters
911 source [find target/BAR.cfg]
912 $_TARGETNAME configure ... BAR specific parameters
917 @subsection Tcl Variables Guide Line
918 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
920 Thus the rule we follow in OpenOCD is this: Variables that begin with
921 a leading underscore are temporary in nature, and can be modified and
922 used at will within a ?TARGET? configuration file.
924 @b{EXAMPLE:} The user should be able to do this:
928 # PXA270 #1 network side, big endian
929 # PXA270 #2 video side, little endian
933 source [find target/pxa270.cfg]
934 # variable: _TARGETNAME = network.cpu
935 # other commands can refer to the "network.cpu" tap.
936 $_TARGETNAME configure .... params for this CPU..
940 source [find target/pxa270.cfg]
941 # variable: _TARGETNAME = video.cpu
942 # other commands can refer to the "video.cpu" tap.
943 $_TARGETNAME configure .... params for this CPU..
947 source [find target/spartan3.cfg]
949 # Since $_TARGETNAME is temporal..
950 # these names still work!
951 network.cpu configure ... params
952 video.cpu configure ... params
956 @subsection Default Value Boiler Plate Code
958 All target configuration files should start with this (or a modified form)
962 if @{ [info exists CHIPNAME] @} @{
963 set _CHIPNAME $CHIPNAME
965 set _CHIPNAME sam7x256
968 if @{ [info exists ENDIAN] @} @{
974 if @{ [info exists CPUTAPID ] @} @{
975 set _CPUTAPID $CPUTAPID
977 set _CPUTAPID 0x3f0f0f0f
982 @subsection Creating Taps
983 After the ``defaults'' are choosen [see above] the taps are created.
985 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
989 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
990 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
995 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
998 @item @b{Unform tap names} - See: Tap Naming Convention
999 @item @b{_TARGETNAME} is created at the end where used.
1003 if @{ [info exists FLASHTAPID ] @} @{
1004 set _FLASHTAPID $FLASHTAPID
1006 set _FLASHTAPID 0x25966041
1008 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
1010 if @{ [info exists CPUTAPID ] @} @{
1011 set _CPUTAPID $CPUTAPID
1013 set _CPUTAPID 0x25966041
1015 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
1018 if @{ [info exists BSTAPID ] @} @{
1019 set _BSTAPID $BSTAPID
1021 set _BSTAPID 0x1457f041
1023 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
1025 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1028 @b{Tap Naming Convention}
1030 See the command ``jtag newtap'' for detail, but in brief the names you should use are:
1039 @item @b{unknownN} - it happens :-(
1042 @subsection Reset Configuration
1044 Some chips have specific ways the TRST and SRST signals are
1045 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1046 @b{BOARD SPECIFIC} they go in the board file.
1048 @subsection Work Areas
1050 Work areas are small RAM areas used by OpenOCD to speed up downloads,
1051 and to download small snippets of code to program flash chips.
1053 If the chip includes a form of ``on-chip-ram'' - and many do - define
1054 a reasonable work area and use the ``backup'' option.
1056 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
1057 inaccessible if/when the application code enables or disables the MMU.
1059 @subsection ARM Core Specific Hacks
1061 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1062 special high speed download features - enable it.
1064 If the chip has an ARM ``vector catch'' feature - by default enable
1065 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1066 user is really writing a handler for those situations - they can
1067 easily disable it. Experiance has shown the ``vector catch'' is
1068 helpful - for common programing errors.
1070 If present, the MMU, the MPU and the CACHE should be disabled.
1072 Some ARM cores are equipped with trace support, which permits
1073 examination of the instruction and data bus activity. Trace
1074 activity is controlled through an ``Embedded Trace Module'' (ETM)
1075 on one of the core's scan chains. The ETM emits voluminous data
1076 through a ``trace port''. The trace port is accessed in one
1077 of two ways. When its signals are pinned out from the chip,
1078 boards may provide a special high speed debugging connector;
1079 software support for this is not configured by default, use
1080 the ``--enable-oocd_trace'' option. Alternatively, trace data
1081 may be stored an on-chip SRAM which is packaged as an ``Embedded
1082 Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
1083 its associated ARM core. OpenOCD supports the ETM, and your
1084 target configuration should set it up with the relevant trace
1085 port: ``etb'' for chips which use that, else the board-specific
1086 option will be either ``oocd_trace'' or ``dummy''.
1089 etm config $_TARGETNAME 16 normal full etb
1090 etb config $_TARGETNAME $_CHIPNAME.etb
1093 @subsection Internal Flash Configuration
1095 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1097 @b{Never ever} in the ``target configuration file'' define any type of
1098 flash that is external to the chip. (For example a BOOT flash on
1099 Chip Select 0.) Such flash information goes in a board file - not
1100 the TARGET (chip) file.
1104 @item at91sam7x256 - has 256K flash YES enable it.
1105 @item str912 - has flash internal YES enable it.
1106 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1107 @item pxa270 - again - CS0 flash - it goes in the board file.
1111 @chapter About JIM-Tcl
1115 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1116 learn more about JIM here: @url{http://jim.berlios.de}
1119 @item @b{JIM vs. Tcl}
1120 @* JIM-TCL is a stripped down version of the well known Tcl language,
1121 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1122 fewer features. JIM-Tcl is a single .C file and a single .H file and
1123 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1124 4.2 MB .zip file containing 1540 files.
1126 @item @b{Missing Features}
1127 @* Our practice has been: Add/clone the real Tcl feature if/when
1128 needed. We welcome JIM Tcl improvements, not bloat.
1131 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1132 command interpreter today (28/nov/2008) is a mixture of (newer)
1133 JIM-Tcl commands, and (older) the orginal command interpreter.
1136 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1137 can type a Tcl for() loop, set variables, etc.
1139 @item @b{Historical Note}
1140 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1142 @item @b{Need a crash course in Tcl?}
1143 @* See: @xref{Tcl Crash Course}.
1147 @node Daemon Configuration
1148 @chapter Daemon Configuration
1149 @cindex initialization
1150 The commands here are commonly found in the openocd.cfg file and are
1151 used to specify what TCP/IP ports are used, and how GDB should be
1154 @section Configuration Stage
1155 @cindex configuration stage
1156 @cindex configuration command
1158 When the OpenOCD server process starts up, it enters a
1159 @emph{configuration stage} which is the only time that
1160 certain commands, @emph{configuration commands}, may be issued.
1161 Those configuration commands include declaration of TAPs
1162 and other basic setup.
1163 The server must leave the configuration stage before it
1164 may access or activate TAPs.
1165 After it leaves this stage, configuration commands may no
1168 @deffn {Config Command} init
1169 This command terminates the configuration stage and
1170 enters the normal command mode. This can be useful to add commands to
1171 the startup scripts and commands such as resetting the target,
1172 programming flash, etc. To reset the CPU upon startup, add "init" and
1173 "reset" at the end of the config script or at the end of the OpenOCD
1174 command line using the @option{-c} command line switch.
1176 If this command does not appear in any startup/configuration file
1177 OpenOCD executes the command for you after processing all
1178 configuration files and/or command line options.
1180 @b{NOTE:} This command normally occurs at or near the end of your
1181 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1182 targets ready. For example: If your openocd.cfg file needs to
1183 read/write memory on your target, @command{init} must occur before
1184 the memory read/write commands. This includes @command{nand probe}.
1187 @section TCP/IP Ports
1191 The OpenOCD server accepts remote commands in several syntaxes.
1192 Each syntax uses a different TCP/IP port, which you may specify
1193 only during configuration (before those ports are opened).
1195 @deffn {Command} gdb_port (number)
1197 Specify or query the first port used for incoming GDB connections.
1198 The GDB port for the
1199 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1200 When not specified during the configuration stage,
1201 the port @var{number} defaults to 3333.
1204 @deffn {Command} tcl_port (number)
1205 Specify or query the port used for a simplified RPC
1206 connection that can be used by clients to issue TCL commands and get the
1207 output from the Tcl engine.
1208 Intended as a machine interface.
1209 When not specified during the configuration stage,
1210 the port @var{number} defaults to 6666.
1213 @deffn {Command} telnet_port (number)
1214 Specify or query the
1215 port on which to listen for incoming telnet connections.
1216 This port is intended for interaction with one human through TCL commands.
1217 When not specified during the configuration stage,
1218 the port @var{number} defaults to 4444.
1221 @section GDB Configuration
1222 @anchor{GDB Configuration}
1224 @cindex GDB configuration
1225 You can reconfigure some GDB behaviors if needed.
1226 The ones listed here are static and global.
1227 @xref{Target Create}, about declaring individual targets.
1228 @xref{Target Events}, about configuring target-specific event handling.
1230 @deffn {Command} gdb_breakpoint_override <hard|soft|disable>
1231 @anchor{gdb_breakpoint_override}
1232 Force breakpoint type for gdb @command{break} commands.
1233 The raison d'etre for this option is to support GDB GUI's which don't
1234 distinguish hard versus soft breakpoints, if the default OpenOCD and
1235 GDB behaviour is not sufficient. GDB normally uses hardware
1236 breakpoints if the memory map has been set up for flash regions.
1238 This option replaces older arm7_9 target commands that addressed
1242 @deffn {Config command} gdb_detach <resume|reset|halt|nothing>
1243 Configures what OpenOCD will do when GDB detaches from the daemon.
1244 Default behaviour is @var{resume}.
1247 @deffn {Config command} gdb_flash_program <enable|disable>
1248 @anchor{gdb_flash_program}
1249 Set to @var{enable} to cause OpenOCD to program the flash memory when a
1250 vFlash packet is received.
1251 The default behaviour is @var{enable}.
1254 @deffn {Config command} gdb_memory_map <enable|disable>
1255 Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
1256 requested. GDB will then know when to set hardware breakpoints, and program flash
1257 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1258 for flash programming to work.
1259 Default behaviour is @var{enable}.
1260 @xref{gdb_flash_program}.
1263 @deffn {Config command} gdb_report_data_abort <enable|disable>
1264 Specifies whether data aborts cause an error to be reported
1265 by GDB memory read packets.
1266 The default behaviour is @var{disable};
1267 use @var{enable} see these errors reported.
1270 @node Interface - Dongle Configuration
1271 @chapter Interface - Dongle Configuration
1272 Interface commands are normally found in an interface configuration
1273 file which is sourced by your openocd.cfg file. These commands tell
1274 OpenOCD what type of JTAG dongle you have and how to talk to it.
1275 @section Simple Complete Interface Examples
1276 @b{A Turtelizer FT2232 Based JTAG Dongle}
1280 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1281 ft2232_layout turtelizer2
1282 ft2232_vid_pid 0x0403 0xbdc8
1289 @b{A Raisonance RLink}
1298 parport_cable wiggler
1303 interface arm-jtag-ew
1305 @section Interface Command
1307 The interface command tells OpenOCD what type of JTAG dongle you are
1308 using. Depending on the type of dongle, you may need to have one or
1309 more additional commands.
1313 @item @b{interface} <@var{name}>
1315 @*Use the interface driver <@var{name}> to connect to the
1316 target. Currently supported interfaces are
1321 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1323 @item @b{amt_jtagaccel}
1324 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1328 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1329 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1330 platform. The libftdi uses libusb, and should be portable to all systems that provide
1334 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1337 @* ASIX PRESTO USB JTAG programmer.
1340 @* usbprog is a freely programmable USB adapter.
1343 @* Gateworks GW16012 JTAG programmer.
1346 @* Segger jlink USB adapter
1349 @* Raisonance RLink USB adapter
1352 @* vsllink is part of Versaloon which is a versatile USB programmer.
1354 @item @b{arm-jtag-ew}
1355 @* Olimex ARM-JTAG-EW USB adapter
1356 @comment - End parameters
1358 @comment - End Interface
1360 @subsection parport options
1363 @item @b{parport_port} <@var{number}>
1364 @cindex parport_port
1365 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1366 the @file{/dev/parport} device
1368 When using PPDEV to access the parallel port, use the number of the parallel port:
1369 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1370 you may encounter a problem.
1371 @item @b{parport_cable} <@var{name}>
1372 @cindex parport_cable
1373 @*The layout of the parallel port cable used to connect to the target.
1374 Currently supported cables are
1378 The original Wiggler layout, also supported by several clones, such
1379 as the Olimex ARM-JTAG
1382 Same as original wiggler except an led is fitted on D5.
1383 @item @b{wiggler_ntrst_inverted}
1384 @cindex wiggler_ntrst_inverted
1385 Same as original wiggler except TRST is inverted.
1386 @item @b{old_amt_wiggler}
1387 @cindex old_amt_wiggler
1388 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1389 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1392 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1393 program the Chameleon itself, not a connected target.
1396 The Xilinx Parallel cable III.
1399 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1400 This is also the layout used by the HollyGates design
1401 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1404 The ST Parallel cable.
1407 Same as original wiggler except SRST and TRST connections reversed and
1408 TRST is also inverted.
1411 Altium Universal JTAG cable.
1413 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1414 @cindex parport_write_on_exit
1415 @*This will configure the parallel driver to write a known value to the parallel
1416 interface on exiting OpenOCD
1419 @subsection amt_jtagaccel options
1421 @item @b{parport_port} <@var{number}>
1422 @cindex parport_port
1423 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1424 @file{/dev/parport} device
1426 @subsection ft2232 options
1429 @item @b{ft2232_device_desc} <@var{description}>
1430 @cindex ft2232_device_desc
1431 @*The USB device description of the FTDI FT2232 device. If not
1432 specified, the FTDI default value is used. This setting is only valid
1433 if compiled with FTD2XX support.
1435 @b{TODO:} Confirm the following: On Windows the name needs to end with
1436 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1437 this be added and when must it not be added? Why can't the code in the
1438 interface or in OpenOCD automatically add this if needed? -- Duane.
1440 @item @b{ft2232_serial} <@var{serial-number}>
1441 @cindex ft2232_serial
1442 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1444 @item @b{ft2232_layout} <@var{name}>
1445 @cindex ft2232_layout
1446 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1447 signals. Valid layouts are
1450 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1452 Amontec JTAGkey and JTAGkey-Tiny
1453 @item @b{signalyzer}
1455 @item @b{olimex-jtag}
1458 American Microsystems M5960
1459 @item @b{evb_lm3s811}
1460 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1461 SRST signals on external connector
1464 @item @b{stm32stick}
1465 Hitex STM32 Performance Stick
1466 @item @b{flyswatter}
1467 Tin Can Tools Flyswatter
1468 @item @b{turtelizer2}
1469 egnite Software turtelizer2
1472 @item @b{axm0432_jtag}
1476 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1477 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1478 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1480 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1482 @item @b{ft2232_latency} <@var{ms}>
1483 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1484 ft2232_read() fails to return the expected number of bytes. This can be caused by
1485 USB communication delays and has proved hard to reproduce and debug. Setting the
1486 FT2232 latency timer to a larger value increases delays for short USB packets but it
1487 also reduces the risk of timeouts before receiving the expected number of bytes.
1488 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1491 @subsection ep93xx options
1492 @cindex ep93xx options
1493 Currently, there are no options available for the ep93xx interface.
1497 JTAG clock setup is part of system setup.
1498 It @emph{does not belong with interface setup} since any interface
1499 only knows a few of the constraints for the JTAG clock speed.
1500 Sometimes the JTAG speed is
1501 changed during the target initialization process: (1) slow at
1502 reset, (2) program the CPU clocks, (3) run fast.
1503 Both the "slow" and "fast" clock rates are functions of the
1504 oscillators used, the chip, the board design, and sometimes
1505 power management software that may be active.
1507 The speed used during reset can be adjusted using pre_reset
1508 and post_reset event handlers.
1509 @xref{Target Events}.
1511 If your system supports adaptive clocking (RTCK), configuring
1512 JTAG to use that is probably the most robust approach.
1513 However, it introduces delays to synchronize clocks; so it
1514 may not be the fastest solution.
1516 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1517 instead of @command{jtag_khz}.
1519 @deffn {Command} jtag_khz max_speed_kHz
1520 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1521 JTAG interfaces usually support a limited number of
1522 speeds. The speed actually used won't be faster
1523 than the speed specified.
1525 As a rule of thumb, if you specify a clock rate make
1526 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1527 This is especially true for synthesized cores (ARMxxx-S).
1529 Speed 0 (khz) selects RTCK method.
1531 If your system uses RTCK, you won't need to change the
1532 JTAG clocking after setup.
1533 Not all interfaces, boards, or targets support ``rtck''.
1534 If the interface device can not
1535 support it, an error is returned when you try to use RTCK.
1538 @defun jtag_rclk fallback_speed_kHz
1540 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
1541 If that fails (maybe the interface, board, or target doesn't
1542 support it), falls back to the specified frequency.
1544 # Fall back to 3mhz if RTCK is not supported
1549 @node Reset Configuration
1550 @chapter Reset Configuration
1551 @cindex Reset Configuration
1553 Every system configuration may require a different reset
1554 configuration. This can also be quite confusing. Please see the
1555 various board files for example.
1557 @section jtag_nsrst_delay <@var{ms}>
1558 @cindex jtag_nsrst_delay
1559 @*How long (in milliseconds) OpenOCD should wait after deasserting
1560 nSRST before starting new JTAG operations.
1562 @section jtag_ntrst_delay <@var{ms}>
1563 @cindex jtag_ntrst_delay
1564 @*Same @b{jtag_nsrst_delay}, but for nTRST
1566 The jtag_n[st]rst_delay options are useful if reset circuitry (like a
1567 big resistor/capacitor, reset supervisor, or on-chip features). This
1568 keeps the signal asserted for some time after the external reset got
1571 @section reset_config
1573 @b{Note:} To maintainers and integrators: Where exactly the
1574 ``reset configuration'' goes is a good question. It touches several
1575 things at once. In the end, if you have a board file - the board file
1576 should define it and assume 100% that the DONGLE supports
1577 anything. However, that does not mean the target should not also make
1578 not of something the silicon vendor has done inside the
1579 chip. @i{Grr.... nothing is every pretty.}
1583 @item Every JTAG Dongle is slightly different, some dongles implement reset differently.
1584 @item Every board is also slightly different; some boards tie TRST and SRST together.
1585 @item Every chip is slightly different; some chips internally tie the two signals together.
1586 @item Some may not implement all of the signals the same way.
1587 @item Some signals might be push-pull, others open-drain/collector.
1589 @b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
1590 reset the TAP via TRST and send commands through the JTAG tap to halt
1591 the CPU at the reset vector before the 1st instruction is executed,
1592 and finally release the SRST signal.
1593 @*Depending on your board vendor, chip vendor, etc., these
1594 signals may have slightly different names.
1596 OpenOCD defines these signals in these terms:
1598 @item @b{TRST} - is Tap Reset - and should reset only the TAP.
1599 @item @b{SRST} - is System Reset - typically equal to a reset push button.
1605 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
1606 @cindex reset_config
1607 @* The @t{reset_config} command tells OpenOCD the reset configuration
1608 of your combination of Dongle, Board, and Chips.
1609 If the JTAG interface provides SRST, but the target doesn't connect
1610 that signal properly, then OpenOCD can't use it. <@var{signals}> can
1611 be @option{none}, @option{trst_only}, @option{srst_only} or
1612 @option{trst_and_srst}.
1614 [@var{combination}] is an optional value specifying broken reset
1615 signal implementations. @option{srst_pulls_trst} states that the
1616 test logic is reset together with the reset of the system (e.g. Philips
1617 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1618 the system is reset together with the test logic (only hypothetical, I
1619 haven't seen hardware with such a bug, and can be worked around).
1620 @option{combined} implies both @option{srst_pulls_trst} and
1621 @option{trst_pulls_srst}. The default behaviour if no option given is
1624 The [@var{trst_type}] and [@var{srst_type}] parameters allow the
1625 driver type of the reset lines to be specified. Possible values are
1626 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1627 test reset signal, and @option{srst_open_drain} (default) and
1628 @option{srst_push_pull} for the system reset. These values only affect
1629 JTAG interfaces with support for different drivers, like the Amontec
1630 JTAGkey and JTAGAccelerator.
1632 @comment - end command
1638 @chapter Tap Creation
1639 @cindex tap creation
1640 @cindex tap configuration
1642 In order for OpenOCD to control a target, a JTAG tap must be
1645 Commands to create taps are normally found in a configuration file and
1646 are not normally typed by a human.
1648 When a tap is created a @b{dotted.name} is created for the tap. Other
1649 commands use that dotted.name to manipulate or refer to the tap.
1653 @item @b{Debug Target} A tap can be used by a GDB debug target
1654 @item @b{Flash Programing} Some chips program the flash directly via JTAG,
1655 instead of indirectly by making a CPU do it.
1656 @item @b{Boundry Scan} Some chips support boundary scan.
1660 @section jtag newtap
1661 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1666 @cindex tap geometry
1668 @comment START options
1671 @* is a symbolic name of the chip.
1673 @* is a symbol name of a tap present on the chip.
1674 @item @b{Required configparams}
1675 @* Every tap has 3 required configparams, and several ``optional
1676 parameters'', the required parameters are:
1677 @comment START REQUIRED
1679 @item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
1680 @item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
1681 @item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
1682 some devices, there are bits in the IR that aren't used. This lets you mask
1683 them off when doing comparisons. In general, this should just be all ones for
1685 @comment END REQUIRED
1687 An example of a FOOBAR Tap
1689 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1691 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1692 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1693 [6,4,2,0] are checked.
1695 @item @b{Optional configparams}
1696 @comment START Optional
1698 @item @b{-expected-id NUMBER}
1699 @* By default it is zero. If non-zero represents the
1700 expected tap ID used when the JTAG chain is examined. Repeat
1701 the option as many times as required if multiple id's can be
1702 expected. See below.
1705 @* By default not specified the tap is enabled. Some chips have a
1706 JTAG route controller (JRC) that is used to enable and/or disable
1707 specific JTAG taps. You can later enable or disable any JTAG tap via
1708 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1710 @comment END Optional
1713 @comment END OPTIONS
1716 @comment START NOTES
1718 @item @b{Technically}
1719 @* newtap is a sub command of the ``jtag'' command
1720 @item @b{Big Picture Background}
1721 @*GDB Talks to OpenOCD using the GDB protocol via
1722 TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
1723 control the JTAG chain on your board. Your board has one or more chips
1724 in a @i{daisy chain configuration}. Each chip may have one or more
1725 JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
1726 @item @b{NAME Rules}
1727 @*Names follow ``C'' symbol name rules (start with alpha ...)
1728 @item @b{TAPNAME - Conventions}
1730 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1731 @item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1732 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1733 @item @b{bs} - for boundary scan if this is a seperate tap.
1734 @item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
1735 @item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
1736 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1737 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1738 @item @b{When in doubt} - use the chip maker's name in their data sheet.
1740 @item @b{DOTTED.NAME}
1741 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1742 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1743 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1744 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1745 numerous other places to refer to various taps.
1747 @* The order this command appears via the config files is
1749 @item @b{Multi Tap Example}
1750 @* This example is based on the ST Microsystems STR912. See the ST
1751 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1752 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1754 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1755 @*@b{checked: 28/nov/2008}
1757 The diagram shows that the TDO pin connects to the flash tap, flash TDI
1758 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1759 tap which then connects to the TDI pin.
1763 # create tap: 'str912.flash'
1764 jtag newtap str912 flash ... params ...
1765 # create tap: 'str912.cpu'
1766 jtag newtap str912 cpu ... params ...
1767 # create tap: 'str912.bs'
1768 jtag newtap str912 bs ... params ...
1771 @item @b{Note: Deprecated} - Index Numbers
1772 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1773 feature is still present, however its use is highly discouraged and
1774 should not be counted upon. Update all of your scripts to use
1775 TAP names rather than numbers.
1776 @item @b{Multiple chips}
1777 @* If your board has multiple chips, you should be
1778 able to @b{source} two configuration files, in the proper order, and
1779 have the taps created in the proper order.
1782 @comment at command level
1783 @comment DOCUMENT old command
1784 @section jtag_device - REMOVED
1786 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1790 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1791 by the ``jtag newtap'' command. The documentation remains here so that
1792 one can easily convert the old syntax to the new syntax. About the old
1793 syntax: The old syntax is positional, i.e.: The 3rd parameter is the
1794 ``irmask''. The new syntax requires named prefixes, and supports
1795 additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
1796 @b{jtag newtap} command for details.
1798 OLD: jtag_device 8 0x01 0xe3 0xfe
1799 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
1802 @section Enable/Disable Taps
1803 @b{Note:} These commands are intended to be used as a machine/script
1804 interface. Humans might find the ``scan_chain'' command more helpful
1805 when querying the state of the JTAG taps.
1807 @b{By default, all taps are enabled}
1810 @item @b{jtag tapenable} @var{DOTTED.NAME}
1811 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1812 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1817 @cindex route controller
1819 These commands are used when your target has a JTAG route controller
1820 that effectively adds or removes a tap from the JTAG chain in a
1823 The ``standard way'' to remove a tap would be to place the tap in
1824 bypass mode. But with the advent of modern chips, this is not always a
1825 good solution. Some taps operate slowly, others operate fast, and
1826 there are other JTAG clock synchronisation problems one must face. To
1827 solve that problem, the JTAG route controller was introduced. Rather
1828 than ``bypass'' the tap, the tap is completely removed from the
1829 circuit and skipped.
1832 From OpenOCD's point of view, a JTAG tap is in one of 3 states:
1835 @item @b{Enabled - Not In ByPass} and has a variable bit length
1836 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1837 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1840 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1841 @b{Historical note:} this feature was added 28/nov/2008
1843 @b{jtag tapisenabled DOTTED.NAME}
1845 This command returns 1 if the named tap is currently enabled, 0 if not.
1846 This command exists so that scripts that manipulate a JRC (like the
1847 OMAP3530 has) can determine if OpenOCD thinks a tap is presently
1848 enabled or disabled.
1851 @node Target Configuration
1852 @chapter Target Configuration
1855 This chapter discusses how to create a GDB debug target. Before
1856 creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
1858 @section targets [NAME]
1859 @b{Note:} This command name is PLURAL - not singular.
1861 With NO parameter, this plural @b{targets} command lists all known
1862 targets in a human friendly form.
1864 With a parameter, this plural @b{targets} command sets the current
1865 target to the given name. (i.e.: If there are multiple debug targets)
1870 CmdName Type Endian ChainPos State
1871 -- ---------- ---------- ---------- -------- ----------
1872 0: target0 arm7tdmi little 0 halted
1875 @section target COMMANDS
1876 @b{Note:} This command name is SINGULAR - not plural. It is used to
1877 manipulate specific targets, to create targets and other things.
1879 Once a target is created, a TARGETNAME (object) command is created;
1880 see below for details.
1882 The TARGET command accepts these sub-commands:
1884 @item @b{create} .. parameters ..
1885 @* creates a new target, see below for details.
1887 @* Lists all supported target types (perhaps some are not yet in this document).
1889 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1891 foreach t [target names] {
1892 puts [format "Target: %s\n" $t]
1896 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1897 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1898 @item @b{number} @b{NUMBER}
1899 @* Internally OpenOCD maintains a list of targets - in numerical index
1900 (0..N-1) this command returns the name of the target at index N.
1903 set thename [target number $x]
1904 puts [format "Target %d is: %s\n" $x $thename]
1907 @* Returns the number of targets known to OpenOCD (see number above)
1910 set c [target count]
1911 for { set x 0 } { $x < $c } { incr x } {
1912 # Assuming you have created this function
1913 print_target_details $x
1919 @section TARGETNAME (object) commands
1920 @b{Use:} Once a target is created, an ``object name'' that represents the
1921 target is created. By convention, the target name is identical to the
1922 tap name. In a multiple target system, one can preceed many common
1923 commands with a specific target name and effect only that target.
1925 str912.cpu mww 0x1234 0x42
1926 omap3530.cpu mww 0x5555 123
1929 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1930 good example is a on screen button, once a button is created a button
1931 has a name (a path in Tk terms) and that name is useable as a 1st
1932 class command. For example in Tk, one can create a button and later
1933 configure it like this:
1937 button .foobar -background red -command @{ foo @}
1939 .foobar configure -foreground blue
1941 set x [.foobar cget -background]
1943 puts [format "The button is %s" $x]
1946 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
1947 button. Commands available as a ``target object'' are:
1949 @comment START targetobj commands.
1951 @item @b{configure} - configure the target; see Target Config/Cget Options below
1952 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
1953 @item @b{curstate} - current target state (running, halt, etc.
1955 @* Intended for a human to see/read the currently configure target events.
1956 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
1957 @comment start memory
1967 @item @b{Memory To Array, Array To Memory}
1968 @* These are aimed at a machine interface to memory
1970 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
1971 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
1973 @* @b{ARRAYNAME} is the name of an array variable
1974 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
1975 @* @b{ADDRESS} is the target memory address
1976 @* @b{COUNT} is the number of elements to process
1978 @item @b{Used during ``reset''}
1979 @* These commands are used internally by the OpenOCD scripts to deal
1980 with odd reset situations and are not documented here.
1982 @item @b{arp_examine}
1986 @item @b{arp_waitstate}
1988 @item @b{invoke-event} @b{EVENT-NAME}
1989 @* Invokes the specific event manually for the target
1992 @section Target Events
1994 @anchor{Target Events}
1995 At various times, certain things can happen, or you want them to happen.
1999 @item What should happen when GDB connects? Should your target reset?
2000 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2001 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
2004 All of the above items are handled by target events.
2006 To specify an event action, either during target creation, or later
2007 via ``$_TARGETNAME configure'' see this example.
2009 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
2010 target event name, and BODY is a Tcl procedure or string of commands
2013 The programmers model is the ``-command'' option used in Tcl/Tk
2014 buttons and events. Below are two identical examples, the first
2015 creates and invokes small procedure. The second inlines the procedure.
2018 proc my_attach_proc @{ @} @{
2022 mychip.cpu configure -event gdb-attach my_attach_proc
2023 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
2026 @section Current Events
2027 The following events are available:
2029 @item @b{debug-halted}
2030 @* The target has halted for debug reasons (i.e.: breakpoint)
2031 @item @b{debug-resumed}
2032 @* The target has resumed (i.e.: gdb said run)
2033 @item @b{early-halted}
2034 @* Occurs early in the halt process
2035 @item @b{examine-end}
2036 @* Currently not used (goal: when JTAG examine completes)
2037 @item @b{examine-start}
2038 @* Currently not used (goal: when JTAG examine starts)
2039 @item @b{gdb-attach}
2040 @* When GDB connects
2041 @item @b{gdb-detach}
2042 @* When GDB disconnects
2044 @* When the taret has halted and GDB is not doing anything (see early halt)
2045 @item @b{gdb-flash-erase-start}
2046 @* Before the GDB flash process tries to erase the flash
2047 @item @b{gdb-flash-erase-end}
2048 @* After the GDB flash process has finished erasing the flash
2049 @item @b{gdb-flash-write-start}
2050 @* Before GDB writes to the flash
2051 @item @b{gdb-flash-write-end}
2052 @* After GDB writes to the flash
2054 @* Before the taret steps, gdb is trying to start/resume the target
2056 @* The target has halted
2057 @item @b{old-gdb_program_config}
2058 @* DO NOT USE THIS: Used internally
2059 @item @b{old-pre_resume}
2060 @* DO NOT USE THIS: Used internally
2061 @item @b{reset-assert-pre}
2062 @* Before reset is asserted on the tap.
2063 @item @b{reset-assert-post}
2064 @* Reset is now asserted on the tap.
2065 @item @b{reset-deassert-pre}
2066 @* Reset is about to be released on the tap
2067 @item @b{reset-deassert-post}
2068 @* Reset has been released on the tap
2070 @* Currently not used.
2071 @item @b{reset-halt-post}
2072 @* Currently not usd
2073 @item @b{reset-halt-pre}
2074 @* Currently not used
2075 @item @b{reset-init}
2076 @* Used by @b{reset init} command for board-specific initialization.
2077 This is where you would configure PLLs and clocking, set up DRAM so
2078 you can download programs that don't fit in on-chip SRAM, set up pin
2079 multiplexing, and so on.
2080 @item @b{reset-start}
2081 @* Currently not used
2082 @item @b{reset-wait-pos}
2083 @* Currently not used
2084 @item @b{reset-wait-pre}
2085 @* Currently not used
2086 @item @b{resume-start}
2087 @* Before any target is resumed
2088 @item @b{resume-end}
2089 @* After all targets have resumed
2093 @* Target has resumed
2094 @item @b{tap-enable}
2095 @* Executed by @b{jtag tapenable DOTTED.NAME} command. Example:
2097 jtag configure DOTTED.NAME -event tap-enable @{
2102 @item @b{tap-disable}
2103 @*Executed by @b{jtag tapdisable DOTTED.NAME} command. Example:
2105 jtag configure DOTTED.NAME -event tap-disable @{
2106 puts "Disabling CPU"
2112 @section Target Create
2113 @anchor{Target Create}
2115 @cindex target creation
2118 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2120 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2121 @comment START params
2124 @* Is the name of the debug target. By convention it should be the tap
2125 DOTTED.NAME. This name is also used to create the target object
2126 command, and in other places the target needs to be identified.
2128 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2129 @comment START types
2146 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2147 @comment START mandatory
2149 @item @b{-endian big|little}
2150 @item @b{-chain-position DOTTED.NAME}
2151 @comment end MANDATORY
2156 @section Target Config/Cget Options
2157 These options can be specified when the target is created, or later
2158 via the configure option or to query the target via cget.
2160 You should specify a working area if you can; typically it uses some
2161 on-chip SRAM. Such a working area can speed up many things, including bulk
2162 writes to target memory; flash operations like checking to see if memory needs
2163 to be erased; GDB memory checksumming; and may help perform otherwise
2164 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2166 @item @b{-type} - returns the target type
2167 @item @b{-event NAME BODY} see Target events
2168 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2169 which will be used when an MMU is active.
2170 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2171 which will be used when an MMU is inactive.
2172 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2173 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2174 by default, it doesn't. When possible, use a working_area that doesn't
2175 need to be backed up, since performing a backup slows down operations.
2176 @item @b{-endian [big|little]}
2177 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2178 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2182 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2183 set name [target number $x]
2184 set y [$name cget -endian]
2185 set z [$name cget -type]
2186 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2190 @section Target Variants
2193 @* Unknown (please write me)
2195 @* Unknown (please write me) (similar to arm7tdmi)
2197 @* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
2198 This enables the hardware single-stepping support found on these
2203 @* None (this is also used as the ARM946)
2205 @* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
2206 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
2207 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
2208 be detected and the normal reset behaviour used.
2210 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
2212 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
2214 @* Use variant @option{ejtag_srst} when debugging targets that do not
2215 provide a functional SRST line on the EJTAG connector. This causes
2216 OpenOCD to instead use an EJTAG software reset command to reset the
2217 processor. You still need to enable @option{srst} on the reset
2218 configuration command to enable OpenOCD hardware reset functionality.
2219 @comment END variants
2221 @section working_area - Command Removed
2222 @cindex working_area
2223 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
2224 @* This documentation remains because there are existing scripts that
2225 still use this that need to be converted.
2227 working_area target# address size backup| [virtualaddress]
2229 @* The target# is a the 0 based target numerical index.
2231 @node Flash Configuration
2232 @chapter Flash programming
2233 @cindex Flash Configuration
2235 OpenOCD has different commands for NOR and NAND flash;
2236 the ``flash'' command works with NOR flash, while
2237 the ``nand'' command works with NAND flash.
2238 This partially reflects different hardware technologies:
2239 NOR flash usually supports direct CPU instruction and data bus access,
2240 while data from a NAND flash must be copied to memory before it can be
2241 used. (SPI flash must also be copied to memory before use.)
2242 However, the documentation also uses ``flash'' as a generic term;
2243 for example, ``Put flash configuration in board-specific files''.
2245 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
2246 flash that a micro may boot from. Perhaps you, the reader, would like to
2247 contribute support for this.
2251 @item Configure via the command @b{flash bank}
2252 @* Normally this is done in a configuration file.
2253 @item Operate on the flash via @b{flash SOMECOMMAND}
2254 @* Often commands to manipulate the flash are typed by a human, or run
2255 via a script in some automated way. For example: To program the boot
2256 flash on your board.
2258 @* Flashing via GDB requires the flash be configured via ``flash
2259 bank'', and the GDB flash features be enabled.
2260 @xref{GDB Configuration}.
2263 @section Flash commands
2264 @cindex Flash commands
2265 @subsection flash banks
2268 @*List configured flash banks
2269 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
2270 @subsection flash info
2271 @b{flash info} <@var{num}>
2273 @*Print info about flash bank <@option{num}>
2274 @subsection flash probe
2275 @b{flash probe} <@var{num}>
2277 @*Identify the flash, or validate the parameters of the configured flash. Operation
2278 depends on the flash type.
2279 @subsection flash erase_check
2280 @b{flash erase_check} <@var{num}>
2281 @cindex flash erase_check
2282 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
2283 updates the erase state information displayed by @option{flash info}. That means you have
2284 to issue an @option{erase_check} command after erasing or programming the device to get
2285 updated information.
2286 @subsection flash protect_check
2287 @b{flash protect_check} <@var{num}>
2288 @cindex flash protect_check
2289 @*Check protection state of sectors in flash bank <num>.
2290 @option{flash erase_sector} using the same syntax.
2291 @subsection flash erase_sector
2292 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
2293 @cindex flash erase_sector
2294 @anchor{flash erase_sector}
2295 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
2296 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
2297 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
2299 @subsection flash erase_address
2300 @b{flash erase_address} <@var{address}> <@var{length}>
2301 @cindex flash erase_address
2302 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
2303 @subsection flash write_bank
2304 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
2305 @cindex flash write_bank
2306 @anchor{flash write_bank}
2307 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
2308 <@option{offset}> bytes from the beginning of the bank.
2309 @subsection flash write_image
2310 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
2311 @cindex flash write_image
2312 @anchor{flash write_image}
2313 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
2314 [@var{offset}] can be specified and the file [@var{type}] can be specified
2315 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
2316 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
2317 if the @option{erase} parameter is given.
2318 @subsection flash protect
2319 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
2320 @cindex flash protect
2321 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
2322 <@var{last}> of @option{flash bank} <@var{num}>.
2324 @subsection mFlash commands
2325 @cindex mFlash commands
2327 @item @b{mflash probe}
2328 @cindex mflash probe
2330 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2331 @cindex mflash write
2332 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2333 <@var{offset}> bytes from the beginning of the bank.
2334 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2336 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2340 @section flash bank command
2341 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2344 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2345 <@var{bus_width}> <@var{target}> [@var{driver_options ...}]
2348 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2349 and <@var{bus_width}> bytes using the selected flash <driver>.
2351 @subsection External Flash - cfi options
2353 CFI flashes are external flash chips - often they are connected to a
2354 specific chip select on the CPU. By default, at hard reset, most
2355 CPUs have the ablity to ``boot'' from some flash chip - typically
2356 attached to the CPU's CS0 pin.
2358 For other chip selects: OpenOCD does not know how to configure, or
2359 access a specific chip select. Instead you, the human, might need to
2360 configure additional chip selects via other commands (like: mww) , or
2361 perhaps configure a GPIO pin that controls the ``write protect'' pin
2364 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2365 <@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
2366 @*CFI flashes require the name or number of the target they're connected to
2368 argument. The CFI driver makes use of a working area (specified for the target)
2369 to significantly speed up operation.
2371 @var{chip_width} and @var{bus_width} are specified in bytes.
2373 The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
2377 @subsection Internal Flash (Microcontrollers)
2378 @subsubsection lpc2000 options
2379 @cindex lpc2000 options
2381 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2382 <@var{clock}> [@var{calc_checksum}]
2383 @*LPC flashes don't require the chip and bus width to be specified. Additional
2384 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2385 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
2386 the name or number of the target this flash belongs to (first is 0),
2387 the frequency at which the core
2388 is currently running (in kHz - must be an integral number), and the optional keyword
2389 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2393 @subsubsection at91sam7 options
2394 @cindex at91sam7 options
2396 @b{flash bank at91sam7} 0 0 0 0 <@var{target}>
2397 @*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
2398 reading the chip-id and type.
2400 @subsubsection str7 options
2401 @cindex str7 options
2403 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2404 @*variant can be either STR71x, STR73x or STR75x.
2406 @subsubsection str9 options
2407 @cindex str9 options
2409 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2410 @*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
2412 str9x flash_config 0 4 2 0 0x80000
2414 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2416 @subsubsection str9 options (str9xpec driver)
2418 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2419 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2420 @option{enable_turbo} <@var{num>.}
2422 Only use this driver for locking/unlocking the device or configuring the option bytes.
2423 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2425 @subsubsection Stellaris (LM3Sxxx) options
2426 @cindex Stellaris (LM3Sxxx) options
2428 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
2429 @*Stellaris flash plugin only require the @var{target}.
2431 @subsubsection stm32x options
2432 @cindex stm32x options
2434 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2435 @*stm32x flash plugin only require the @var{target}.
2437 @subsubsection aduc702x options
2438 @cindex aduc702x options
2440 @b{flash bank aduc702x} 0 0 0 0 <@var{target}>
2441 @*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
2443 @subsection mFlash Configuration
2444 @cindex mFlash Configuration
2445 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2446 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
2448 @*Configures a mflash for <@var{soc}> host bank at
2449 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2450 order. Pin number format is dependent on host GPIO calling convention.
2451 If WP or DPD pin was not used, write -1. Currently, mflash bank
2452 support s3c2440 and pxa270.
2454 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2456 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2458 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2460 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2463 @section Microcontroller specific Flash Commands
2465 @subsection AT91SAM7 specific commands
2466 @cindex AT91SAM7 specific commands
2467 The flash configuration is deduced from the chip identification register. The flash
2468 controller handles erases automatically on a page (128/265 byte) basis, so erase is
2469 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2470 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2471 that can be erased separatly. Only an EraseAll command is supported by the controller
2472 for each flash plane and this is called with
2474 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2475 @*bulk erase flash planes first_plane to last_plane.
2476 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2477 @cindex at91sam7 gpnvm
2478 @*set or clear a gpnvm bit for the processor
2481 @subsection STR9 specific commands
2482 @cindex STR9 specific commands
2483 @anchor{STR9 specific commands}
2484 These are flash specific commands when using the str9xpec driver.
2486 @item @b{str9xpec enable_turbo} <@var{num}>
2487 @cindex str9xpec enable_turbo
2488 @*enable turbo mode, will simply remove the str9 from the chain and talk
2489 directly to the embedded flash controller.
2490 @item @b{str9xpec disable_turbo} <@var{num}>
2491 @cindex str9xpec disable_turbo
2492 @*restore the str9 into JTAG chain.
2493 @item @b{str9xpec lock} <@var{num}>
2494 @cindex str9xpec lock
2495 @*lock str9 device. The str9 will only respond to an unlock command that will
2497 @item @b{str9xpec unlock} <@var{num}>
2498 @cindex str9xpec unlock
2499 @*unlock str9 device.
2500 @item @b{str9xpec options_read} <@var{num}>
2501 @cindex str9xpec options_read
2502 @*read str9 option bytes.
2503 @item @b{str9xpec options_write} <@var{num}>
2504 @cindex str9xpec options_write
2505 @*write str9 option bytes.
2508 Note: Before using the str9xpec driver here is some background info to help
2509 you better understand how the drivers works. OpenOCD has two flash drivers for
2513 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2514 flash programming as it is faster than the @option{str9xpec} driver.
2516 Direct programming @option{str9xpec} using the flash controller. This is an
2517 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2518 core does not need to be running to program using this flash driver. Typical use
2519 for this driver is locking/unlocking the target and programming the option bytes.
2522 Before we run any commands using the @option{str9xpec} driver we must first disable
2523 the str9 core. This example assumes the @option{str9xpec} driver has been
2524 configured for flash bank 0.
2526 # assert srst, we do not want core running
2527 # while accessing str9xpec flash driver
2529 # turn off target polling
2532 str9xpec enable_turbo 0
2534 str9xpec options_read 0
2535 # re-enable str9 core
2536 str9xpec disable_turbo 0
2540 The above example will read the str9 option bytes.
2541 When performing a unlock remember that you will not be able to halt the str9 - it
2542 has been locked. Halting the core is not required for the @option{str9xpec} driver
2543 as mentioned above, just issue the commands above manually or from a telnet prompt.
2545 @subsection STR9 configuration
2546 @cindex STR9 configuration
2548 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2549 <@var{BBADR}> <@var{NBBADR}>
2550 @cindex str9x flash_config
2551 @*Configure str9 flash controller.
2553 e.g. str9x flash_config 0 4 2 0 0x80000
2555 BBSR - Boot Bank Size register
2556 NBBSR - Non Boot Bank Size register
2557 BBADR - Boot Bank Start Address register
2558 NBBADR - Boot Bank Start Address register
2562 @subsection STR9 option byte configuration
2563 @cindex STR9 option byte configuration
2565 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2566 @cindex str9xpec options_cmap
2567 @*configure str9 boot bank.
2568 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2569 @cindex str9xpec options_lvdthd
2570 @*configure str9 lvd threshold.
2571 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2572 @cindex str9xpec options_lvdsel
2573 @*configure str9 lvd source.
2574 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2575 @cindex str9xpec options_lvdwarn
2576 @*configure str9 lvd reset warning source.
2579 @subsection STM32x specific commands
2580 @cindex STM32x specific commands
2582 These are flash specific commands when using the stm32x driver.
2584 @item @b{stm32x lock} <@var{num}>
2586 @*lock stm32 device.
2587 @item @b{stm32x unlock} <@var{num}>
2588 @cindex stm32x unlock
2589 @*unlock stm32 device.
2590 @item @b{stm32x options_read} <@var{num}>
2591 @cindex stm32x options_read
2592 @*read stm32 option bytes.
2593 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2594 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2595 @cindex stm32x options_write
2596 @*write stm32 option bytes.
2597 @item @b{stm32x mass_erase} <@var{num}>
2598 @cindex stm32x mass_erase
2599 @*mass erase flash memory.
2602 @subsection Stellaris specific commands
2603 @cindex Stellaris specific commands
2605 These are flash specific commands when using the Stellaris driver.
2607 @item @b{stellaris mass_erase} <@var{num}>
2608 @cindex stellaris mass_erase
2609 @*mass erase flash memory.
2612 @node NAND Flash Commands
2613 @chapter NAND Flash Commands
2616 Compared to NOR or SPI flash, NAND devices are inexpensive
2617 and high density. Today's NAND chips, and multi-chip modules,
2618 commonly hold multiple GigaBytes of data.
2620 NAND chips consist of a number of ``erase blocks'' of a given
2621 size (such as 128 KBytes), each of which is divided into a
2622 number of pages (of perhaps 512 or 2048 bytes each). Each
2623 page of a NAND flash has an ``out of band'' (OOB) area to hold
2624 Error Correcting Code (ECC) and other metadata, usually 16 bytes
2625 of OOB for every 512 bytes of page data.
2627 One key characteristic of NAND flash is that its error rate
2628 is higher than that of NOR flash. In normal operation, that
2629 ECC is used to correct and detect errors. However, NAND
2630 blocks can also wear out and become unusable; those blocks
2631 are then marked "bad". NAND chips are even shipped from the
2632 manufacturer with a few bad blocks. The highest density chips
2633 use a technology (MLC) that wears out more quickly, so ECC
2634 support is increasingly important as a way to detect blocks
2635 that have begun to fail, and help to preserve data integrity
2636 with techniques such as wear leveling.
2638 Software is used to manage the ECC. Some controllers don't
2639 support ECC directly; in those cases, software ECC is used.
2640 Other controllers speed up the ECC calculations with hardware.
2641 Single-bit error correction hardware is routine. Controllers
2642 geared for newer MLC chips may correct 4 or more errors for
2643 every 512 bytes of data.
2645 You will need to make sure that any data you write using
2646 OpenOCD includes the apppropriate kind of ECC. For example,
2647 that may mean passing the @code{oob_softecc} flag when
2648 writing NAND data, or ensuring that the correct hardware
2651 The basic steps for using NAND devices include:
2653 @item Declare via the command @command{nand device}
2654 @* Do this in a board-specific configuration file,
2655 passing parameters as needed by the controller.
2656 @item Configure each device using @command{nand probe}.
2657 @* Do this only after the associated target is set up,
2658 such as in its reset-init script or in procures defined
2659 to access that device.
2660 @item Operate on the flash via @command{nand subcommand}
2661 @* Often commands to manipulate the flash are typed by a human, or run
2662 via a script in some automated way. Common task include writing a
2663 boot loader, operating system, or other data needed to initialize or
2667 @b{NOTE:} At the time this text was written, the largest NAND
2668 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
2669 This is because the variables used to hold offsets and lengths
2670 are only 32 bits wide.
2671 (Larger chips may work in some cases, unless an offset or length
2672 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
2673 Some larger devices will work, since they are actually multi-chip
2674 modules with two smaller chips and individual chipselect lines.
2676 @section NAND Configuration Commands
2677 @cindex NAND configuration
2679 NAND chips must be declared in configuration scripts,
2680 plus some additional configuration that's done after
2681 OpenOCD has initialized.
2683 @deffn {Config Command} {nand device} controller target [configparams...]
2684 Declares a NAND device, which can be read and written to
2685 after it has been configured through @command{nand probe}.
2686 In OpenOCD, devices are single chips; this is unlike some
2687 operating systems, which may manage multiple chips as if
2688 they were a single (larger) device.
2689 In some cases, configuring a device will activate extra
2690 commands; see the controller-specific documentation.
2692 @b{NOTE:} This command is not available after OpenOCD
2693 initialization has completed. Use it in board specific
2694 configuration files, not interactively.
2697 @item @var{controller} ... identifies a the controller driver
2698 associated with the NAND device being declared.
2699 @xref{NAND Driver List}.
2700 @item @var{target} ... names the target used when issuing
2701 commands to the NAND controller.
2702 @comment Actually, it's currently a controller-specific parameter...
2703 @item @var{configparams} ... controllers may support, or require,
2704 additional parameters. See the controller-specific documentation
2705 for more information.
2709 @deffn Command {nand list}
2710 Prints a one-line summary of each device declared
2711 using @command{nand device}, numbered from zero.
2712 Note that un-probed devices show no details.
2715 @deffn Command {nand probe} num
2716 Probes the specified device to determine key characteristics
2717 like its page and block sizes, and how many blocks it has.
2718 The @var{num} parameter is the value shown by @command{nand list}.
2719 You must (successfully) probe a device before you can use
2720 it with most other NAND commands.
2723 @section Erasing, Reading, Writing to NAND Flash
2725 @deffn Command {nand dump} num filename offset length [oob_option]
2726 @cindex NAND reading
2727 Reads binary data from the NAND device and writes it to the file,
2728 starting at the specified offset.
2729 The @var{num} parameter is the value shown by @command{nand list}.
2731 Use a complete path name for @var{filename}, so you don't depend
2732 on the directory used to start the OpenOCD server.
2734 The @var{offset} and @var{length} must be exact multiples of the
2735 device's page size. They describe a data region; the OOB data
2736 associated with each such page may also be accessed.
2738 @b{NOTE:} At the time this text was written, no error correction
2739 was done on the data that's read, unless raw access was disabled
2740 and the underlying NAND controller driver had a @code{read_page}
2741 method which handled that error correction.
2743 By default, only page data is saved to the specified file.
2744 Use an @var{oob_option} parameter to save OOB data:
2746 @item no oob_* parameter
2747 @*Output file holds only page data; OOB is discarded.
2748 @item @code{oob_raw}
2749 @*Output file interleaves page data and OOB data;
2750 the file will be longer than "length" by the size of the
2751 spare areas associated with each data page.
2752 Note that this kind of "raw" access is different from
2753 what's implied by @command{nand raw_access}, which just
2754 controls whether a hardware-aware access method is used.
2755 @item @code{oob_only}
2756 @*Output file has only raw OOB data, and will
2757 be smaller than "length" since it will contain only the
2758 spare areas associated with each data page.
2762 @deffn Command {nand erase} num offset length
2763 @cindex NAND erasing
2764 Erases blocks on the specified NAND device, starting at the
2765 specified @var{offset} and continuing for @var{length} bytes.
2766 Both of those values must be exact multiples of the device's
2767 block size, and the region they specify must fit entirely in the chip.
2768 The @var{num} parameter is the value shown by @command{nand list}.
2770 @b{NOTE:} This command will try to erase bad blocks, when told
2771 to do so, which will probably invalidate the manufacturer's bad
2773 For the remainder of the current server session, @command{nand info}
2774 will still report that the block ``is'' bad.
2777 @deffn Command {nand write} num filename offset [option...]
2778 @cindex NAND writing
2779 Writes binary data from the file into the specified NAND device,
2780 starting at the specified offset. Those pages should already
2781 have been erased; you can't change zero bits to one bits.
2782 The @var{num} parameter is the value shown by @command{nand list}.
2784 Use a complete path name for @var{filename}, so you don't depend
2785 on the directory used to start the OpenOCD server.
2787 The @var{offset} must be an exact multiple of the device's page size.
2788 All data in the file will be written, assuming it doesn't run
2789 past the end of the device.
2790 Only full pages are written, and any extra space in the last
2791 page will be filled with 0xff bytes. (That includes OOB data,
2792 if that's being written.)
2794 @b{NOTE:} At the time this text was written, bad blocks are
2795 ignored. That is, this routine will not skip bad blocks,
2796 but will instead try to write them. This can cause problems.
2798 Provide at most one @var{option} parameter. With some
2799 NAND drivers, the meanings of these parameters may change
2800 if @command{nand raw_access} was used to disable hardware ECC.
2802 @item no oob_* parameter
2803 @*File has only page data, which is written.
2804 If raw acccess is in use, the OOB area will not be written.
2805 Otherwise, if the underlying NAND controller driver has
2806 a @code{write_page} routine, that routine may write the OOB
2807 with hardware-computed ECC data.
2808 @item @code{oob_only}
2809 @*File has only raw OOB data, which is written to the OOB area.
2810 Each page's data area stays untouched. @i{This can be a dangerous
2811 option}, since it can invalidate the ECC data.
2812 You may need to force raw access to use this mode.
2813 @item @code{oob_raw}
2814 @*File interleaves data and OOB data, both of which are written
2815 If raw access is enabled, the data is written first, then the
2817 Otherwise, if the underlying NAND controller driver has
2818 a @code{write_page} routine, that routine may modify the OOB
2819 before it's written, to include hardware-computed ECC data.
2820 @item @code{oob_softecc}
2821 @*File has only page data, which is written.
2822 The OOB area is filled with 0xff, except for a standard 1-bit
2823 software ECC code stored in conventional locations.
2824 You might need to force raw access to use this mode, to prevent
2825 the underlying driver from applying hardware ECC.
2826 @item @code{oob_softecc_kw}
2827 @*File has only page data, which is written.
2828 The OOB area is filled with 0xff, except for a 4-bit software ECC
2829 specific to the boot ROM in Marvell Kirkwood SoCs.
2830 You might need to force raw access to use this mode, to prevent
2831 the underlying driver from applying hardware ECC.
2835 @section Other NAND commands
2836 @cindex NAND other commands
2838 @deffn Command {nand check_bad_blocks} [offset length]
2839 Checks for manufacturer bad block markers on the specified NAND
2840 device. If no parameters are provided, checks the whole
2841 device; otherwise, starts at the specified @var{offset} and
2842 continues for @var{length} bytes.
2843 Both of those values must be exact multiples of the device's
2844 block size, and the region they specify must fit entirely in the chip.
2845 The @var{num} parameter is the value shown by @command{nand list}.
2847 @b{NOTE:} Before using this command you should force raw access
2848 with @command{nand raw_access enable} to ensure that the underlying
2849 driver will not try to apply hardware ECC.
2852 @deffn Command {nand info} num
2853 The @var{num} parameter is the value shown by @command{nand list}.
2854 This prints the one-line summary from "nand list", plus for
2855 devices which have been probed this also prints any known
2856 status for each block.
2859 @deffn Command {nand raw_access} num <enable|disable>
2860 Sets or clears an flag affecting how page I/O is done.
2861 The @var{num} parameter is the value shown by @command{nand list}.
2863 This flag is cleared (disabled) by default, but changing that
2864 value won't affect all NAND devices. The key factor is whether
2865 the underlying driver provides @code{read_page} or @code{write_page}
2866 methods. If it doesn't provide those methods, the setting of
2867 this flag is irrelevant; all access is effectively ``raw''.
2869 When those methods exist, they are normally used when reading
2870 data (@command{nand dump} or reading bad block markers) or
2871 writing it (@command{nand write}). However, enabling
2872 raw access (setting the flag) prevents use of those methods,
2873 bypassing hardware ECC logic.
2874 @i{This can be a dangerous option}, since writing blocks
2875 with the wrong ECC data can cause them to be marked as bad.
2878 @section NAND Drivers; Driver-specific Options and Commands
2879 @anchor{NAND Driver List}
2880 As noted above, the @command{nand device} command allows
2881 driver-specific options and behaviors.
2882 Some controllers also activate controller-specific commands.
2884 @deffn {NAND Driver} davinci
2885 This driver handles the NAND controllers found on DaVinci family
2886 chips from Texas Instruments.
2887 It takes three extra parameters:
2888 address of the NAND chip;
2889 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
2890 address of the AEMIF controller on this processor.
2892 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
2894 All DaVinci processors support the single-bit ECC hardware,
2895 and newer ones also support the four-bit ECC hardware.
2896 The @code{write_page} and @code{read_page} methods are used
2897 to implement those ECC modes, unless they are disabled using
2898 the @command{nand raw_access} command.
2901 @deffn {NAND Driver} lpc3180
2902 These controllers require an extra @command{nand device}
2903 parameter: the clock rate used by the controller.
2904 @deffn Command {nand lpc3180 select} num [mlc|slc]
2905 Configures use of the MLC or SLC controller mode.
2906 MLC implies use of hardware ECC.
2907 The @var{num} parameter is the value shown by @command{nand list}.
2910 At this writing, this driver includes @code{write_page}
2911 and @code{read_page} methods. Using @command{nand raw_access}
2912 to disable those methods will prevent use of hardware ECC
2913 in the MLC controller mode, but won't change SLC behavior.
2915 @comment current lpc3180 code won't issue 5-byte address cycles
2917 @deffn {NAND Driver} orion
2918 These controllers require an extra @command{nand device}
2919 parameter: the address of the controller.
2921 nand device orion 0xd8000000
2923 These controllers don't define any specialized commands.
2924 At this writing, their drivers don't include @code{write_page}
2925 or @code{read_page} methods, so @command{nand raw_access} won't
2926 change any behavior.
2929 @deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
2930 These S3C24xx family controllers don't have any special
2931 @command{nand device} options, and don't define any
2932 specialized commands.
2933 At this writing, their drivers don't include @code{write_page}
2934 or @code{read_page} methods, so @command{nand raw_access} won't
2935 change any behavior.
2938 @node General Commands
2939 @chapter General Commands
2942 The commands documented in this chapter here are common commands that
2943 you, as a human, may want to type and see the output of. Configuration type
2944 commands are documented elsewhere.
2948 @item @b{Source Of Commands}
2949 @* OpenOCD commands can occur in a configuration script (discussed
2950 elsewhere) or typed manually by a human or supplied programatically,
2951 or via one of several TCP/IP Ports.
2953 @item @b{From the human}
2954 @* A human should interact with the telnet interface (default port: 4444)
2955 or via GDB (default port 3333).
2957 To issue commands from within a GDB session, use the @option{monitor}
2958 command, e.g. use @option{monitor poll} to issue the @option{poll}
2959 command. All output is relayed through the GDB session.
2961 @item @b{Machine Interface}
2962 The Tcl interface's intent is to be a machine interface. The default Tcl
2967 @section Daemon Commands
2969 @subsection sleep [@var{msec}]
2971 @*Wait for n milliseconds before resuming. Useful in connection with script files
2972 (@var{script} command and @var{target_script} configuration).
2974 @subsection shutdown
2976 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
2978 @subsection debug_level [@var{n}]
2980 @anchor{debug_level}
2981 @*Display or adjust debug level to n<0-3>
2983 @subsection fast [@var{enable|disable}]
2985 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
2986 downloads and fast memory access will work if the JTAG interface isn't too fast and
2987 the core doesn't run at a too low frequency. Note that this option only changes the default
2988 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
2991 The target specific "dangerous" optimisation tweaking options may come and go
2992 as more robust and user friendly ways are found to ensure maximum throughput
2993 and robustness with a minimum of configuration.
2995 Typically the "fast enable" is specified first on the command line:
2998 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
3001 @subsection echo <@var{message}>
3003 @*Output message to stdio. e.g. echo "Programming - please wait"
3005 @subsection log_output <@var{file}>
3007 @*Redirect logging to <file> (default: stderr)
3009 @subsection script <@var{file}>
3011 @*Execute commands from <file>
3012 See also: ``source [find FILENAME]''
3014 @section Target state handling
3015 @subsection power <@var{on}|@var{off}>
3017 @*Turn power switch to target on/off.
3018 No arguments: print status.
3019 Not all interfaces support this.
3021 @subsection reg [@option{#}|@option{name}] [value]
3023 @*Access a single register by its number[@option{#}] or by its [@option{name}].
3024 No arguments: list all available registers for the current target.
3025 Number or name argument: display a register.
3026 Number or name and value arguments: set register value.
3028 @subsection poll [@option{on}|@option{off}]
3030 @*Poll the target for its current state. If the target is in debug mode, architecture
3031 specific information about the current state is printed. An optional parameter
3032 allows continuous polling to be enabled and disabled.
3034 @subsection halt [@option{ms}]
3036 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
3037 Default [@option{ms}] is 5 seconds if no arg given.
3038 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
3039 will stop OpenOCD from waiting.
3041 @subsection wait_halt [@option{ms}]
3043 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
3044 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
3047 @subsection resume [@var{address}]
3049 @*Resume the target at its current code position, or at an optional address.
3050 OpenOCD will wait 5 seconds for the target to resume.
3052 @subsection step [@var{address}]
3054 @*Single-step the target at its current code position, or at an optional address.
3056 @subsection reset [@option{run}|@option{halt}|@option{init}]
3058 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
3060 With no arguments a "reset run" is executed
3064 @*Let the target run.
3067 @*Immediately halt the target (works only with certain configurations).
3070 @*Immediately halt the target, and execute the reset script (works only with certain
3074 @subsection soft_reset_halt
3076 @*Requesting target halt and executing a soft reset. This is often used
3077 when a target cannot be reset and halted. The target, after reset is
3078 released begins to execute code. OpenOCD attempts to stop the CPU and
3079 then sets the program counter back to the reset vector. Unfortunately
3080 the code that was executed may have left the hardware in an unknown
3084 @section Memory access commands
3086 display available RAM memory.
3087 @subsection Memory peek/poke type commands
3088 These commands allow accesses of a specific size to the memory
3089 system. Often these are used to configure the current target in some
3090 special way. For example - one may need to write certian values to the
3091 SDRAM controller to enable SDRAM.
3094 @item To change the current target see the ``targets'' (plural) command
3095 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
3099 @item @b{mdw} <@var{addr}> [@var{count}]
3101 @*display memory words (32bit)
3102 @item @b{mdh} <@var{addr}> [@var{count}]
3104 @*display memory half-words (16bit)
3105 @item @b{mdb} <@var{addr}> [@var{count}]
3107 @*display memory bytes (8bit)
3108 @item @b{mww} <@var{addr}> <@var{value}>
3110 @*write memory word (32bit)
3111 @item @b{mwh} <@var{addr}> <@var{value}>
3113 @*write memory half-word (16bit)
3114 @item @b{mwb} <@var{addr}> <@var{value}>
3116 @*write memory byte (8bit)
3119 @section Image loading commands
3120 @subsection load_image
3121 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3124 @*Load image <@var{file}> to target memory at <@var{address}>
3125 @subsection fast_load_image
3126 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3127 @cindex fast_load_image
3128 @anchor{fast_load_image}
3129 @*Normally you should be using @b{load_image} or GDB load. However, for
3130 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3131 host), storing the image in memory and uploading the image to the target
3132 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3133 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3134 memory, i.e. does not affect target. This approach is also useful when profiling
3135 target programming performance as I/O and target programming can easily be profiled
3137 @subsection fast_load
3141 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3142 @subsection dump_image
3143 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3146 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3147 (binary) <@var{file}>.
3148 @subsection verify_image
3149 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3150 @cindex verify_image
3151 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3152 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3155 @section Breakpoint commands
3156 @cindex Breakpoint commands
3158 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3160 @*set breakpoint <address> <length> [hw]
3161 @item @b{rbp} <@var{addr}>
3163 @*remove breakpoint <adress>
3164 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3166 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3167 @item @b{rwp} <@var{addr}>
3169 @*remove watchpoint <adress>
3172 @section Misc Commands
3173 @cindex Other Target Commands
3175 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3177 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3181 @section Target Specific Commands
3182 @cindex Target Specific Commands
3186 @section Architecture Specific Commands
3187 @cindex Architecture Specific Commands
3189 @subsection ARMV4/5 specific commands
3190 @cindex ARMV4/5 specific commands
3192 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
3193 or Intel XScale (XScale isn't supported yet).
3195 @item @b{armv4_5 reg}
3197 @*Display a list of all banked core registers, fetching the current value from every
3198 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3200 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
3201 @cindex armv4_5 core_mode
3202 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
3203 The target is resumed in the currently set @option{core_mode}.
3206 @subsection ARM7/9 specific commands
3207 @cindex ARM7/9 specific commands
3209 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
3210 ARM920T or ARM926EJ-S.
3212 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
3213 @cindex arm7_9 dbgrq
3214 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
3215 safe for all but ARM7TDMI--S cores (like Philips LPC).
3216 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
3217 @cindex arm7_9 fast_memory_access
3218 @anchor{arm7_9 fast_memory_access}
3219 @*Allow OpenOCD to read and write memory without checking completion of
3220 the operation. This provides a huge speed increase, especially with USB JTAG
3221 cables (FT2232), but might be unsafe if used with targets running at very low
3222 speeds, like the 32kHz startup clock of an AT91RM9200.
3223 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
3224 @cindex arm7_9 dcc_downloads
3225 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
3226 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
3227 unsafe, especially with targets running at very low speeds. This command was introduced
3228 with OpenOCD rev. 60, and requires a few bytes of working area.
3231 @subsection ARM720T specific commands
3232 @cindex ARM720T specific commands
3235 @item @b{arm720t cp15} <@var{num}> [@var{value}]
3236 @cindex arm720t cp15
3237 @*display/modify cp15 register <@option{num}> [@option{value}].
3238 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
3239 @cindex arm720t md<bhw>_phys
3240 @*Display memory at physical address addr.
3241 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
3242 @cindex arm720t mw<bhw>_phys
3243 @*Write memory at physical address addr.
3244 @item @b{arm720t virt2phys} <@var{va}>
3245 @cindex arm720t virt2phys
3246 @*Translate a virtual address to a physical address.
3249 @subsection ARM9TDMI specific commands
3250 @cindex ARM9TDMI specific commands
3253 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
3254 @cindex arm9tdmi vector_catch
3255 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
3256 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3257 @option{irq} @option{fiq}.
3259 Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
3262 @subsection ARM966E specific commands
3263 @cindex ARM966E specific commands
3266 @item @b{arm966e cp15} <@var{num}> [@var{value}]
3267 @cindex arm966e cp15
3268 @*display/modify cp15 register <@option{num}> [@option{value}].
3271 @subsection ARM920T specific commands
3272 @cindex ARM920T specific commands
3275 @item @b{arm920t cp15} <@var{num}> [@var{value}]
3276 @cindex arm920t cp15
3277 @*display/modify cp15 register <@option{num}> [@option{value}].
3278 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
3279 @cindex arm920t cp15i
3280 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
3281 @item @b{arm920t cache_info}
3282 @cindex arm920t cache_info
3283 @*Print information about the caches found. This allows to see whether your target
3284 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3285 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
3286 @cindex arm920t md<bhw>_phys
3287 @*Display memory at physical address addr.
3288 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
3289 @cindex arm920t mw<bhw>_phys
3290 @*Write memory at physical address addr.
3291 @item @b{arm920t read_cache} <@var{filename}>
3292 @cindex arm920t read_cache
3293 @*Dump the content of ICache and DCache to a file.
3294 @item @b{arm920t read_mmu} <@var{filename}>
3295 @cindex arm920t read_mmu
3296 @*Dump the content of the ITLB and DTLB to a file.
3297 @item @b{arm920t virt2phys} <@var{va}>
3298 @cindex arm920t virt2phys
3299 @*Translate a virtual address to a physical address.
3302 @subsection ARM926EJ-S specific commands
3303 @cindex ARM926EJ-S specific commands
3306 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
3307 @cindex arm926ejs cp15
3308 @*display/modify cp15 register <@option{num}> [@option{value}].
3309 @item @b{arm926ejs cache_info}
3310 @cindex arm926ejs cache_info
3311 @*Print information about the caches found.
3312 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
3313 @cindex arm926ejs md<bhw>_phys
3314 @*Display memory at physical address addr.
3315 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
3316 @cindex arm926ejs mw<bhw>_phys
3317 @*Write memory at physical address addr.
3318 @item @b{arm926ejs virt2phys} <@var{va}>
3319 @cindex arm926ejs virt2phys
3320 @*Translate a virtual address to a physical address.
3323 @subsection CORTEX_M3 specific commands
3324 @cindex CORTEX_M3 specific commands
3327 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
3328 @cindex cortex_m3 maskisr
3329 @*Enable masking (disabling) interrupts during target step/resume.
3333 @section Debug commands
3334 @cindex Debug commands
3335 The following commands give direct access to the core, and are most likely
3336 only useful while debugging OpenOCD.
3338 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
3339 @cindex arm7_9 write_xpsr
3340 @*Immediately write either the current program status register (CPSR) or the saved
3341 program status register (SPSR), without changing the register cache (as displayed
3342 by the @option{reg} and @option{armv4_5 reg} commands).
3343 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
3344 <@var{0=cpsr},@var{1=spsr}>
3345 @cindex arm7_9 write_xpsr_im8
3346 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
3347 operation (similar to @option{write_xpsr}).
3348 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
3349 @cindex arm7_9 write_core_reg
3350 @*Write a core register, without changing the register cache (as displayed by the
3351 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
3352 encoding of the [M4:M0] bits of the PSR.
3355 @section Target Requests
3356 @cindex Target Requests
3357 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
3358 See libdcc in the contrib dir for more details.
3360 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
3361 @cindex target_request debugmsgs
3362 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
3366 @chapter JTAG Commands
3367 @cindex JTAG Commands
3368 Generally most people will not use the bulk of these commands. They
3369 are mostly used by the OpenOCD developers or those who need to
3370 directly manipulate the JTAG taps.
3372 In general these commands control JTAG taps at a very low level. For
3373 example if you need to control a JTAG Route Controller (i.e.: the
3374 OMAP3530 on the Beagle Board has one) you might use these commands in
3375 a script or an event procedure.
3379 @item @b{scan_chain}
3381 @*Print current scan chain configuration.
3382 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
3384 @*Toggle reset lines.
3385 @item @b{endstate} <@var{tap_state}>
3387 @*Finish JTAG operations in <@var{tap_state}>.
3388 @item @b{runtest} <@var{num_cycles}>
3390 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
3391 @item @b{statemove} [@var{tap_state}]
3393 @*Move to current endstate or [@var{tap_state}]
3394 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3396 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3397 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
3399 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
3400 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
3401 @cindex verify_ircapture
3402 @*Verify value captured during Capture-IR. Default is enabled.
3403 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3405 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3406 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
3408 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
3413 Available tap_states are:
3453 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
3454 be used to access files on PCs (either the developer's PC or some other PC).
3456 The way this works on the ZY1000 is to prefix a filename by
3457 "/tftp/ip/" and append the TFTP path on the TFTP
3458 server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
3459 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
3460 if the file was hosted on the embedded host.
3462 In order to achieve decent performance, you must choose a TFTP server
3463 that supports a packet size bigger than the default packet size (512 bytes). There
3464 are numerous TFTP servers out there (free and commercial) and you will have to do
3465 a bit of googling to find something that fits your requirements.
3467 @node Sample Scripts
3468 @chapter Sample Scripts
3471 This page shows how to use the Target Library.
3473 The configuration script can be divided into the following sections:
3475 @item Daemon configuration
3477 @item JTAG scan chain
3478 @item Target configuration
3479 @item Flash configuration
3482 Detailed information about each section can be found at OpenOCD configuration.
3484 @section AT91R40008 example
3485 @cindex AT91R40008 example
3486 To start OpenOCD with a target script for the AT91R40008 CPU and reset
3487 the CPU upon startup of the OpenOCD daemon.
3489 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
3493 @node GDB and OpenOCD
3494 @chapter GDB and OpenOCD
3496 OpenOCD complies with the remote gdbserver protocol, and as such can be used
3497 to debug remote targets.
3499 @section Connecting to GDB
3500 @cindex Connecting to GDB
3501 @anchor{Connecting to GDB}
3502 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
3503 instance GDB 6.3 has a known bug that produces bogus memory access
3504 errors, which has since been fixed: look up 1836 in
3505 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
3507 @*OpenOCD can communicate with GDB in two ways:
3510 A socket (TCP/IP) connection is typically started as follows:
3512 target remote localhost:3333
3514 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
3516 A pipe connection is typically started as follows:
3518 target remote | openocd --pipe
3520 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
3521 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
3525 @*To see a list of available OpenOCD commands type @option{monitor help} on the
3528 OpenOCD supports the gdb @option{qSupported} packet, this enables information
3529 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
3530 packet size and the device's memory map.
3532 Previous versions of OpenOCD required the following GDB options to increase
3533 the packet size and speed up GDB communication:
3535 set remote memory-write-packet-size 1024
3536 set remote memory-write-packet-size fixed
3537 set remote memory-read-packet-size 1024
3538 set remote memory-read-packet-size fixed
3540 This is now handled in the @option{qSupported} PacketSize and should not be required.
3542 @section Programming using GDB
3543 @cindex Programming using GDB
3545 By default the target memory map is sent to GDB. This can be disabled by
3546 the following OpenOCD configuration option:
3548 gdb_memory_map disable
3550 For this to function correctly a valid flash configuration must also be set
3551 in OpenOCD. For faster performance you should also configure a valid
3554 Informing GDB of the memory map of the target will enable GDB to protect any
3555 flash areas of the target and use hardware breakpoints by default. This means
3556 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
3557 using a memory map. @xref{gdb_breakpoint_override}.
3559 To view the configured memory map in GDB, use the GDB command @option{info mem}
3560 All other unassigned addresses within GDB are treated as RAM.
3562 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
3563 This can be changed to the old behaviour by using the following GDB command
3565 set mem inaccessible-by-default off
3568 If @command{gdb_flash_program enable} is also used, GDB will be able to
3569 program any flash memory using the vFlash interface.
3571 GDB will look at the target memory map when a load command is given, if any
3572 areas to be programmed lie within the target flash area the vFlash packets
3575 If the target needs configuring before GDB programming, an event
3576 script can be executed:
3578 $_TARGETNAME configure -event EVENTNAME BODY
3581 To verify any flash programming the GDB command @option{compare-sections}
3584 @node Tcl Scripting API
3585 @chapter Tcl Scripting API
3586 @cindex Tcl Scripting API
3590 The commands are stateless. E.g. the telnet command line has a concept
3591 of currently active target, the Tcl API proc's take this sort of state
3592 information as an argument to each proc.
3594 There are three main types of return values: single value, name value
3595 pair list and lists.
3597 Name value pair. The proc 'foo' below returns a name/value pair
3603 > set foo(you) Oyvind
3604 > set foo(mouse) Micky
3605 > set foo(duck) Donald
3613 me Duane you Oyvind mouse Micky duck Donald
3615 Thus, to get the names of the associative array is easy:
3617 foreach { name value } [set foo] {
3618 puts "Name: $name, Value: $value"
3622 Lists returned must be relatively small. Otherwise a range
3623 should be passed in to the proc in question.
3625 @section Internal low-level Commands
3627 By low-level, the intent is a human would not directly use these commands.
3629 Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
3630 is the low level API upon which "flash banks" is implemented.
3633 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3635 Read memory and return as a Tcl array for script processing
3636 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3638 Convert a Tcl array to memory locations and write the values
3639 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
3641 Return information about the flash banks
3644 OpenOCD commands can consist of two words, e.g. "flash banks". The
3645 startup.tcl "unknown" proc will translate this into a Tcl proc
3646 called "flash_banks".
3648 @section OpenOCD specific Global Variables
3652 Real Tcl has ::tcl_platform(), and platform::identify, and many other
3653 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
3654 holds one of the following values:
3657 @item @b{winxx} Built using Microsoft Visual Studio
3658 @item @b{linux} Linux is the underlying operating sytem
3659 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
3660 @item @b{cygwin} Running under Cygwin
3661 @item @b{mingw32} Running under MingW32
3662 @item @b{other} Unknown, none of the above.
3665 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
3668 @chapter Deprecated/Removed Commands
3669 @cindex Deprecated/Removed Commands
3670 Certain OpenOCD commands have been deprecated/removed during the various revisions.
3673 @item @b{arm7_9 fast_writes}
3674 @cindex arm7_9 fast_writes
3675 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
3676 @item @b{arm7_9 force_hw_bkpts}
3677 @cindex arm7_9 force_hw_bkpts
3678 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
3679 for flash if the GDB memory map has been set up(default when flash is declared in
3680 target configuration). @xref{gdb_breakpoint_override}.
3681 @item @b{arm7_9 sw_bkpts}
3682 @cindex arm7_9 sw_bkpts
3683 @*On by default. @xref{gdb_breakpoint_override}.
3684 @item @b{daemon_startup}
3685 @cindex daemon_startup
3686 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
3687 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
3688 and @option{target cortex_m3 little reset_halt 0}.
3689 @item @b{dump_binary}
3691 @*use @option{dump_image} command with same args. @xref{dump_image}.
3692 @item @b{flash erase}
3694 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
3695 @item @b{flash write}
3697 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3698 @item @b{flash write_binary}
3699 @cindex flash write_binary
3700 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3701 @item @b{flash auto_erase}
3702 @cindex flash auto_erase
3703 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
3705 @item @b{jtag_speed} value
3706 @*@xref{JTAG Speed}.
3707 Usually, a value of zero means maximum
3708 speed. The actual effect of this option depends on the JTAG interface used.
3710 @item wiggler: maximum speed / @var{number}
3711 @item ft2232: 6MHz / (@var{number}+1)
3712 @item amt jtagaccel: 8 / 2**@var{number}
3713 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
3714 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
3715 @comment end speed list.
3718 @item @b{load_binary}
3720 @*use @option{load_image} command with same args. @xref{load_image}.
3721 @item @b{run_and_halt_time}
3722 @cindex run_and_halt_time
3723 @*This command has been removed for simpler reset behaviour, it can be simulated with the
3730 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
3732 @*use the create subcommand of @option{target}.
3733 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
3734 @cindex target_script
3735 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
3736 @item @b{working_area}
3737 @cindex working_area
3738 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3745 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3748 @cindex adaptive clocking
3751 In digital circuit design it is often refered to as ``clock
3752 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
3753 operating at some speed, your target is operating at another. The two
3754 clocks are not synchronised, they are ``asynchronous''
3756 In order for the two to work together they must be synchronised. Otherwise
3757 the two systems will get out of sync with each other and nothing will
3758 work. There are 2 basic options:
3761 Use a special circuit.
3763 One clock must be some multiple slower than the other.
3766 @b{Does this really matter?} For some chips and some situations, this
3767 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
3768 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
3769 program/enable the oscillators and eventually the main clock. It is in
3770 those critical times you must slow the JTAG clock to sometimes 1 to
3773 Imagine debugging a 500MHz ARM926 hand held battery powered device
3774 that ``deep sleeps'' at 32kHz between every keystroke. It can be
3777 @b{Solution #1 - A special circuit}
3779 In order to make use of this, your JTAG dongle must support the RTCK
3780 feature. Not all dongles support this - keep reading!
3782 The RTCK signal often found in some ARM chips is used to help with
3783 this problem. ARM has a good description of the problem described at
3784 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3785 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
3786 work? / how does adaptive clocking work?''.
3788 The nice thing about adaptive clocking is that ``battery powered hand
3789 held device example'' - the adaptiveness works perfectly all the
3790 time. One can set a break point or halt the system in the deep power
3791 down code, slow step out until the system speeds up.
3793 @b{Solution #2 - Always works - but may be slower}
3795 Often this is a perfectly acceptable solution.
3797 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3798 the target clock speed. But what that ``magic division'' is varies
3799 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
3800 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
3801 1/12 the clock speed.
3803 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
3805 You can still debug the 'low power' situations - you just need to
3806 manually adjust the clock speed at every step. While painful and
3807 tedious, it is not always practical.
3809 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
3810 have a special debug mode in your application that does a ``high power
3811 sleep''. If you are careful - 98% of your problems can be debugged
3814 To set the JTAG frequency use the command:
3822 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
3824 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3825 around Windows filenames.
3838 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3840 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3841 claims to come with all the necessary DLLs. When using Cygwin, try launching
3842 OpenOCD from the Cygwin shell.
3844 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3845 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3846 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3848 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3849 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
3850 software breakpoints consume one of the two available hardware breakpoints.
3852 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
3854 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3855 clock at the time you're programming the flash. If you've specified the crystal's
3856 frequency, make sure the PLL is disabled. If you've specified the full core speed
3857 (e.g. 60MHz), make sure the PLL is enabled.
3859 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3860 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3861 out while waiting for end of scan, rtck was disabled".
3863 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3864 settings in your PC BIOS (ECP, EPP, and different versions of those).
3866 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3867 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3868 memory read caused data abort".
3870 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3871 beyond the last valid frame. It might be possible to prevent this by setting up
3872 a proper "initial" stack frame, if you happen to know what exactly has to
3873 be done, feel free to add this here.
3875 @b{Simple:} In your startup code - push 8 registers of zeros onto the
3876 stack before calling main(). What GDB is doing is ``climbing'' the run
3877 time stack by reading various values on the stack using the standard
3878 call frame for the target. GDB keeps going - until one of 2 things
3879 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3880 stackframes have been processed. By pushing zeros on the stack, GDB
3883 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3884 your C code, do the same - artifically push some zeros onto the stack,
3885 remember to pop them off when the ISR is done.
3887 @b{Also note:} If you have a multi-threaded operating system, they
3888 often do not @b{in the intrest of saving memory} waste these few
3892 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3893 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3895 This warning doesn't indicate any serious problem, as long as you don't want to
3896 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3897 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3898 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3899 independently. With this setup, it's not possible to halt the core right out of
3900 reset, everything else should work fine.
3902 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3903 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3904 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3905 quit with an error message. Is there a stability issue with OpenOCD?
3907 No, this is not a stability issue concerning OpenOCD. Most users have solved
3908 this issue by simply using a self-powered USB hub, which they connect their
3909 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3910 supply stable enough for the Amontec JTAGkey to be operated.
3912 @b{Laptops running on battery have this problem too...}
3914 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3915 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3916 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3917 What does that mean and what might be the reason for this?
3919 First of all, the reason might be the USB power supply. Try using a self-powered
3920 hub instead of a direct connection to your computer. Secondly, the error code 4
3921 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3922 chip ran into some sort of error - this points us to a USB problem.
3924 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3925 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3926 What does that mean and what might be the reason for this?
3928 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3929 has closed the connection to OpenOCD. This might be a GDB issue.
3931 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3932 are described, there is a parameter for specifying the clock frequency
3933 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
3934 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
3935 specified in kilohertz. However, I do have a quartz crystal of a
3936 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
3937 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
3940 No. The clock frequency specified here must be given as an integral number.
3941 However, this clock frequency is used by the In-Application-Programming (IAP)
3942 routines of the LPC2000 family only, which seems to be very tolerant concerning
3943 the given clock frequency, so a slight difference between the specified clock
3944 frequency and the actual clock frequency will not cause any trouble.
3946 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
3948 Well, yes and no. Commands can be given in arbitrary order, yet the
3949 devices listed for the JTAG scan chain must be given in the right
3950 order (jtag newdevice), with the device closest to the TDO-Pin being
3951 listed first. In general, whenever objects of the same type exist
3952 which require an index number, then these objects must be given in the
3953 right order (jtag newtap, targets and flash banks - a target
3954 references a jtag newtap and a flash bank references a target).
3956 You can use the ``scan_chain'' command to verify and display the tap order.
3958 Also, some commands can't execute until after @command{init} has been
3959 processed. Such commands include @command{nand probe} and everything
3960 else that needs to write to controller registers, perhaps for setting
3961 up DRAM and loading it with code.
3963 @item @b{JTAG Tap Order} JTAG tap order - command order
3965 Many newer devices have multiple JTAG taps. For example: ST
3966 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
3967 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
3968 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
3969 connected to the boundary scan tap, which then connects to the
3970 Cortex-M3 tap, which then connects to the TDO pin.
3972 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
3973 (2) The boundary scan tap. If your board includes an additional JTAG
3974 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
3975 place it before or after the STM32 chip in the chain. For example:
3978 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
3979 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
3980 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
3981 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
3982 @item Xilinx TDO Pin -> OpenOCD TDO (input)
3985 The ``jtag device'' commands would thus be in the order shown below. Note:
3988 @item jtag newtap Xilinx tap -irlen ...
3989 @item jtag newtap stm32 cpu -irlen ...
3990 @item jtag newtap stm32 bs -irlen ...
3991 @item # Create the debug target and say where it is
3992 @item target create stm32.cpu -chain-position stm32.cpu ...
3996 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
3997 log file, I can see these error messages: Error: arm7_9_common.c:561
3998 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
4004 @node Tcl Crash Course
4005 @chapter Tcl Crash Course
4008 Not everyone knows Tcl - this is not intended to be a replacement for
4009 learning Tcl, the intent of this chapter is to give you some idea of
4010 how the Tcl scripts work.
4012 This chapter is written with two audiences in mind. (1) OpenOCD users
4013 who need to understand a bit more of how JIM-Tcl works so they can do
4014 something useful, and (2) those that want to add a new command to
4017 @section Tcl Rule #1
4018 There is a famous joke, it goes like this:
4020 @item Rule #1: The wife is always correct
4021 @item Rule #2: If you think otherwise, See Rule #1
4024 The Tcl equal is this:
4027 @item Rule #1: Everything is a string
4028 @item Rule #2: If you think otherwise, See Rule #1
4031 As in the famous joke, the consequences of Rule #1 are profound. Once
4032 you understand Rule #1, you will understand Tcl.
4034 @section Tcl Rule #1b
4035 There is a second pair of rules.
4037 @item Rule #1: Control flow does not exist. Only commands
4038 @* For example: the classic FOR loop or IF statement is not a control
4039 flow item, they are commands, there is no such thing as control flow
4041 @item Rule #2: If you think otherwise, See Rule #1
4042 @* Actually what happens is this: There are commands that by
4043 convention, act like control flow key words in other languages. One of
4044 those commands is the word ``for'', another command is ``if''.
4047 @section Per Rule #1 - All Results are strings
4048 Every Tcl command results in a string. The word ``result'' is used
4049 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
4050 Everything is a string}
4052 @section Tcl Quoting Operators
4053 In life of a Tcl script, there are two important periods of time, the
4054 difference is subtle.
4057 @item Evaluation Time
4060 The two key items here are how ``quoted things'' work in Tcl. Tcl has
4061 three primary quoting constructs, the [square-brackets] the
4062 @{curly-braces@} and ``double-quotes''
4064 By now you should know $VARIABLES always start with a $DOLLAR
4065 sign. BTW: To set a variable, you actually use the command ``set'', as
4066 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
4067 = 1'' statement, but without the equal sign.
4070 @item @b{[square-brackets]}
4071 @* @b{[square-brackets]} are command substitutions. It operates much
4072 like Unix Shell `back-ticks`. The result of a [square-bracket]
4073 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
4074 string}. These two statements are roughly identical:
4078 echo "The Date is: $X"
4081 puts "The Date is: $X"
4083 @item @b{``double-quoted-things''}
4084 @* @b{``double-quoted-things''} are just simply quoted
4085 text. $VARIABLES and [square-brackets] are expanded in place - the
4086 result however is exactly 1 string. @i{Remember Rule #1 - Everything
4090 puts "It is now \"[date]\", $x is in 1 hour"
4092 @item @b{@{Curly-Braces@}}
4093 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
4094 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
4095 'single-quote' operators in BASH shell scripts, with the added
4096 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
4097 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
4098 28/nov/2008, Jim/OpenOCD does not have a date command.
4101 @section Consequences of Rule 1/2/3/4
4103 The consequences of Rule 1 are profound.
4105 @subsection Tokenisation & Execution.
4107 Of course, whitespace, blank lines and #comment lines are handled in
4110 As a script is parsed, each (multi) line in the script file is
4111 tokenised and according to the quoting rules. After tokenisation, that
4112 line is immedatly executed.
4114 Multi line statements end with one or more ``still-open''
4115 @{curly-braces@} which - eventually - closes a few lines later.
4117 @subsection Command Execution
4119 Remember earlier: There are no ``control flow''
4120 statements in Tcl. Instead there are COMMANDS that simply act like
4121 control flow operators.
4123 Commands are executed like this:
4126 @item Parse the next line into (argc) and (argv[]).
4127 @item Look up (argv[0]) in a table and call its function.
4128 @item Repeat until End Of File.
4131 It sort of works like this:
4134 ReadAndParse( &argc, &argv );
4136 cmdPtr = LookupCommand( argv[0] );
4138 (*cmdPtr->Execute)( argc, argv );
4142 When the command ``proc'' is parsed (which creates a procedure
4143 function) it gets 3 parameters on the command line. @b{1} the name of
4144 the proc (function), @b{2} the list of parameters, and @b{3} the body
4145 of the function. Not the choice of words: LIST and BODY. The PROC
4146 command stores these items in a table somewhere so it can be found by
4149 @subsection The FOR command
4151 The most interesting command to look at is the FOR command. In Tcl,
4152 the FOR command is normally implemented in C. Remember, FOR is a
4153 command just like any other command.
4155 When the ascii text containing the FOR command is parsed, the parser
4156 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
4160 @item The ascii text 'for'
4161 @item The start text
4162 @item The test expression
4167 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
4168 Remember @i{Rule #1 - Everything is a string.} The key point is this:
4169 Often many of those parameters are in @{curly-braces@} - thus the
4170 variables inside are not expanded or replaced until later.
4172 Remember that every Tcl command looks like the classic ``main( argc,
4173 argv )'' function in C. In JimTCL - they actually look like this:
4177 MyCommand( Jim_Interp *interp,
4179 Jim_Obj * const *argvs );
4182 Real Tcl is nearly identical. Although the newer versions have
4183 introduced a byte-code parser and intepreter, but at the core, it
4184 still operates in the same basic way.
4186 @subsection FOR command implementation
4188 To understand Tcl it is perhaps most helpful to see the FOR
4189 command. Remember, it is a COMMAND not a control flow structure.
4191 In Tcl there are two underlying C helper functions.
4193 Remember Rule #1 - You are a string.
4195 The @b{first} helper parses and executes commands found in an ascii
4196 string. Commands can be seperated by semicolons, or newlines. While
4197 parsing, variables are expanded via the quoting rules.
4199 The @b{second} helper evaluates an ascii string as a numerical
4200 expression and returns a value.
4202 Here is an example of how the @b{FOR} command could be
4203 implemented. The pseudo code below does not show error handling.
4205 void Execute_AsciiString( void *interp, const char *string );
4207 int Evaluate_AsciiExpression( void *interp, const char *string );
4210 MyForCommand( void *interp,
4215 SetResult( interp, "WRONG number of parameters");
4219 // argv[0] = the ascii string just like C
4221 // Execute the start statement.
4222 Execute_AsciiString( interp, argv[1] );
4226 i = Evaluate_AsciiExpression(interp, argv[2]);
4231 Execute_AsciiString( interp, argv[3] );
4233 // Execute the LOOP part
4234 Execute_AsciiString( interp, argv[4] );
4238 SetResult( interp, "" );
4243 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
4244 in the same basic way.
4246 @section OpenOCD Tcl Usage
4248 @subsection source and find commands
4249 @b{Where:} In many configuration files
4250 @* Example: @b{ source [find FILENAME] }
4251 @*Remember the parsing rules
4253 @item The FIND command is in square brackets.
4254 @* The FIND command is executed with the parameter FILENAME. It should
4255 find the full path to the named file. The RESULT is a string, which is
4256 substituted on the orginal command line.
4257 @item The command source is executed with the resulting filename.
4258 @* SOURCE reads a file and executes as a script.
4260 @subsection format command
4261 @b{Where:} Generally occurs in numerous places.
4262 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
4268 puts [format "The answer: %d" [expr $x * $y]]
4271 @item The SET command creates 2 variables, X and Y.
4272 @item The double [nested] EXPR command performs math
4273 @* The EXPR command produces numerical result as a string.
4275 @item The format command is executed, producing a single string
4276 @* Refer to Rule #1.
4277 @item The PUTS command outputs the text.
4279 @subsection Body or Inlined Text
4280 @b{Where:} Various TARGET scripts.
4283 proc someproc @{@} @{
4284 ... multiple lines of stuff ...
4286 $_TARGETNAME configure -event FOO someproc
4287 #2 Good - no variables
4288 $_TARGETNAME confgure -event foo "this ; that;"
4289 #3 Good Curly Braces
4290 $_TARGETNAME configure -event FOO @{
4293 #4 DANGER DANGER DANGER
4294 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
4297 @item The $_TARGETNAME is an OpenOCD variable convention.
4298 @*@b{$_TARGETNAME} represents the last target created, the value changes
4299 each time a new target is created. Remember the parsing rules. When
4300 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
4301 the name of the target which happens to be a TARGET (object)
4303 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
4304 @*There are 4 examples:
4306 @item The TCLBODY is a simple string that happens to be a proc name
4307 @item The TCLBODY is several simple commands seperated by semicolons
4308 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
4309 @item The TCLBODY is a string with variables that get expanded.
4312 In the end, when the target event FOO occurs the TCLBODY is
4313 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
4314 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
4316 Remember the parsing rules. In case #3, @{curly-braces@} mean the
4317 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
4318 and the text is evaluated. In case #4, they are replaced before the
4319 ``Target Object Command'' is executed. This occurs at the same time
4320 $_TARGETNAME is replaced. In case #4 the date will never
4321 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
4322 Jim/OpenOCD does not have a date command@}
4324 @subsection Global Variables
4325 @b{Where:} You might discover this when writing your own procs @* In
4326 simple terms: Inside a PROC, if you need to access a global variable
4327 you must say so. See also ``upvar''. Example:
4329 proc myproc @{ @} @{
4330 set y 0 #Local variable Y
4331 global x #Global variable X
4332 puts [format "X=%d, Y=%d" $x $y]
4335 @section Other Tcl Hacks
4336 @b{Dynamic variable creation}
4338 # Dynamically create a bunch of variables.
4339 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
4341 set vn [format "BIT%d" $x]
4345 set $vn [expr (1 << $x)]
4348 @b{Dynamic proc/command creation}
4350 # One "X" function - 5 uart functions.
4351 foreach who @{A B C D E@}
4352 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
4356 @node Target Library
4357 @chapter Target Library
4358 @cindex Target Library
4360 OpenOCD comes with a target configuration script library. These scripts can be
4361 used as-is or serve as a starting point.
4363 The target library is published together with the OpenOCD executable and
4364 the path to the target library is in the OpenOCD script search path.
4365 Similarly there are example scripts for configuring the JTAG interface.
4367 The command line below uses the example parport configuration script
4368 that ship with OpenOCD, then configures the str710.cfg target and
4369 finally issues the init and reset commands. The communication speed
4370 is set to 10kHz for reset and 8MHz for post reset.
4373 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
4376 To list the target scripts available:
4379 $ ls /usr/local/lib/openocd/target
4381 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
4382 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
4383 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
4384 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
4389 @node OpenOCD Concept Index
4390 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
4391 @comment case issue with ``Index.html'' and ``index.html''
4392 @comment Occurs when creating ``--html --no-split'' output
4393 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
4394 @unnumbered OpenOCD Concept Index
4398 @node OpenOCD Command Index
4399 @unnumbered OpenOCD Command Index