1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
535 @item @b{TI XDS110 Debug Probe}
536 @* The XDS110 is included as the embedded debug probe on many Texas Instruments
537 LaunchPad evaluation boards.
538 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
539 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
542 @section IBM PC Parallel Printer Port Based
544 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
545 and the Macraigor Wiggler. There are many clones and variations of
548 Note that parallel ports are becoming much less common, so if you
549 have the choice you should probably avoid these adapters in favor
554 @item @b{Wiggler} - There are many clones of this.
555 @* Link: @url{http://www.macraigor.com/wiggler.htm}
557 @item @b{DLC5} - From XILINX - There are many clones of this
558 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
559 produced, PDF schematics are easily found and it is easy to make.
561 @item @b{Amontec - JTAG Accelerator}
562 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
565 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
567 @item @b{Wiggler_ntrst_inverted}
568 @* Yet another variation - See the source code, src/jtag/parport.c
570 @item @b{old_amt_wiggler}
571 @* Unknown - probably not on the market today
574 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
577 @* Link: @url{http://www.amontec.com/chameleon.shtml}
583 @* ispDownload from Lattice Semiconductor
584 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
587 @* From STMicroelectronics;
588 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
596 @* An EP93xx based Linux machine using the GPIO pins directly.
599 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
601 @item @b{bcm2835gpio}
602 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
605 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
608 @* A JTAG driver acting as a client for the JTAG VPI server interface.
609 @* Link: @url{http://github.com/fjullien/jtag_vpi}
614 @chapter About Jim-Tcl
618 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
619 This programming language provides a simple and extensible
622 All commands presented in this Guide are extensions to Jim-Tcl.
623 You can use them as simple commands, without needing to learn
624 much of anything about Tcl.
625 Alternatively, you can write Tcl programs with them.
627 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
628 There is an active and responsive community, get on the mailing list
629 if you have any questions. Jim-Tcl maintainers also lurk on the
630 OpenOCD mailing list.
633 @item @b{Jim vs. Tcl}
634 @* Jim-Tcl is a stripped down version of the well known Tcl language,
635 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
636 fewer features. Jim-Tcl is several dozens of .C files and .H files and
637 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
638 4.2 MB .zip file containing 1540 files.
640 @item @b{Missing Features}
641 @* Our practice has been: Add/clone the real Tcl feature if/when
642 needed. We welcome Jim-Tcl improvements, not bloat. Also there
643 are a large number of optional Jim-Tcl features that are not
647 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
648 command interpreter today is a mixture of (newer)
649 Jim-Tcl commands, and the (older) original command interpreter.
652 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
653 can type a Tcl for() loop, set variables, etc.
654 Some of the commands documented in this guide are implemented
655 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
657 @item @b{Historical Note}
658 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
659 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
660 as a Git submodule, which greatly simplified upgrading Jim-Tcl
661 to benefit from new features and bugfixes in Jim-Tcl.
663 @item @b{Need a crash course in Tcl?}
664 @*@xref{Tcl Crash Course}.
669 @cindex command line options
671 @cindex directory search
673 Properly installing OpenOCD sets up your operating system to grant it access
674 to the debug adapters. On Linux, this usually involves installing a file
675 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
676 that works for many common adapters is shipped with OpenOCD in the
677 @file{contrib} directory. MS-Windows needs
678 complex and confusing driver configuration for every peripheral. Such issues
679 are unique to each operating system, and are not detailed in this User's Guide.
681 Then later you will invoke the OpenOCD server, with various options to
682 tell it how each debug session should work.
683 The @option{--help} option shows:
687 --help | -h display this help
688 --version | -v display OpenOCD version
689 --file | -f use configuration file <name>
690 --search | -s dir to search for config files and scripts
691 --debug | -d set debug level to 3
692 | -d<n> set debug level to <level>
693 --log_output | -l redirect log output to file <name>
694 --command | -c run <command>
697 If you don't give any @option{-f} or @option{-c} options,
698 OpenOCD tries to read the configuration file @file{openocd.cfg}.
699 To specify one or more different
700 configuration files, use @option{-f} options. For example:
703 openocd -f config1.cfg -f config2.cfg -f config3.cfg
706 Configuration files and scripts are searched for in
708 @item the current directory,
709 @item any search dir specified on the command line using the @option{-s} option,
710 @item any search dir specified using the @command{add_script_search_dir} command,
711 @item @file{$HOME/.openocd} (not on Windows),
712 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
713 @item the site wide script library @file{$pkgdatadir/site} and
714 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
716 The first found file with a matching file name will be used.
719 Don't try to use configuration script names or paths which
720 include the "#" character. That character begins Tcl comments.
723 @section Simple setup, no customization
725 In the best case, you can use two scripts from one of the script
726 libraries, hook up your JTAG adapter, and start the server ... and
727 your JTAG setup will just work "out of the box". Always try to
728 start by reusing those scripts, but assume you'll need more
729 customization even if this works. @xref{OpenOCD Project Setup}.
731 If you find a script for your JTAG adapter, and for your board or
732 target, you may be able to hook up your JTAG adapter then start
733 the server with some variation of one of the following:
736 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
737 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
740 You might also need to configure which reset signals are present,
741 using @option{-c 'reset_config trst_and_srst'} or something similar.
742 If all goes well you'll see output something like
745 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
746 For bug reports, read
747 http://openocd.org/doc/doxygen/bugs.html
748 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
749 (mfg: 0x23b, part: 0xba00, ver: 0x3)
752 Seeing that "tap/device found" message, and no warnings, means
753 the JTAG communication is working. That's a key milestone, but
754 you'll probably need more project-specific setup.
756 @section What OpenOCD does as it starts
758 OpenOCD starts by processing the configuration commands provided
759 on the command line or, if there were no @option{-c command} or
760 @option{-f file.cfg} options given, in @file{openocd.cfg}.
761 @xref{configurationstage,,Configuration Stage}.
762 At the end of the configuration stage it verifies the JTAG scan
763 chain defined using those commands; your configuration should
764 ensure that this always succeeds.
765 Normally, OpenOCD then starts running as a server.
766 Alternatively, commands may be used to terminate the configuration
767 stage early, perform work (such as updating some flash memory),
768 and then shut down without acting as a server.
770 Once OpenOCD starts running as a server, it waits for connections from
771 clients (Telnet, GDB, RPC) and processes the commands issued through
774 If you are having problems, you can enable internal debug messages via
775 the @option{-d} option.
777 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
778 @option{-c} command line switch.
780 To enable debug output (when reporting problems or working on OpenOCD
781 itself), use the @option{-d} command line switch. This sets the
782 @option{debug_level} to "3", outputting the most information,
783 including debug messages. The default setting is "2", outputting only
784 informational messages, warnings and errors. You can also change this
785 setting from within a telnet or gdb session using @command{debug_level<n>}
786 (@pxref{debuglevel,,debug_level}).
788 You can redirect all output from the server to a file using the
789 @option{-l <logfile>} switch.
791 Note! OpenOCD will launch the GDB & telnet server even if it can not
792 establish a connection with the target. In general, it is possible for
793 the JTAG controller to be unresponsive until the target is set up
794 correctly via e.g. GDB monitor commands in a GDB init script.
796 @node OpenOCD Project Setup
797 @chapter OpenOCD Project Setup
799 To use OpenOCD with your development projects, you need to do more than
800 just connect the JTAG adapter hardware (dongle) to your development board
801 and start the OpenOCD server.
802 You also need to configure your OpenOCD server so that it knows
803 about your adapter and board, and helps your work.
804 You may also want to connect OpenOCD to GDB, possibly
805 using Eclipse or some other GUI.
807 @section Hooking up the JTAG Adapter
809 Today's most common case is a dongle with a JTAG cable on one side
810 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
811 and a USB cable on the other.
812 Instead of USB, some cables use Ethernet;
813 older ones may use a PC parallel port, or even a serial port.
816 @item @emph{Start with power to your target board turned off},
817 and nothing connected to your JTAG adapter.
818 If you're particularly paranoid, unplug power to the board.
819 It's important to have the ground signal properly set up,
820 unless you are using a JTAG adapter which provides
821 galvanic isolation between the target board and the
824 @item @emph{Be sure it's the right kind of JTAG connector.}
825 If your dongle has a 20-pin ARM connector, you need some kind
826 of adapter (or octopus, see below) to hook it up to
827 boards using 14-pin or 10-pin connectors ... or to 20-pin
828 connectors which don't use ARM's pinout.
830 In the same vein, make sure the voltage levels are compatible.
831 Not all JTAG adapters have the level shifters needed to work
832 with 1.2 Volt boards.
834 @item @emph{Be certain the cable is properly oriented} or you might
835 damage your board. In most cases there are only two possible
836 ways to connect the cable.
837 Connect the JTAG cable from your adapter to the board.
838 Be sure it's firmly connected.
840 In the best case, the connector is keyed to physically
841 prevent you from inserting it wrong.
842 This is most often done using a slot on the board's male connector
843 housing, which must match a key on the JTAG cable's female connector.
844 If there's no housing, then you must look carefully and
845 make sure pin 1 on the cable hooks up to pin 1 on the board.
846 Ribbon cables are frequently all grey except for a wire on one
847 edge, which is red. The red wire is pin 1.
849 Sometimes dongles provide cables where one end is an ``octopus'' of
850 color coded single-wire connectors, instead of a connector block.
851 These are great when converting from one JTAG pinout to another,
852 but are tedious to set up.
853 Use these with connector pinout diagrams to help you match up the
854 adapter signals to the right board pins.
856 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
857 A USB, parallel, or serial port connector will go to the host which
858 you are using to run OpenOCD.
859 For Ethernet, consult the documentation and your network administrator.
861 For USB-based JTAG adapters you have an easy sanity check at this point:
862 does the host operating system see the JTAG adapter? If you're running
863 Linux, try the @command{lsusb} command. If that host is an
864 MS-Windows host, you'll need to install a driver before OpenOCD works.
866 @item @emph{Connect the adapter's power supply, if needed.}
867 This step is primarily for non-USB adapters,
868 but sometimes USB adapters need extra power.
870 @item @emph{Power up the target board.}
871 Unless you just let the magic smoke escape,
872 you're now ready to set up the OpenOCD server
873 so you can use JTAG to work with that board.
877 Talk with the OpenOCD server using
878 telnet (@code{telnet localhost 4444} on many systems) or GDB.
879 @xref{GDB and OpenOCD}.
881 @section Project Directory
883 There are many ways you can configure OpenOCD and start it up.
885 A simple way to organize them all involves keeping a
886 single directory for your work with a given board.
887 When you start OpenOCD from that directory,
888 it searches there first for configuration files, scripts,
889 files accessed through semihosting,
890 and for code you upload to the target board.
891 It is also the natural place to write files,
892 such as log files and data you download from the board.
894 @section Configuration Basics
896 There are two basic ways of configuring OpenOCD, and
897 a variety of ways you can mix them.
898 Think of the difference as just being how you start the server:
901 @item Many @option{-f file} or @option{-c command} options on the command line
902 @item No options, but a @dfn{user config file}
903 in the current directory named @file{openocd.cfg}
906 Here is an example @file{openocd.cfg} file for a setup
907 using a Signalyzer FT2232-based JTAG adapter to talk to
908 a board with an Atmel AT91SAM7X256 microcontroller:
911 source [find interface/ftdi/signalyzer.cfg]
913 # GDB can also flash my flash!
914 gdb_memory_map enable
915 gdb_flash_program enable
917 source [find target/sam7x256.cfg]
920 Here is the command line equivalent of that configuration:
923 openocd -f interface/ftdi/signalyzer.cfg \
924 -c "gdb_memory_map enable" \
925 -c "gdb_flash_program enable" \
926 -f target/sam7x256.cfg
929 You could wrap such long command lines in shell scripts,
930 each supporting a different development task.
931 One might re-flash the board with a specific firmware version.
932 Another might set up a particular debugging or run-time environment.
935 At this writing (October 2009) the command line method has
936 problems with how it treats variables.
937 For example, after @option{-c "set VAR value"}, or doing the
938 same in a script, the variable @var{VAR} will have no value
939 that can be tested in a later script.
942 Here we will focus on the simpler solution: one user config
943 file, including basic configuration plus any TCL procedures
944 to simplify your work.
946 @section User Config Files
947 @cindex config file, user
948 @cindex user config file
949 @cindex config file, overview
951 A user configuration file ties together all the parts of a project
953 One of the following will match your situation best:
956 @item Ideally almost everything comes from configuration files
957 provided by someone else.
958 For example, OpenOCD distributes a @file{scripts} directory
959 (probably in @file{/usr/share/openocd/scripts} on Linux).
960 Board and tool vendors can provide these too, as can individual
961 user sites; the @option{-s} command line option lets you say
962 where to find these files. (@xref{Running}.)
963 The AT91SAM7X256 example above works this way.
965 Three main types of non-user configuration file each have their
966 own subdirectory in the @file{scripts} directory:
969 @item @b{interface} -- one for each different debug adapter;
970 @item @b{board} -- one for each different board
971 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
974 Best case: include just two files, and they handle everything else.
975 The first is an interface config file.
976 The second is board-specific, and it sets up the JTAG TAPs and
977 their GDB targets (by deferring to some @file{target.cfg} file),
978 declares all flash memory, and leaves you nothing to do except
982 source [find interface/olimex-jtag-tiny.cfg]
983 source [find board/csb337.cfg]
986 Boards with a single microcontroller often won't need more
987 than the target config file, as in the AT91SAM7X256 example.
988 That's because there is no external memory (flash, DDR RAM), and
989 the board differences are encapsulated by application code.
991 @item Maybe you don't know yet what your board looks like to JTAG.
992 Once you know the @file{interface.cfg} file to use, you may
993 need help from OpenOCD to discover what's on the board.
994 Once you find the JTAG TAPs, you can just search for appropriate
996 configuration files ... or write your own, from the bottom up.
997 @xref{autoprobing,,Autoprobing}.
999 @item You can often reuse some standard config files but
1000 need to write a few new ones, probably a @file{board.cfg} file.
1001 You will be using commands described later in this User's Guide,
1002 and working with the guidelines in the next chapter.
1004 For example, there may be configuration files for your JTAG adapter
1005 and target chip, but you need a new board-specific config file
1006 giving access to your particular flash chips.
1007 Or you might need to write another target chip configuration file
1008 for a new chip built around the Cortex-M3 core.
1011 When you write new configuration files, please submit
1012 them for inclusion in the next OpenOCD release.
1013 For example, a @file{board/newboard.cfg} file will help the
1014 next users of that board, and a @file{target/newcpu.cfg}
1015 will help support users of any board using that chip.
1019 You may may need to write some C code.
1020 It may be as simple as supporting a new FT2232 or parport
1021 based adapter; a bit more involved, like a NAND or NOR flash
1022 controller driver; or a big piece of work like supporting
1023 a new chip architecture.
1026 Reuse the existing config files when you can.
1027 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1028 You may find a board configuration that's a good example to follow.
1030 When you write config files, separate the reusable parts
1031 (things every user of that interface, chip, or board needs)
1032 from ones specific to your environment and debugging approach.
1036 For example, a @code{gdb-attach} event handler that invokes
1037 the @command{reset init} command will interfere with debugging
1038 early boot code, which performs some of the same actions
1039 that the @code{reset-init} event handler does.
1042 Likewise, the @command{arm9 vector_catch} command (or
1043 @cindex vector_catch
1044 its siblings @command{xscale vector_catch}
1045 and @command{cortex_m vector_catch}) can be a time-saver
1046 during some debug sessions, but don't make everyone use that either.
1047 Keep those kinds of debugging aids in your user config file,
1048 along with messaging and tracing setup.
1049 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1052 You might need to override some defaults.
1053 For example, you might need to move, shrink, or back up the target's
1054 work area if your application needs much SRAM.
1057 TCP/IP port configuration is another example of something which
1058 is environment-specific, and should only appear in
1059 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1062 @section Project-Specific Utilities
1064 A few project-specific utility
1065 routines may well speed up your work.
1066 Write them, and keep them in your project's user config file.
1068 For example, if you are making a boot loader work on a
1069 board, it's nice to be able to debug the ``after it's
1070 loaded to RAM'' parts separately from the finicky early
1071 code which sets up the DDR RAM controller and clocks.
1072 A script like this one, or a more GDB-aware sibling,
1076 proc ramboot @{ @} @{
1077 # Reset, running the target's "reset-init" scripts
1078 # to initialize clocks and the DDR RAM controller.
1079 # Leave the CPU halted.
1082 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1083 load_image u-boot.bin 0x20000000
1090 Then once that code is working you will need to make it
1091 boot from NOR flash; a different utility would help.
1092 Alternatively, some developers write to flash using GDB.
1093 (You might use a similar script if you're working with a flash
1094 based microcontroller application instead of a boot loader.)
1097 proc newboot @{ @} @{
1098 # Reset, leaving the CPU halted. The "reset-init" event
1099 # proc gives faster access to the CPU and to NOR flash;
1100 # "reset halt" would be slower.
1103 # Write standard version of U-Boot into the first two
1104 # sectors of NOR flash ... the standard version should
1105 # do the same lowlevel init as "reset-init".
1106 flash protect 0 0 1 off
1107 flash erase_sector 0 0 1
1108 flash write_bank 0 u-boot.bin 0x0
1109 flash protect 0 0 1 on
1111 # Reboot from scratch using that new boot loader.
1116 You may need more complicated utility procedures when booting
1118 That often involves an extra bootloader stage,
1119 running from on-chip SRAM to perform DDR RAM setup so it can load
1120 the main bootloader code (which won't fit into that SRAM).
1122 Other helper scripts might be used to write production system images,
1123 involving considerably more than just a three stage bootloader.
1125 @section Target Software Changes
1127 Sometimes you may want to make some small changes to the software
1128 you're developing, to help make JTAG debugging work better.
1129 For example, in C or assembly language code you might
1130 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1131 handling issues like:
1135 @item @b{Watchdog Timers}...
1136 Watchdog timers are typically used to automatically reset systems if
1137 some application task doesn't periodically reset the timer. (The
1138 assumption is that the system has locked up if the task can't run.)
1139 When a JTAG debugger halts the system, that task won't be able to run
1140 and reset the timer ... potentially causing resets in the middle of
1141 your debug sessions.
1143 It's rarely a good idea to disable such watchdogs, since their usage
1144 needs to be debugged just like all other parts of your firmware.
1145 That might however be your only option.
1147 Look instead for chip-specific ways to stop the watchdog from counting
1148 while the system is in a debug halt state. It may be simplest to set
1149 that non-counting mode in your debugger startup scripts. You may however
1150 need a different approach when, for example, a motor could be physically
1151 damaged by firmware remaining inactive in a debug halt state. That might
1152 involve a type of firmware mode where that "non-counting" mode is disabled
1153 at the beginning then re-enabled at the end; a watchdog reset might fire
1154 and complicate the debug session, but hardware (or people) would be
1155 protected.@footnote{Note that many systems support a "monitor mode" debug
1156 that is a somewhat cleaner way to address such issues. You can think of
1157 it as only halting part of the system, maybe just one task,
1158 instead of the whole thing.
1159 At this writing, January 2010, OpenOCD based debugging does not support
1160 monitor mode debug, only "halt mode" debug.}
1162 @item @b{ARM Semihosting}...
1163 @cindex ARM semihosting
1164 When linked with a special runtime library provided with many
1165 toolchains@footnote{See chapter 8 "Semihosting" in
1166 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1167 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1168 The CodeSourcery EABI toolchain also includes a semihosting library.},
1169 your target code can use I/O facilities on the debug host. That library
1170 provides a small set of system calls which are handled by OpenOCD.
1171 It can let the debugger provide your system console and a file system,
1172 helping with early debugging or providing a more capable environment
1173 for sometimes-complex tasks like installing system firmware onto
1176 @item @b{ARM Wait-For-Interrupt}...
1177 Many ARM chips synchronize the JTAG clock using the core clock.
1178 Low power states which stop that core clock thus prevent JTAG access.
1179 Idle loops in tasking environments often enter those low power states
1180 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1182 You may want to @emph{disable that instruction} in source code,
1183 or otherwise prevent using that state,
1184 to ensure you can get JTAG access at any time.@footnote{As a more
1185 polite alternative, some processors have special debug-oriented
1186 registers which can be used to change various features including
1187 how the low power states are clocked while debugging.
1188 The STM32 DBGMCU_CR register is an example; at the cost of extra
1189 power consumption, JTAG can be used during low power states.}
1190 For example, the OpenOCD @command{halt} command may not
1191 work for an idle processor otherwise.
1193 @item @b{Delay after reset}...
1194 Not all chips have good support for debugger access
1195 right after reset; many LPC2xxx chips have issues here.
1196 Similarly, applications that reconfigure pins used for
1197 JTAG access as they start will also block debugger access.
1199 To work with boards like this, @emph{enable a short delay loop}
1200 the first thing after reset, before "real" startup activities.
1201 For example, one second's delay is usually more than enough
1202 time for a JTAG debugger to attach, so that
1203 early code execution can be debugged
1204 or firmware can be replaced.
1206 @item @b{Debug Communications Channel (DCC)}...
1207 Some processors include mechanisms to send messages over JTAG.
1208 Many ARM cores support these, as do some cores from other vendors.
1209 (OpenOCD may be able to use this DCC internally, speeding up some
1210 operations like writing to memory.)
1212 Your application may want to deliver various debugging messages
1213 over JTAG, by @emph{linking with a small library of code}
1214 provided with OpenOCD and using the utilities there to send
1215 various kinds of message.
1216 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1220 @section Target Hardware Setup
1222 Chip vendors often provide software development boards which
1223 are highly configurable, so that they can support all options
1224 that product boards may require. @emph{Make sure that any
1225 jumpers or switches match the system configuration you are
1228 Common issues include:
1232 @item @b{JTAG setup} ...
1233 Boards may support more than one JTAG configuration.
1234 Examples include jumpers controlling pullups versus pulldowns
1235 on the nTRST and/or nSRST signals, and choice of connectors
1236 (e.g. which of two headers on the base board,
1237 or one from a daughtercard).
1238 For some Texas Instruments boards, you may need to jumper the
1239 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1241 @item @b{Boot Modes} ...
1242 Complex chips often support multiple boot modes, controlled
1243 by external jumpers. Make sure this is set up correctly.
1244 For example many i.MX boards from NXP need to be jumpered
1245 to "ATX mode" to start booting using the on-chip ROM, when
1246 using second stage bootloader code stored in a NAND flash chip.
1248 Such explicit configuration is common, and not limited to
1249 booting from NAND. You might also need to set jumpers to
1250 start booting using code loaded from an MMC/SD card; external
1251 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1252 flash; some external host; or various other sources.
1255 @item @b{Memory Addressing} ...
1256 Boards which support multiple boot modes may also have jumpers
1257 to configure memory addressing. One board, for example, jumpers
1258 external chipselect 0 (used for booting) to address either
1259 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1260 or NAND flash. When it's jumpered to address NAND flash, that
1261 board must also be told to start booting from on-chip ROM.
1263 Your @file{board.cfg} file may also need to be told this jumper
1264 configuration, so that it can know whether to declare NOR flash
1265 using @command{flash bank} or instead declare NAND flash with
1266 @command{nand device}; and likewise which probe to perform in
1267 its @code{reset-init} handler.
1269 A closely related issue is bus width. Jumpers might need to
1270 distinguish between 8 bit or 16 bit bus access for the flash
1271 used to start booting.
1273 @item @b{Peripheral Access} ...
1274 Development boards generally provide access to every peripheral
1275 on the chip, sometimes in multiple modes (such as by providing
1276 multiple audio codec chips).
1277 This interacts with software
1278 configuration of pin multiplexing, where for example a
1279 given pin may be routed either to the MMC/SD controller
1280 or the GPIO controller. It also often interacts with
1281 configuration jumpers. One jumper may be used to route
1282 signals to an MMC/SD card slot or an expansion bus (which
1283 might in turn affect booting); others might control which
1284 audio or video codecs are used.
1288 Plus you should of course have @code{reset-init} event handlers
1289 which set up the hardware to match that jumper configuration.
1290 That includes in particular any oscillator or PLL used to clock
1291 the CPU, and any memory controllers needed to access external
1292 memory and peripherals. Without such handlers, you won't be
1293 able to access those resources without working target firmware
1294 which can do that setup ... this can be awkward when you're
1295 trying to debug that target firmware. Even if there's a ROM
1296 bootloader which handles a few issues, it rarely provides full
1297 access to all board-specific capabilities.
1300 @node Config File Guidelines
1301 @chapter Config File Guidelines
1303 This chapter is aimed at any user who needs to write a config file,
1304 including developers and integrators of OpenOCD and any user who
1305 needs to get a new board working smoothly.
1306 It provides guidelines for creating those files.
1308 You should find the following directories under
1309 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1310 them as-is where you can; or as models for new files.
1312 @item @file{interface} ...
1313 These are for debug adapters. Files that specify configuration to use
1314 specific JTAG, SWD and other adapters go here.
1315 @item @file{board} ...
1316 Think Circuit Board, PWA, PCB, they go by many names. Board files
1317 contain initialization items that are specific to a board.
1319 They reuse target configuration files, since the same
1320 microprocessor chips are used on many boards,
1321 but support for external parts varies widely. For
1322 example, the SDRAM initialization sequence for the board, or the type
1323 of external flash and what address it uses. Any initialization
1324 sequence to enable that external flash or SDRAM should be found in the
1325 board file. Boards may also contain multiple targets: two CPUs; or
1327 @item @file{target} ...
1328 Think chip. The ``target'' directory represents the JTAG TAPs
1330 which OpenOCD should control, not a board. Two common types of targets
1331 are ARM chips and FPGA or CPLD chips.
1332 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1333 the target config file defines all of them.
1334 @item @emph{more} ... browse for other library files which may be useful.
1335 For example, there are various generic and CPU-specific utilities.
1338 The @file{openocd.cfg} user config
1339 file may override features in any of the above files by
1340 setting variables before sourcing the target file, or by adding
1341 commands specific to their situation.
1343 @section Interface Config Files
1345 The user config file
1346 should be able to source one of these files with a command like this:
1349 source [find interface/FOOBAR.cfg]
1352 A preconfigured interface file should exist for every debug adapter
1353 in use today with OpenOCD.
1354 That said, perhaps some of these config files
1355 have only been used by the developer who created it.
1357 A separate chapter gives information about how to set these up.
1358 @xref{Debug Adapter Configuration}.
1359 Read the OpenOCD source code (and Developer's Guide)
1360 if you have a new kind of hardware interface
1361 and need to provide a driver for it.
1363 @section Board Config Files
1364 @cindex config file, board
1365 @cindex board config file
1367 The user config file
1368 should be able to source one of these files with a command like this:
1371 source [find board/FOOBAR.cfg]
1374 The point of a board config file is to package everything
1375 about a given board that user config files need to know.
1376 In summary the board files should contain (if present)
1379 @item One or more @command{source [find target/...cfg]} statements
1380 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1381 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1382 @item Target @code{reset} handlers for SDRAM and I/O configuration
1383 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1384 @item All things that are not ``inside a chip''
1387 Generic things inside target chips belong in target config files,
1388 not board config files. So for example a @code{reset-init} event
1389 handler should know board-specific oscillator and PLL parameters,
1390 which it passes to target-specific utility code.
1392 The most complex task of a board config file is creating such a
1393 @code{reset-init} event handler.
1394 Define those handlers last, after you verify the rest of the board
1395 configuration works.
1397 @subsection Communication Between Config files
1399 In addition to target-specific utility code, another way that
1400 board and target config files communicate is by following a
1401 convention on how to use certain variables.
1403 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1404 Thus the rule we follow in OpenOCD is this: Variables that begin with
1405 a leading underscore are temporary in nature, and can be modified and
1406 used at will within a target configuration file.
1408 Complex board config files can do the things like this,
1409 for a board with three chips:
1412 # Chip #1: PXA270 for network side, big endian
1413 set CHIPNAME network
1415 source [find target/pxa270.cfg]
1416 # on return: _TARGETNAME = network.cpu
1417 # other commands can refer to the "network.cpu" target.
1418 $_TARGETNAME configure .... events for this CPU..
1420 # Chip #2: PXA270 for video side, little endian
1423 source [find target/pxa270.cfg]
1424 # on return: _TARGETNAME = video.cpu
1425 # other commands can refer to the "video.cpu" target.
1426 $_TARGETNAME configure .... events for this CPU..
1428 # Chip #3: Xilinx FPGA for glue logic
1431 source [find target/spartan3.cfg]
1434 That example is oversimplified because it doesn't show any flash memory,
1435 or the @code{reset-init} event handlers to initialize external DRAM
1436 or (assuming it needs it) load a configuration into the FPGA.
1437 Such features are usually needed for low-level work with many boards,
1438 where ``low level'' implies that the board initialization software may
1439 not be working. (That's a common reason to need JTAG tools. Another
1440 is to enable working with microcontroller-based systems, which often
1441 have no debugging support except a JTAG connector.)
1443 Target config files may also export utility functions to board and user
1444 config files. Such functions should use name prefixes, to help avoid
1447 Board files could also accept input variables from user config files.
1448 For example, there might be a @code{J4_JUMPER} setting used to identify
1449 what kind of flash memory a development board is using, or how to set
1450 up other clocks and peripherals.
1452 @subsection Variable Naming Convention
1453 @cindex variable names
1455 Most boards have only one instance of a chip.
1456 However, it should be easy to create a board with more than
1457 one such chip (as shown above).
1458 Accordingly, we encourage these conventions for naming
1459 variables associated with different @file{target.cfg} files,
1460 to promote consistency and
1461 so that board files can override target defaults.
1463 Inputs to target config files include:
1466 @item @code{CHIPNAME} ...
1467 This gives a name to the overall chip, and is used as part of
1468 tap identifier dotted names.
1469 While the default is normally provided by the chip manufacturer,
1470 board files may need to distinguish between instances of a chip.
1471 @item @code{ENDIAN} ...
1472 By default @option{little} - although chips may hard-wire @option{big}.
1473 Chips that can't change endianess don't need to use this variable.
1474 @item @code{CPUTAPID} ...
1475 When OpenOCD examines the JTAG chain, it can be told verify the
1476 chips against the JTAG IDCODE register.
1477 The target file will hold one or more defaults, but sometimes the
1478 chip in a board will use a different ID (perhaps a newer revision).
1481 Outputs from target config files include:
1484 @item @code{_TARGETNAME} ...
1485 By convention, this variable is created by the target configuration
1486 script. The board configuration file may make use of this variable to
1487 configure things like a ``reset init'' script, or other things
1488 specific to that board and that target.
1489 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1490 @code{_TARGETNAME1}, ... etc.
1493 @subsection The reset-init Event Handler
1494 @cindex event, reset-init
1495 @cindex reset-init handler
1497 Board config files run in the OpenOCD configuration stage;
1498 they can't use TAPs or targets, since they haven't been
1500 This means you can't write memory or access chip registers;
1501 you can't even verify that a flash chip is present.
1502 That's done later in event handlers, of which the target @code{reset-init}
1503 handler is one of the most important.
1505 Except on microcontrollers, the basic job of @code{reset-init} event
1506 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1507 Microcontrollers rarely use boot loaders; they run right out of their
1508 on-chip flash and SRAM memory. But they may want to use one of these
1509 handlers too, if just for developer convenience.
1512 Because this is so very board-specific, and chip-specific, no examples
1514 Instead, look at the board config files distributed with OpenOCD.
1515 If you have a boot loader, its source code will help; so will
1516 configuration files for other JTAG tools
1517 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1520 Some of this code could probably be shared between different boards.
1521 For example, setting up a DRAM controller often doesn't differ by
1522 much except the bus width (16 bits or 32?) and memory timings, so a
1523 reusable TCL procedure loaded by the @file{target.cfg} file might take
1524 those as parameters.
1525 Similarly with oscillator, PLL, and clock setup;
1526 and disabling the watchdog.
1527 Structure the code cleanly, and provide comments to help
1528 the next developer doing such work.
1529 (@emph{You might be that next person} trying to reuse init code!)
1531 The last thing normally done in a @code{reset-init} handler is probing
1532 whatever flash memory was configured. For most chips that needs to be
1533 done while the associated target is halted, either because JTAG memory
1534 access uses the CPU or to prevent conflicting CPU access.
1536 @subsection JTAG Clock Rate
1538 Before your @code{reset-init} handler has set up
1539 the PLLs and clocking, you may need to run with
1540 a low JTAG clock rate.
1541 @xref{jtagspeed,,JTAG Speed}.
1542 Then you'd increase that rate after your handler has
1543 made it possible to use the faster JTAG clock.
1544 When the initial low speed is board-specific, for example
1545 because it depends on a board-specific oscillator speed, then
1546 you should probably set it up in the board config file;
1547 if it's target-specific, it belongs in the target config file.
1549 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1550 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1551 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1552 Consult chip documentation to determine the peak JTAG clock rate,
1553 which might be less than that.
1556 On most ARMs, JTAG clock detection is coupled to the core clock, so
1557 software using a @option{wait for interrupt} operation blocks JTAG access.
1558 Adaptive clocking provides a partial workaround, but a more complete
1559 solution just avoids using that instruction with JTAG debuggers.
1562 If both the chip and the board support adaptive clocking,
1563 use the @command{jtag_rclk}
1564 command, in case your board is used with JTAG adapter which
1565 also supports it. Otherwise use @command{adapter_khz}.
1566 Set the slow rate at the beginning of the reset sequence,
1567 and the faster rate as soon as the clocks are at full speed.
1569 @anchor{theinitboardprocedure}
1570 @subsection The init_board procedure
1571 @cindex init_board procedure
1573 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1574 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1575 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1576 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1577 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1578 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1579 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1580 Additionally ``linear'' board config file will most likely fail when target config file uses
1581 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1582 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1583 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1584 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1586 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1587 the original), allowing greater code reuse.
1590 ### board_file.cfg ###
1592 # source target file that does most of the config in init_targets
1593 source [find target/target.cfg]
1595 proc enable_fast_clock @{@} @{
1596 # enables fast on-board clock source
1597 # configures the chip to use it
1600 # initialize only board specifics - reset, clock, adapter frequency
1601 proc init_board @{@} @{
1602 reset_config trst_and_srst trst_pulls_srst
1604 $_TARGETNAME configure -event reset-start @{
1608 $_TARGETNAME configure -event reset-init @{
1615 @section Target Config Files
1616 @cindex config file, target
1617 @cindex target config file
1619 Board config files communicate with target config files using
1620 naming conventions as described above, and may source one or
1621 more target config files like this:
1624 source [find target/FOOBAR.cfg]
1627 The point of a target config file is to package everything
1628 about a given chip that board config files need to know.
1629 In summary the target files should contain
1633 @item Add TAPs to the scan chain
1634 @item Add CPU targets (includes GDB support)
1635 @item CPU/Chip/CPU-Core specific features
1639 As a rule of thumb, a target file sets up only one chip.
1640 For a microcontroller, that will often include a single TAP,
1641 which is a CPU needing a GDB target, and its on-chip flash.
1643 More complex chips may include multiple TAPs, and the target
1644 config file may need to define them all before OpenOCD
1645 can talk to the chip.
1646 For example, some phone chips have JTAG scan chains that include
1647 an ARM core for operating system use, a DSP,
1648 another ARM core embedded in an image processing engine,
1649 and other processing engines.
1651 @subsection Default Value Boiler Plate Code
1653 All target configuration files should start with code like this,
1654 letting board config files express environment-specific
1655 differences in how things should be set up.
1658 # Boards may override chip names, perhaps based on role,
1659 # but the default should match what the vendor uses
1660 if @{ [info exists CHIPNAME] @} @{
1661 set _CHIPNAME $CHIPNAME
1663 set _CHIPNAME sam7x256
1666 # ONLY use ENDIAN with targets that can change it.
1667 if @{ [info exists ENDIAN] @} @{
1673 # TAP identifiers may change as chips mature, for example with
1674 # new revision fields (the "3" here). Pick a good default; you
1675 # can pass several such identifiers to the "jtag newtap" command.
1676 if @{ [info exists CPUTAPID ] @} @{
1677 set _CPUTAPID $CPUTAPID
1679 set _CPUTAPID 0x3f0f0f0f
1682 @c but 0x3f0f0f0f is for an str73x part ...
1684 @emph{Remember:} Board config files may include multiple target
1685 config files, or the same target file multiple times
1686 (changing at least @code{CHIPNAME}).
1688 Likewise, the target configuration file should define
1689 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1690 use it later on when defining debug targets:
1693 set _TARGETNAME $_CHIPNAME.cpu
1694 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1697 @subsection Adding TAPs to the Scan Chain
1698 After the ``defaults'' are set up,
1699 add the TAPs on each chip to the JTAG scan chain.
1700 @xref{TAP Declaration}, and the naming convention
1703 In the simplest case the chip has only one TAP,
1704 probably for a CPU or FPGA.
1705 The config file for the Atmel AT91SAM7X256
1706 looks (in part) like this:
1709 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1712 A board with two such at91sam7 chips would be able
1713 to source such a config file twice, with different
1714 values for @code{CHIPNAME}, so
1715 it adds a different TAP each time.
1717 If there are nonzero @option{-expected-id} values,
1718 OpenOCD attempts to verify the actual tap id against those values.
1719 It will issue error messages if there is mismatch, which
1720 can help to pinpoint problems in OpenOCD configurations.
1723 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1724 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1725 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1726 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1727 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1730 There are more complex examples too, with chips that have
1731 multiple TAPs. Ones worth looking at include:
1734 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1735 plus a JRC to enable them
1736 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1737 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1738 is not currently used)
1741 @subsection Add CPU targets
1743 After adding a TAP for a CPU, you should set it up so that
1744 GDB and other commands can use it.
1745 @xref{CPU Configuration}.
1746 For the at91sam7 example above, the command can look like this;
1747 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1748 to little endian, and this chip doesn't support changing that.
1751 set _TARGETNAME $_CHIPNAME.cpu
1752 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1755 Work areas are small RAM areas associated with CPU targets.
1756 They are used by OpenOCD to speed up downloads,
1757 and to download small snippets of code to program flash chips.
1758 If the chip includes a form of ``on-chip-ram'' - and many do - define
1759 a work area if you can.
1760 Again using the at91sam7 as an example, this can look like:
1763 $_TARGETNAME configure -work-area-phys 0x00200000 \
1764 -work-area-size 0x4000 -work-area-backup 0
1767 @anchor{definecputargetsworkinginsmp}
1768 @subsection Define CPU targets working in SMP
1770 After setting targets, you can define a list of targets working in SMP.
1773 set _TARGETNAME_1 $_CHIPNAME.cpu1
1774 set _TARGETNAME_2 $_CHIPNAME.cpu2
1775 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1776 -coreid 0 -dbgbase $_DAP_DBG1
1777 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1778 -coreid 1 -dbgbase $_DAP_DBG2
1779 #define 2 targets working in smp.
1780 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1782 In the above example on cortex_a, 2 cpus are working in SMP.
1783 In SMP only one GDB instance is created and :
1785 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1786 @item halt command triggers the halt of all targets in the list.
1787 @item resume command triggers the write context and the restart of all targets in the list.
1788 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1789 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1790 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1793 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1794 command have been implemented.
1796 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1797 @item cortex_a smp_off : disable SMP mode, the current target is the one
1798 displayed in the GDB session, only this target is now controlled by GDB
1799 session. This behaviour is useful during system boot up.
1800 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1807 #0 : coreid 0 is displayed to GDB ,
1808 #-> -1 : next resume triggers a real resume
1809 > cortex_a smp_gdb 1
1811 #0 :coreid 0 is displayed to GDB ,
1812 #->1 : next resume displays coreid 1 to GDB
1816 #1 :coreid 1 is displayed to GDB ,
1817 #->1 : next resume displays coreid 1 to GDB
1818 > cortex_a smp_gdb -1
1820 #1 :coreid 1 is displayed to GDB,
1821 #->-1 : next resume triggers a real resume
1825 @subsection Chip Reset Setup
1827 As a rule, you should put the @command{reset_config} command
1828 into the board file. Most things you think you know about a
1829 chip can be tweaked by the board.
1831 Some chips have specific ways the TRST and SRST signals are
1832 managed. In the unusual case that these are @emph{chip specific}
1833 and can never be changed by board wiring, they could go here.
1834 For example, some chips can't support JTAG debugging without
1837 Provide a @code{reset-assert} event handler if you can.
1838 Such a handler uses JTAG operations to reset the target,
1839 letting this target config be used in systems which don't
1840 provide the optional SRST signal, or on systems where you
1841 don't want to reset all targets at once.
1842 Such a handler might write to chip registers to force a reset,
1843 use a JRC to do that (preferable -- the target may be wedged!),
1844 or force a watchdog timer to trigger.
1845 (For Cortex-M targets, this is not necessary. The target
1846 driver knows how to use trigger an NVIC reset when SRST is
1849 Some chips need special attention during reset handling if
1850 they're going to be used with JTAG.
1851 An example might be needing to send some commands right
1852 after the target's TAP has been reset, providing a
1853 @code{reset-deassert-post} event handler that writes a chip
1854 register to report that JTAG debugging is being done.
1855 Another would be reconfiguring the watchdog so that it stops
1856 counting while the core is halted in the debugger.
1858 JTAG clocking constraints often change during reset, and in
1859 some cases target config files (rather than board config files)
1860 are the right places to handle some of those issues.
1861 For example, immediately after reset most chips run using a
1862 slower clock than they will use later.
1863 That means that after reset (and potentially, as OpenOCD
1864 first starts up) they must use a slower JTAG clock rate
1865 than they will use later.
1866 @xref{jtagspeed,,JTAG Speed}.
1868 @quotation Important
1869 When you are debugging code that runs right after chip
1870 reset, getting these issues right is critical.
1871 In particular, if you see intermittent failures when
1872 OpenOCD verifies the scan chain after reset,
1873 look at how you are setting up JTAG clocking.
1876 @anchor{theinittargetsprocedure}
1877 @subsection The init_targets procedure
1878 @cindex init_targets procedure
1880 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1881 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1882 procedure called @code{init_targets}, which will be executed when entering run stage
1883 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1884 Such procedure can be overridden by ``next level'' script (which sources the original).
1885 This concept facilitates code reuse when basic target config files provide generic configuration
1886 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1887 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1888 because sourcing them executes every initialization commands they provide.
1891 ### generic_file.cfg ###
1893 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1894 # basic initialization procedure ...
1897 proc init_targets @{@} @{
1898 # initializes generic chip with 4kB of flash and 1kB of RAM
1899 setup_my_chip MY_GENERIC_CHIP 4096 1024
1902 ### specific_file.cfg ###
1904 source [find target/generic_file.cfg]
1906 proc init_targets @{@} @{
1907 # initializes specific chip with 128kB of flash and 64kB of RAM
1908 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1912 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1913 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1915 For an example of this scheme see LPC2000 target config files.
1917 The @code{init_boards} procedure is a similar concept concerning board config files
1918 (@xref{theinitboardprocedure,,The init_board procedure}.)
1920 @anchor{theinittargeteventsprocedure}
1921 @subsection The init_target_events procedure
1922 @cindex init_target_events procedure
1924 A special procedure called @code{init_target_events} is run just after
1925 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1926 procedure}.) and before @code{init_board}
1927 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1928 to set up default target events for the targets that do not have those
1929 events already assigned.
1931 @subsection ARM Core Specific Hacks
1933 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1934 special high speed download features - enable it.
1936 If present, the MMU, the MPU and the CACHE should be disabled.
1938 Some ARM cores are equipped with trace support, which permits
1939 examination of the instruction and data bus activity. Trace
1940 activity is controlled through an ``Embedded Trace Module'' (ETM)
1941 on one of the core's scan chains. The ETM emits voluminous data
1942 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1943 If you are using an external trace port,
1944 configure it in your board config file.
1945 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1946 configure it in your target config file.
1949 etm config $_TARGETNAME 16 normal full etb
1950 etb config $_TARGETNAME $_CHIPNAME.etb
1953 @subsection Internal Flash Configuration
1955 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1957 @b{Never ever} in the ``target configuration file'' define any type of
1958 flash that is external to the chip. (For example a BOOT flash on
1959 Chip Select 0.) Such flash information goes in a board file - not
1960 the TARGET (chip) file.
1964 @item at91sam7x256 - has 256K flash YES enable it.
1965 @item str912 - has flash internal YES enable it.
1966 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1967 @item pxa270 - again - CS0 flash - it goes in the board file.
1970 @anchor{translatingconfigurationfiles}
1971 @section Translating Configuration Files
1973 If you have a configuration file for another hardware debugger
1974 or toolset (Abatron, BDI2000, BDI3000, CCS,
1975 Lauterbach, SEGGER, Macraigor, etc.), translating
1976 it into OpenOCD syntax is often quite straightforward. The most tricky
1977 part of creating a configuration script is oftentimes the reset init
1978 sequence where e.g. PLLs, DRAM and the like is set up.
1980 One trick that you can use when translating is to write small
1981 Tcl procedures to translate the syntax into OpenOCD syntax. This
1982 can avoid manual translation errors and make it easier to
1983 convert other scripts later on.
1985 Example of transforming quirky arguments to a simple search and
1989 # Lauterbach syntax(?)
1991 # Data.Set c15:0x042f %long 0x40000015
1993 # OpenOCD syntax when using procedure below.
1995 # setc15 0x01 0x00050078
1997 proc setc15 @{regs value@} @{
2000 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2002 arm mcr 15 [expr ($regs>>12)&0x7] \
2003 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2004 [expr ($regs>>8)&0x7] $value
2010 @node Server Configuration
2011 @chapter Server Configuration
2012 @cindex initialization
2013 The commands here are commonly found in the openocd.cfg file and are
2014 used to specify what TCP/IP ports are used, and how GDB should be
2017 @anchor{configurationstage}
2018 @section Configuration Stage
2019 @cindex configuration stage
2020 @cindex config command
2022 When the OpenOCD server process starts up, it enters a
2023 @emph{configuration stage} which is the only time that
2024 certain commands, @emph{configuration commands}, may be issued.
2025 Normally, configuration commands are only available
2026 inside startup scripts.
2028 In this manual, the definition of a configuration command is
2029 presented as a @emph{Config Command}, not as a @emph{Command}
2030 which may be issued interactively.
2031 The runtime @command{help} command also highlights configuration
2032 commands, and those which may be issued at any time.
2034 Those configuration commands include declaration of TAPs,
2036 the interface used for JTAG communication,
2037 and other basic setup.
2038 The server must leave the configuration stage before it
2039 may access or activate TAPs.
2040 After it leaves this stage, configuration commands may no
2043 @anchor{enteringtherunstage}
2044 @section Entering the Run Stage
2046 The first thing OpenOCD does after leaving the configuration
2047 stage is to verify that it can talk to the scan chain
2048 (list of TAPs) which has been configured.
2049 It will warn if it doesn't find TAPs it expects to find,
2050 or finds TAPs that aren't supposed to be there.
2051 You should see no errors at this point.
2052 If you see errors, resolve them by correcting the
2053 commands you used to configure the server.
2054 Common errors include using an initial JTAG speed that's too
2055 fast, and not providing the right IDCODE values for the TAPs
2058 Once OpenOCD has entered the run stage, a number of commands
2060 A number of these relate to the debug targets you may have declared.
2061 For example, the @command{mww} command will not be available until
2062 a target has been successfully instantiated.
2063 If you want to use those commands, you may need to force
2064 entry to the run stage.
2066 @deffn {Config Command} init
2067 This command terminates the configuration stage and
2068 enters the run stage. This helps when you need to have
2069 the startup scripts manage tasks such as resetting the target,
2070 programming flash, etc. To reset the CPU upon startup, add "init" and
2071 "reset" at the end of the config script or at the end of the OpenOCD
2072 command line using the @option{-c} command line switch.
2074 If this command does not appear in any startup/configuration file
2075 OpenOCD executes the command for you after processing all
2076 configuration files and/or command line options.
2078 @b{NOTE:} This command normally occurs at or near the end of your
2079 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2080 targets ready. For example: If your openocd.cfg file needs to
2081 read/write memory on your target, @command{init} must occur before
2082 the memory read/write commands. This includes @command{nand probe}.
2085 @deffn {Overridable Procedure} jtag_init
2086 This is invoked at server startup to verify that it can talk
2087 to the scan chain (list of TAPs) which has been configured.
2089 The default implementation first tries @command{jtag arp_init},
2090 which uses only a lightweight JTAG reset before examining the
2092 If that fails, it tries again, using a harder reset
2093 from the overridable procedure @command{init_reset}.
2095 Implementations must have verified the JTAG scan chain before
2097 This is done by calling @command{jtag arp_init}
2098 (or @command{jtag arp_init-reset}).
2102 @section TCP/IP Ports
2107 The OpenOCD server accepts remote commands in several syntaxes.
2108 Each syntax uses a different TCP/IP port, which you may specify
2109 only during configuration (before those ports are opened).
2111 For reasons including security, you may wish to prevent remote
2112 access using one or more of these ports.
2113 In such cases, just specify the relevant port number as "disabled".
2114 If you disable all access through TCP/IP, you will need to
2115 use the command line @option{-pipe} option.
2117 @deffn {Command} gdb_port [number]
2119 Normally gdb listens to a TCP/IP port, but GDB can also
2120 communicate via pipes(stdin/out or named pipes). The name
2121 "gdb_port" stuck because it covers probably more than 90% of
2122 the normal use cases.
2124 No arguments reports GDB port. "pipe" means listen to stdin
2125 output to stdout, an integer is base port number, "disabled"
2126 disables the gdb server.
2128 When using "pipe", also use log_output to redirect the log
2129 output to a file so as not to flood the stdin/out pipes.
2131 The -p/--pipe option is deprecated and a warning is printed
2132 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2134 Any other string is interpreted as named pipe to listen to.
2135 Output pipe is the same name as input pipe, but with 'o' appended,
2136 e.g. /var/gdb, /var/gdbo.
2138 The GDB port for the first target will be the base port, the
2139 second target will listen on gdb_port + 1, and so on.
2140 When not specified during the configuration stage,
2141 the port @var{number} defaults to 3333.
2143 Note: when using "gdb_port pipe", increasing the default remote timeout in
2144 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2145 cause initialization to fail with "Unknown remote qXfer reply: OK".
2149 @deffn {Command} tcl_port [number]
2150 Specify or query the port used for a simplified RPC
2151 connection that can be used by clients to issue TCL commands and get the
2152 output from the Tcl engine.
2153 Intended as a machine interface.
2154 When not specified during the configuration stage,
2155 the port @var{number} defaults to 6666.
2156 When specified as "disabled", this service is not activated.
2159 @deffn {Command} telnet_port [number]
2160 Specify or query the
2161 port on which to listen for incoming telnet connections.
2162 This port is intended for interaction with one human through TCL commands.
2163 When not specified during the configuration stage,
2164 the port @var{number} defaults to 4444.
2165 When specified as "disabled", this service is not activated.
2168 @anchor{gdbconfiguration}
2169 @section GDB Configuration
2171 @cindex GDB configuration
2172 You can reconfigure some GDB behaviors if needed.
2173 The ones listed here are static and global.
2174 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2175 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2177 @anchor{gdbbreakpointoverride}
2178 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2179 Force breakpoint type for gdb @command{break} commands.
2180 This option supports GDB GUIs which don't
2181 distinguish hard versus soft breakpoints, if the default OpenOCD and
2182 GDB behaviour is not sufficient. GDB normally uses hardware
2183 breakpoints if the memory map has been set up for flash regions.
2186 @anchor{gdbflashprogram}
2187 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2188 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2189 vFlash packet is received.
2190 The default behaviour is @option{enable}.
2193 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2194 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2195 requested. GDB will then know when to set hardware breakpoints, and program flash
2196 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2197 for flash programming to work.
2198 Default behaviour is @option{enable}.
2199 @xref{gdbflashprogram,,gdb_flash_program}.
2202 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2203 Specifies whether data aborts cause an error to be reported
2204 by GDB memory read packets.
2205 The default behaviour is @option{disable};
2206 use @option{enable} see these errors reported.
2209 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2210 Specifies whether register accesses requested by GDB register read/write
2211 packets report errors or not.
2212 The default behaviour is @option{disable};
2213 use @option{enable} see these errors reported.
2216 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2217 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2218 The default behaviour is @option{enable}.
2221 @deffn {Command} gdb_save_tdesc
2222 Saves the target description file to the local file system.
2224 The file name is @i{target_name}.xml.
2227 @anchor{eventpolling}
2228 @section Event Polling
2230 Hardware debuggers are parts of asynchronous systems,
2231 where significant events can happen at any time.
2232 The OpenOCD server needs to detect some of these events,
2233 so it can report them to through TCL command line
2236 Examples of such events include:
2239 @item One of the targets can stop running ... maybe it triggers
2240 a code breakpoint or data watchpoint, or halts itself.
2241 @item Messages may be sent over ``debug message'' channels ... many
2242 targets support such messages sent over JTAG,
2243 for receipt by the person debugging or tools.
2244 @item Loss of power ... some adapters can detect these events.
2245 @item Resets not issued through JTAG ... such reset sources
2246 can include button presses or other system hardware, sometimes
2247 including the target itself (perhaps through a watchdog).
2248 @item Debug instrumentation sometimes supports event triggering
2249 such as ``trace buffer full'' (so it can quickly be emptied)
2250 or other signals (to correlate with code behavior).
2253 None of those events are signaled through standard JTAG signals.
2254 However, most conventions for JTAG connectors include voltage
2255 level and system reset (SRST) signal detection.
2256 Some connectors also include instrumentation signals, which
2257 can imply events when those signals are inputs.
2259 In general, OpenOCD needs to periodically check for those events,
2260 either by looking at the status of signals on the JTAG connector
2261 or by sending synchronous ``tell me your status'' JTAG requests
2262 to the various active targets.
2263 There is a command to manage and monitor that polling,
2264 which is normally done in the background.
2266 @deffn Command poll [@option{on}|@option{off}]
2267 Poll the current target for its current state.
2268 (Also, @pxref{targetcurstate,,target curstate}.)
2269 If that target is in debug mode, architecture
2270 specific information about the current state is printed.
2271 An optional parameter
2272 allows background polling to be enabled and disabled.
2274 You could use this from the TCL command shell, or
2275 from GDB using @command{monitor poll} command.
2276 Leave background polling enabled while you're using GDB.
2279 background polling: on
2280 target state: halted
2281 target halted in ARM state due to debug-request, \
2282 current mode: Supervisor
2283 cpsr: 0x800000d3 pc: 0x11081bfc
2284 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2289 @node Debug Adapter Configuration
2290 @chapter Debug Adapter Configuration
2291 @cindex config file, interface
2292 @cindex interface config file
2294 Correctly installing OpenOCD includes making your operating system give
2295 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2296 are used to select which one is used, and to configure how it is used.
2299 Because OpenOCD started out with a focus purely on JTAG, you may find
2300 places where it wrongly presumes JTAG is the only transport protocol
2301 in use. Be aware that recent versions of OpenOCD are removing that
2302 limitation. JTAG remains more functional than most other transports.
2303 Other transports do not support boundary scan operations, or may be
2304 specific to a given chip vendor. Some might be usable only for
2305 programming flash memory, instead of also for debugging.
2308 Debug Adapters/Interfaces/Dongles are normally configured
2309 through commands in an interface configuration
2310 file which is sourced by your @file{openocd.cfg} file, or
2311 through a command line @option{-f interface/....cfg} option.
2314 source [find interface/olimex-jtag-tiny.cfg]
2318 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2319 A few cases are so simple that you only need to say what driver to use:
2326 Most adapters need a bit more configuration than that.
2329 @section Interface Configuration
2331 The interface command tells OpenOCD what type of debug adapter you are
2332 using. Depending on the type of adapter, you may need to use one or
2333 more additional commands to further identify or configure the adapter.
2335 @deffn {Config Command} {interface} name
2336 Use the interface driver @var{name} to connect to the
2340 @deffn Command {interface_list}
2341 List the debug adapter drivers that have been built into
2342 the running copy of OpenOCD.
2344 @deffn Command {interface transports} transport_name+
2345 Specifies the transports supported by this debug adapter.
2346 The adapter driver builds-in similar knowledge; use this only
2347 when external configuration (such as jumpering) changes what
2348 the hardware can support.
2353 @deffn Command {adapter_name}
2354 Returns the name of the debug adapter driver being used.
2357 @section Interface Drivers
2359 Each of the interface drivers listed here must be explicitly
2360 enabled when OpenOCD is configured, in order to be made
2361 available at run time.
2363 @deffn {Interface Driver} {amt_jtagaccel}
2364 Amontec Chameleon in its JTAG Accelerator configuration,
2365 connected to a PC's EPP mode parallel port.
2366 This defines some driver-specific commands:
2368 @deffn {Config Command} {parport_port} number
2369 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2370 the number of the @file{/dev/parport} device.
2373 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2374 Displays status of RTCK option.
2375 Optionally sets that option first.
2379 @deffn {Interface Driver} {arm-jtag-ew}
2380 Olimex ARM-JTAG-EW USB adapter
2381 This has one driver-specific command:
2383 @deffn Command {armjtagew_info}
2388 @deffn {Interface Driver} {at91rm9200}
2389 Supports bitbanged JTAG from the local system,
2390 presuming that system is an Atmel AT91rm9200
2391 and a specific set of GPIOs is used.
2392 @c command: at91rm9200_device NAME
2393 @c chooses among list of bit configs ... only one option
2396 @deffn {Interface Driver} {cmsis-dap}
2397 ARM CMSIS-DAP compliant based adapter.
2399 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2400 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2401 the driver will attempt to auto detect the CMSIS-DAP device.
2402 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2404 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2408 @deffn {Config Command} {cmsis_dap_serial} [serial]
2409 Specifies the @var{serial} of the CMSIS-DAP device to use.
2410 If not specified, serial numbers are not considered.
2413 @deffn {Command} {cmsis-dap info}
2414 Display various device information, like hardware version, firmware version, current bus status.
2418 @deffn {Interface Driver} {dummy}
2419 A dummy software-only driver for debugging.
2422 @deffn {Interface Driver} {ep93xx}
2423 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2426 @deffn {Interface Driver} {ftdi}
2427 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2428 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2430 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2431 bypassing intermediate libraries like libftdi or D2XX.
2433 Support for new FTDI based adapters can be added completely through
2434 configuration files, without the need to patch and rebuild OpenOCD.
2436 The driver uses a signal abstraction to enable Tcl configuration files to
2437 define outputs for one or several FTDI GPIO. These outputs can then be
2438 controlled using the @command{ftdi_set_signal} command. Special signal names
2439 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2440 will be used for their customary purpose. Inputs can be read using the
2441 @command{ftdi_get_signal} command.
2443 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2444 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2445 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2446 required by the protocol, to tell the adapter to drive the data output onto
2447 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2449 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2450 be controlled differently. In order to support tristateable signals such as
2451 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2452 signal. The following output buffer configurations are supported:
2455 @item Push-pull with one FTDI output as (non-)inverted data line
2456 @item Open drain with one FTDI output as (non-)inverted output-enable
2457 @item Tristate with one FTDI output as (non-)inverted data line and another
2458 FTDI output as (non-)inverted output-enable
2459 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2460 switching data and direction as necessary
2463 These interfaces have several commands, used to configure the driver
2464 before initializing the JTAG scan chain:
2466 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2467 The vendor ID and product ID of the adapter. Up to eight
2468 [@var{vid}, @var{pid}] pairs may be given, e.g.
2470 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2474 @deffn {Config Command} {ftdi_device_desc} description
2475 Provides the USB device description (the @emph{iProduct string})
2476 of the adapter. If not specified, the device description is ignored
2477 during device selection.
2480 @deffn {Config Command} {ftdi_serial} serial-number
2481 Specifies the @var{serial-number} of the adapter to use,
2482 in case the vendor provides unique IDs and more than one adapter
2483 is connected to the host.
2484 If not specified, serial numbers are not considered.
2485 (Note that USB serial numbers can be arbitrary Unicode strings,
2486 and are not restricted to containing only decimal digits.)
2489 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2490 Specifies the physical USB port of the adapter to use. The path
2491 roots at @var{bus} and walks down the physical ports, with each
2492 @var{port} option specifying a deeper level in the bus topology, the last
2493 @var{port} denoting where the target adapter is actually plugged.
2494 The USB bus topology can be queried with the command @emph{lsusb -t}.
2496 This command is only available if your libusb1 is at least version 1.0.16.
2499 @deffn {Config Command} {ftdi_channel} channel
2500 Selects the channel of the FTDI device to use for MPSSE operations. Most
2501 adapters use the default, channel 0, but there are exceptions.
2504 @deffn {Config Command} {ftdi_layout_init} data direction
2505 Specifies the initial values of the FTDI GPIO data and direction registers.
2506 Each value is a 16-bit number corresponding to the concatenation of the high
2507 and low FTDI GPIO registers. The values should be selected based on the
2508 schematics of the adapter, such that all signals are set to safe levels with
2509 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2510 and initially asserted reset signals.
2513 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2514 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2515 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2516 register bitmasks to tell the driver the connection and type of the output
2517 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2518 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2519 used with inverting data inputs and @option{-data} with non-inverting inputs.
2520 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2521 not-output-enable) input to the output buffer is connected. The options
2522 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2523 with the method @command{ftdi_get_signal}.
2525 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2526 simple open-collector transistor driver would be specified with @option{-oe}
2527 only. In that case the signal can only be set to drive low or to Hi-Z and the
2528 driver will complain if the signal is set to drive high. Which means that if
2529 it's a reset signal, @command{reset_config} must be specified as
2530 @option{srst_open_drain}, not @option{srst_push_pull}.
2532 A special case is provided when @option{-data} and @option{-oe} is set to the
2533 same bitmask. Then the FTDI pin is considered being connected straight to the
2534 target without any buffer. The FTDI pin is then switched between output and
2535 input as necessary to provide the full set of low, high and Hi-Z
2536 characteristics. In all other cases, the pins specified in a signal definition
2537 are always driven by the FTDI.
2539 If @option{-alias} or @option{-nalias} is used, the signal is created
2540 identical (or with data inverted) to an already specified signal
2544 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2545 Set a previously defined signal to the specified level.
2547 @item @option{0}, drive low
2548 @item @option{1}, drive high
2549 @item @option{z}, set to high-impedance
2553 @deffn {Command} {ftdi_get_signal} name
2554 Get the value of a previously defined signal.
2557 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2558 Configure TCK edge at which the adapter samples the value of the TDO signal
2560 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2561 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2562 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2563 stability at higher JTAG clocks.
2565 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2566 @item @option{falling}, sample TDO on falling edge of TCK
2570 For example adapter definitions, see the configuration files shipped in the
2571 @file{interface/ftdi} directory.
2575 @deffn {Interface Driver} {ft232r}
2576 This driver is implementing synchronous bitbang mode of an FTDI FT232R
2579 List of connections (pin numbers for SSOP):
2586 @item DCD(10) - SRST
2589 These interfaces have several commands, used to configure the driver
2590 before initializing the JTAG scan chain:
2592 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2593 The vendor ID and product ID of the adapter. If not specified, default
2594 0x0403:0x6001 is used.
2597 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2598 Specifies the @var{serial} of the adapter to use, in case the
2599 vendor provides unique IDs and more than one adapter is connected to
2600 the host. If not specified, serial numbers are not considered.
2605 @deffn {Interface Driver} {remote_bitbang}
2606 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2607 with a remote process and sends ASCII encoded bitbang requests to that process
2608 instead of directly driving JTAG.
2610 The remote_bitbang driver is useful for debugging software running on
2611 processors which are being simulated.
2613 @deffn {Config Command} {remote_bitbang_port} number
2614 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2615 sockets instead of TCP.
2618 @deffn {Config Command} {remote_bitbang_host} hostname
2619 Specifies the hostname of the remote process to connect to using TCP, or the
2620 name of the UNIX socket to use if remote_bitbang_port is 0.
2623 For example, to connect remotely via TCP to the host foobar you might have
2627 interface remote_bitbang
2628 remote_bitbang_port 3335
2629 remote_bitbang_host foobar
2632 To connect to another process running locally via UNIX sockets with socket
2636 interface remote_bitbang
2637 remote_bitbang_port 0
2638 remote_bitbang_host mysocket
2642 @deffn {Interface Driver} {usb_blaster}
2643 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2644 for FTDI chips. These interfaces have several commands, used to
2645 configure the driver before initializing the JTAG scan chain:
2647 @deffn {Config Command} {usb_blaster_device_desc} description
2648 Provides the USB device description (the @emph{iProduct string})
2649 of the FTDI FT245 device. If not
2650 specified, the FTDI default value is used. This setting is only valid
2651 if compiled with FTD2XX support.
2654 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2655 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2656 default values are used.
2657 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2658 Altera USB-Blaster (default):
2660 usb_blaster_vid_pid 0x09FB 0x6001
2662 The following VID/PID is for Kolja Waschk's USB JTAG:
2664 usb_blaster_vid_pid 0x16C0 0x06AD
2668 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2669 Sets the state or function of the unused GPIO pins on USB-Blasters
2670 (pins 6 and 8 on the female JTAG header). These pins can be used as
2671 SRST and/or TRST provided the appropriate connections are made on the
2674 For example, to use pin 6 as SRST:
2676 usb_blaster_pin pin6 s
2677 reset_config srst_only
2681 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2682 Chooses the low level access method for the adapter. If not specified,
2683 @option{ftdi} is selected unless it wasn't enabled during the
2684 configure stage. USB-Blaster II needs @option{ublast2}.
2687 @deffn {Command} {usb_blaster_firmware} @var{path}
2688 This command specifies @var{path} to access USB-Blaster II firmware
2689 image. To be used with USB-Blaster II only.
2694 @deffn {Interface Driver} {gw16012}
2695 Gateworks GW16012 JTAG programmer.
2696 This has one driver-specific command:
2698 @deffn {Config Command} {parport_port} [port_number]
2699 Display either the address of the I/O port
2700 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2701 If a parameter is provided, first switch to use that port.
2702 This is a write-once setting.
2706 @deffn {Interface Driver} {jlink}
2707 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2710 @quotation Compatibility Note
2711 SEGGER released many firmware versions for the many hardware versions they
2712 produced. OpenOCD was extensively tested and intended to run on all of them,
2713 but some combinations were reported as incompatible. As a general
2714 recommendation, it is advisable to use the latest firmware version
2715 available for each hardware version. However the current V8 is a moving
2716 target, and SEGGER firmware versions released after the OpenOCD was
2717 released may not be compatible. In such cases it is recommended to
2718 revert to the last known functional version. For 0.5.0, this is from
2719 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2720 version is from "May 3 2012 18:36:22", packed with 4.46f.
2723 @deffn {Command} {jlink hwstatus}
2724 Display various hardware related information, for example target voltage and pin
2727 @deffn {Command} {jlink freemem}
2728 Display free device internal memory.
2730 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2731 Set the JTAG command version to be used. Without argument, show the actual JTAG
2734 @deffn {Command} {jlink config}
2735 Display the device configuration.
2737 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2738 Set the target power state on JTAG-pin 19. Without argument, show the target
2741 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2742 Set the MAC address of the device. Without argument, show the MAC address.
2744 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2745 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2746 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2749 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2750 Set the USB address of the device. This will also change the USB Product ID
2751 (PID) of the device. Without argument, show the USB address.
2753 @deffn {Command} {jlink config reset}
2754 Reset the current configuration.
2756 @deffn {Command} {jlink config write}
2757 Write the current configuration to the internal persistent storage.
2759 @deffn {Command} {jlink emucom write <channel> <data>}
2760 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2763 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2764 the EMUCOM channel 0x10:
2766 > jlink emucom write 0x10 aa0b23
2769 @deffn {Command} {jlink emucom read <channel> <length>}
2770 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2773 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2775 > jlink emucom read 0x0 4
2779 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2780 Set the USB address of the interface, in case more than one adapter is connected
2781 to the host. If not specified, USB addresses are not considered. Device
2782 selection via USB address is deprecated and the serial number should be used
2785 As a configuration command, it can be used only before 'init'.
2787 @deffn {Config} {jlink serial} <serial number>
2788 Set the serial number of the interface, in case more than one adapter is
2789 connected to the host. If not specified, serial numbers are not considered.
2791 As a configuration command, it can be used only before 'init'.
2795 @deffn {Interface Driver} {kitprog}
2796 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2797 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2798 families, but it is possible to use it with some other devices. If you are using
2799 this adapter with a PSoC or a PRoC, you may need to add
2800 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2801 configuration script.
2803 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2804 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2805 be used with this driver, and must either be used with the cmsis-dap driver or
2806 switched back to KitProg mode. See the Cypress KitProg User Guide for
2807 instructions on how to switch KitProg modes.
2811 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2813 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2814 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2815 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2816 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2817 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2818 SWD sequence must be sent after every target reset in order to re-establish
2819 communications with the target.
2820 @item Due in part to the limitation above, KitProg devices with firmware below
2821 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2822 communicate with PSoC 5LP devices. This is because, assuming debug is not
2823 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2824 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2825 could only be sent with an acquisition sequence.
2828 @deffn {Config Command} {kitprog_init_acquire_psoc}
2829 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2830 Please be aware that the acquisition sequence hard-resets the target.
2833 @deffn {Config Command} {kitprog_serial} serial
2834 Select a KitProg device by its @var{serial}. If left unspecified, the first
2835 device detected by OpenOCD will be used.
2838 @deffn {Command} {kitprog acquire_psoc}
2839 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2840 outside of the target-specific configuration scripts since it hard-resets the
2841 target as a side-effect.
2842 This is necessary for "reset halt" on some PSoC 4 series devices.
2845 @deffn {Command} {kitprog info}
2846 Display various adapter information, such as the hardware version, firmware
2847 version, and target voltage.
2851 @deffn {Interface Driver} {parport}
2852 Supports PC parallel port bit-banging cables:
2853 Wigglers, PLD download cable, and more.
2854 These interfaces have several commands, used to configure the driver
2855 before initializing the JTAG scan chain:
2857 @deffn {Config Command} {parport_cable} name
2858 Set the layout of the parallel port cable used to connect to the target.
2859 This is a write-once setting.
2860 Currently valid cable @var{name} values include:
2863 @item @b{altium} Altium Universal JTAG cable.
2864 @item @b{arm-jtag} Same as original wiggler except SRST and
2865 TRST connections reversed and TRST is also inverted.
2866 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2867 in configuration mode. This is only used to
2868 program the Chameleon itself, not a connected target.
2869 @item @b{dlc5} The Xilinx Parallel cable III.
2870 @item @b{flashlink} The ST Parallel cable.
2871 @item @b{lattice} Lattice ispDOWNLOAD Cable
2872 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2874 Amontec's Chameleon Programmer. The new version available from
2875 the website uses the original Wiggler layout ('@var{wiggler}')
2876 @item @b{triton} The parallel port adapter found on the
2877 ``Karo Triton 1 Development Board''.
2878 This is also the layout used by the HollyGates design
2879 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2880 @item @b{wiggler} The original Wiggler layout, also supported by
2881 several clones, such as the Olimex ARM-JTAG
2882 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2883 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2887 @deffn {Config Command} {parport_port} [port_number]
2888 Display either the address of the I/O port
2889 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2890 If a parameter is provided, first switch to use that port.
2891 This is a write-once setting.
2893 When using PPDEV to access the parallel port, use the number of the parallel port:
2894 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2895 you may encounter a problem.
2898 @deffn Command {parport_toggling_time} [nanoseconds]
2899 Displays how many nanoseconds the hardware needs to toggle TCK;
2900 the parport driver uses this value to obey the
2901 @command{adapter_khz} configuration.
2902 When the optional @var{nanoseconds} parameter is given,
2903 that setting is changed before displaying the current value.
2905 The default setting should work reasonably well on commodity PC hardware.
2906 However, you may want to calibrate for your specific hardware.
2908 To measure the toggling time with a logic analyzer or a digital storage
2909 oscilloscope, follow the procedure below:
2911 > parport_toggling_time 1000
2914 This sets the maximum JTAG clock speed of the hardware, but
2915 the actual speed probably deviates from the requested 500 kHz.
2916 Now, measure the time between the two closest spaced TCK transitions.
2917 You can use @command{runtest 1000} or something similar to generate a
2918 large set of samples.
2919 Update the setting to match your measurement:
2921 > parport_toggling_time <measured nanoseconds>
2923 Now the clock speed will be a better match for @command{adapter_khz rate}
2924 commands given in OpenOCD scripts and event handlers.
2926 You can do something similar with many digital multimeters, but note
2927 that you'll probably need to run the clock continuously for several
2928 seconds before it decides what clock rate to show. Adjust the
2929 toggling time up or down until the measured clock rate is a good
2930 match for the adapter_khz rate you specified; be conservative.
2934 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2935 This will configure the parallel driver to write a known
2936 cable-specific value to the parallel interface on exiting OpenOCD.
2939 For example, the interface configuration file for a
2940 classic ``Wiggler'' cable on LPT2 might look something like this:
2945 parport_cable wiggler
2949 @deffn {Interface Driver} {presto}
2950 ASIX PRESTO USB JTAG programmer.
2951 @deffn {Config Command} {presto_serial} serial_string
2952 Configures the USB serial number of the Presto device to use.
2956 @deffn {Interface Driver} {rlink}
2957 Raisonance RLink USB adapter
2960 @deffn {Interface Driver} {usbprog}
2961 usbprog is a freely programmable USB adapter.
2964 @deffn {Interface Driver} {vsllink}
2965 vsllink is part of Versaloon which is a versatile USB programmer.
2968 This defines quite a few driver-specific commands,
2969 which are not currently documented here.
2973 @anchor{hla_interface}
2974 @deffn {Interface Driver} {hla}
2975 This is a driver that supports multiple High Level Adapters.
2976 This type of adapter does not expose some of the lower level api's
2977 that OpenOCD would normally use to access the target.
2979 Currently supported adapters include the ST ST-LINK and TI ICDI.
2980 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2981 versions of firmware where serial number is reset after first use. Suggest
2982 using ST firmware update utility to upgrade ST-LINK firmware even if current
2983 version reported is V2.J21.S4.
2985 @deffn {Config Command} {hla_device_desc} description
2986 Currently Not Supported.
2989 @deffn {Config Command} {hla_serial} serial
2990 Specifies the serial number of the adapter.
2993 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2994 Specifies the adapter layout to use.
2997 @deffn {Config Command} {hla_vid_pid} [vid pid]+
2998 Pairs of vendor IDs and product IDs of the device.
3001 @deffn {Command} {hla_command} command
3002 Execute a custom adapter-specific command. The @var{command} string is
3003 passed as is to the underlying adapter layout handler.
3007 @deffn {Interface Driver} {opendous}
3008 opendous-jtag is a freely programmable USB adapter.
3011 @deffn {Interface Driver} {ulink}
3012 This is the Keil ULINK v1 JTAG debugger.
3015 @deffn {Interface Driver} {ZY1000}
3016 This is the Zylin ZY1000 JTAG debugger.
3020 This defines some driver-specific commands,
3021 which are not currently documented here.
3024 @deffn Command power [@option{on}|@option{off}]
3025 Turn power switch to target on/off.
3026 No arguments: print status.
3029 @deffn {Interface Driver} {bcm2835gpio}
3030 This SoC is present in Raspberry Pi which is a cheap single-board computer
3031 exposing some GPIOs on its expansion header.
3033 The driver accesses memory-mapped GPIO peripheral registers directly
3034 for maximum performance, but the only possible race condition is for
3035 the pins' modes/muxing (which is highly unlikely), so it should be
3036 able to coexist nicely with both sysfs bitbanging and various
3037 peripherals' kernel drivers. The driver restores the previous
3038 configuration on exit.
3040 See @file{interface/raspberrypi-native.cfg} for a sample config and
3045 @deffn {Interface Driver} {imx_gpio}
3046 i.MX SoC is present in many community boards. Wandboard is an example
3047 of the one which is most popular.
3049 This driver is mostly the same as bcm2835gpio.
3051 See @file{interface/imx-native.cfg} for a sample config and
3057 @deffn {Interface Driver} {openjtag}
3058 OpenJTAG compatible USB adapter.
3059 This defines some driver-specific commands:
3061 @deffn {Config Command} {openjtag_variant} variant
3062 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3063 Currently valid @var{variant} values include:
3066 @item @b{standard} Standard variant (default).
3067 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3068 (see @uref{http://www.cypress.com/?rID=82870}).
3072 @deffn {Config Command} {openjtag_device_desc} string
3073 The USB device description string of the adapter.
3074 This value is only used with the standard variant.
3078 @section Transport Configuration
3080 As noted earlier, depending on the version of OpenOCD you use,
3081 and the debug adapter you are using,
3082 several transports may be available to
3083 communicate with debug targets (or perhaps to program flash memory).
3084 @deffn Command {transport list}
3085 displays the names of the transports supported by this
3089 @deffn Command {transport select} @option{transport_name}
3090 Select which of the supported transports to use in this OpenOCD session.
3092 When invoked with @option{transport_name}, attempts to select the named
3093 transport. The transport must be supported by the debug adapter
3094 hardware and by the version of OpenOCD you are using (including the
3097 If no transport has been selected and no @option{transport_name} is
3098 provided, @command{transport select} auto-selects the first transport
3099 supported by the debug adapter.
3101 @command{transport select} always returns the name of the session's selected
3105 @subsection JTAG Transport
3107 JTAG is the original transport supported by OpenOCD, and most
3108 of the OpenOCD commands support it.
3109 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3110 each of which must be explicitly declared.
3111 JTAG supports both debugging and boundary scan testing.
3112 Flash programming support is built on top of debug support.
3114 JTAG transport is selected with the command @command{transport select
3115 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3116 driver}, in which case the command is @command{transport select
3119 @subsection SWD Transport
3121 @cindex Serial Wire Debug
3122 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3123 Debug Access Point (DAP, which must be explicitly declared.
3124 (SWD uses fewer signal wires than JTAG.)
3125 SWD is debug-oriented, and does not support boundary scan testing.
3126 Flash programming support is built on top of debug support.
3127 (Some processors support both JTAG and SWD.)
3129 SWD transport is selected with the command @command{transport select
3130 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3131 driver}, in which case the command is @command{transport select
3134 @deffn Command {swd newdap} ...
3135 Declares a single DAP which uses SWD transport.
3136 Parameters are currently the same as "jtag newtap" but this is
3139 @deffn Command {swd wcr trn prescale}
3140 Updates TRN (turnaround delay) and prescaling.fields of the
3141 Wire Control Register (WCR).
3142 No parameters: displays current settings.
3145 @subsection SPI Transport
3147 @cindex Serial Peripheral Interface
3148 The Serial Peripheral Interface (SPI) is a general purpose transport
3149 which uses four wire signaling. Some processors use it as part of a
3150 solution for flash programming.
3154 JTAG clock setup is part of system setup.
3155 It @emph{does not belong with interface setup} since any interface
3156 only knows a few of the constraints for the JTAG clock speed.
3157 Sometimes the JTAG speed is
3158 changed during the target initialization process: (1) slow at
3159 reset, (2) program the CPU clocks, (3) run fast.
3160 Both the "slow" and "fast" clock rates are functions of the
3161 oscillators used, the chip, the board design, and sometimes
3162 power management software that may be active.
3164 The speed used during reset, and the scan chain verification which
3165 follows reset, can be adjusted using a @code{reset-start}
3166 target event handler.
3167 It can then be reconfigured to a faster speed by a
3168 @code{reset-init} target event handler after it reprograms those
3169 CPU clocks, or manually (if something else, such as a boot loader,
3170 sets up those clocks).
3171 @xref{targetevents,,Target Events}.
3172 When the initial low JTAG speed is a chip characteristic, perhaps
3173 because of a required oscillator speed, provide such a handler
3174 in the target config file.
3175 When that speed is a function of a board-specific characteristic
3176 such as which speed oscillator is used, it belongs in the board
3177 config file instead.
3178 In both cases it's safest to also set the initial JTAG clock rate
3179 to that same slow speed, so that OpenOCD never starts up using a
3180 clock speed that's faster than the scan chain can support.
3184 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3187 If your system supports adaptive clocking (RTCK), configuring
3188 JTAG to use that is probably the most robust approach.
3189 However, it introduces delays to synchronize clocks; so it
3190 may not be the fastest solution.
3192 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3193 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3194 which support adaptive clocking.
3196 @deffn {Command} adapter_khz max_speed_kHz
3197 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3198 JTAG interfaces usually support a limited number of
3199 speeds. The speed actually used won't be faster
3200 than the speed specified.
3202 Chip data sheets generally include a top JTAG clock rate.
3203 The actual rate is often a function of a CPU core clock,
3204 and is normally less than that peak rate.
3205 For example, most ARM cores accept at most one sixth of the CPU clock.
3207 Speed 0 (khz) selects RTCK method.
3208 @xref{faqrtck,,FAQ RTCK}.
3209 If your system uses RTCK, you won't need to change the
3210 JTAG clocking after setup.
3211 Not all interfaces, boards, or targets support ``rtck''.
3212 If the interface device can not
3213 support it, an error is returned when you try to use RTCK.
3216 @defun jtag_rclk fallback_speed_kHz
3217 @cindex adaptive clocking
3219 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3220 If that fails (maybe the interface, board, or target doesn't
3221 support it), falls back to the specified frequency.
3223 # Fall back to 3mhz if RTCK is not supported
3228 @node Reset Configuration
3229 @chapter Reset Configuration
3230 @cindex Reset Configuration
3232 Every system configuration may require a different reset
3233 configuration. This can also be quite confusing.
3234 Resets also interact with @var{reset-init} event handlers,
3235 which do things like setting up clocks and DRAM, and
3236 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3237 They can also interact with JTAG routers.
3238 Please see the various board files for examples.
3241 To maintainers and integrators:
3242 Reset configuration touches several things at once.
3243 Normally the board configuration file
3244 should define it and assume that the JTAG adapter supports
3245 everything that's wired up to the board's JTAG connector.
3247 However, the target configuration file could also make note
3248 of something the silicon vendor has done inside the chip,
3249 which will be true for most (or all) boards using that chip.
3250 And when the JTAG adapter doesn't support everything, the
3251 user configuration file will need to override parts of
3252 the reset configuration provided by other files.
3255 @section Types of Reset
3257 There are many kinds of reset possible through JTAG, but
3258 they may not all work with a given board and adapter.
3259 That's part of why reset configuration can be error prone.
3263 @emph{System Reset} ... the @emph{SRST} hardware signal
3264 resets all chips connected to the JTAG adapter, such as processors,
3265 power management chips, and I/O controllers. Normally resets triggered
3266 with this signal behave exactly like pressing a RESET button.
3268 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3269 just the TAP controllers connected to the JTAG adapter.
3270 Such resets should not be visible to the rest of the system; resetting a
3271 device's TAP controller just puts that controller into a known state.
3273 @emph{Emulation Reset} ... many devices can be reset through JTAG
3274 commands. These resets are often distinguishable from system
3275 resets, either explicitly (a "reset reason" register says so)
3276 or implicitly (not all parts of the chip get reset).
3278 @emph{Other Resets} ... system-on-chip devices often support
3279 several other types of reset.
3280 You may need to arrange that a watchdog timer stops
3281 while debugging, preventing a watchdog reset.
3282 There may be individual module resets.
3285 In the best case, OpenOCD can hold SRST, then reset
3286 the TAPs via TRST and send commands through JTAG to halt the
3287 CPU at the reset vector before the 1st instruction is executed.
3288 Then when it finally releases the SRST signal, the system is
3289 halted under debugger control before any code has executed.
3290 This is the behavior required to support the @command{reset halt}
3291 and @command{reset init} commands; after @command{reset init} a
3292 board-specific script might do things like setting up DRAM.
3293 (@xref{resetcommand,,Reset Command}.)
3295 @anchor{srstandtrstissues}
3296 @section SRST and TRST Issues
3298 Because SRST and TRST are hardware signals, they can have a
3299 variety of system-specific constraints. Some of the most
3304 @item @emph{Signal not available} ... Some boards don't wire
3305 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3306 support such signals even if they are wired up.
3307 Use the @command{reset_config} @var{signals} options to say
3308 when either of those signals is not connected.
3309 When SRST is not available, your code might not be able to rely
3310 on controllers having been fully reset during code startup.
3311 Missing TRST is not a problem, since JTAG-level resets can
3312 be triggered using with TMS signaling.
3314 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3315 adapter will connect SRST to TRST, instead of keeping them separate.
3316 Use the @command{reset_config} @var{combination} options to say
3317 when those signals aren't properly independent.
3319 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3320 delay circuit, reset supervisor, or on-chip features can extend
3321 the effect of a JTAG adapter's reset for some time after the adapter
3322 stops issuing the reset. For example, there may be chip or board
3323 requirements that all reset pulses last for at least a
3324 certain amount of time; and reset buttons commonly have
3325 hardware debouncing.
3326 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3327 commands to say when extra delays are needed.
3329 @item @emph{Drive type} ... Reset lines often have a pullup
3330 resistor, letting the JTAG interface treat them as open-drain
3331 signals. But that's not a requirement, so the adapter may need
3332 to use push/pull output drivers.
3333 Also, with weak pullups it may be advisable to drive
3334 signals to both levels (push/pull) to minimize rise times.
3335 Use the @command{reset_config} @var{trst_type} and
3336 @var{srst_type} parameters to say how to drive reset signals.
3338 @item @emph{Special initialization} ... Targets sometimes need
3339 special JTAG initialization sequences to handle chip-specific
3340 issues (not limited to errata).
3341 For example, certain JTAG commands might need to be issued while
3342 the system as a whole is in a reset state (SRST active)
3343 but the JTAG scan chain is usable (TRST inactive).
3344 Many systems treat combined assertion of SRST and TRST as a
3345 trigger for a harder reset than SRST alone.
3346 Such custom reset handling is discussed later in this chapter.
3349 There can also be other issues.
3350 Some devices don't fully conform to the JTAG specifications.
3351 Trivial system-specific differences are common, such as
3352 SRST and TRST using slightly different names.
3353 There are also vendors who distribute key JTAG documentation for
3354 their chips only to developers who have signed a Non-Disclosure
3357 Sometimes there are chip-specific extensions like a requirement to use
3358 the normally-optional TRST signal (precluding use of JTAG adapters which
3359 don't pass TRST through), or needing extra steps to complete a TAP reset.
3361 In short, SRST and especially TRST handling may be very finicky,
3362 needing to cope with both architecture and board specific constraints.
3364 @section Commands for Handling Resets
3366 @deffn {Command} adapter_nsrst_assert_width milliseconds
3367 Minimum amount of time (in milliseconds) OpenOCD should wait
3368 after asserting nSRST (active-low system reset) before
3369 allowing it to be deasserted.
3372 @deffn {Command} adapter_nsrst_delay milliseconds
3373 How long (in milliseconds) OpenOCD should wait after deasserting
3374 nSRST (active-low system reset) before starting new JTAG operations.
3375 When a board has a reset button connected to SRST line it will
3376 probably have hardware debouncing, implying you should use this.
3379 @deffn {Command} jtag_ntrst_assert_width milliseconds
3380 Minimum amount of time (in milliseconds) OpenOCD should wait
3381 after asserting nTRST (active-low JTAG TAP reset) before
3382 allowing it to be deasserted.
3385 @deffn {Command} jtag_ntrst_delay milliseconds
3386 How long (in milliseconds) OpenOCD should wait after deasserting
3387 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3390 @deffn {Command} reset_config mode_flag ...
3391 This command displays or modifies the reset configuration
3392 of your combination of JTAG board and target in target
3393 configuration scripts.
3395 Information earlier in this section describes the kind of problems
3396 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3397 As a rule this command belongs only in board config files,
3398 describing issues like @emph{board doesn't connect TRST};
3399 or in user config files, addressing limitations derived
3400 from a particular combination of interface and board.
3401 (An unlikely example would be using a TRST-only adapter
3402 with a board that only wires up SRST.)
3404 The @var{mode_flag} options can be specified in any order, but only one
3405 of each type -- @var{signals}, @var{combination}, @var{gates},
3406 @var{trst_type}, @var{srst_type} and @var{connect_type}
3407 -- may be specified at a time.
3408 If you don't provide a new value for a given type, its previous
3409 value (perhaps the default) is unchanged.
3410 For example, this means that you don't need to say anything at all about
3411 TRST just to declare that if the JTAG adapter should want to drive SRST,
3412 it must explicitly be driven high (@option{srst_push_pull}).
3416 @var{signals} can specify which of the reset signals are connected.
3417 For example, If the JTAG interface provides SRST, but the board doesn't
3418 connect that signal properly, then OpenOCD can't use it.
3419 Possible values are @option{none} (the default), @option{trst_only},
3420 @option{srst_only} and @option{trst_and_srst}.
3423 If your board provides SRST and/or TRST through the JTAG connector,
3424 you must declare that so those signals can be used.
3428 The @var{combination} is an optional value specifying broken reset
3429 signal implementations.
3430 The default behaviour if no option given is @option{separate},
3431 indicating everything behaves normally.
3432 @option{srst_pulls_trst} states that the
3433 test logic is reset together with the reset of the system (e.g. NXP
3434 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3435 the system is reset together with the test logic (only hypothetical, I
3436 haven't seen hardware with such a bug, and can be worked around).
3437 @option{combined} implies both @option{srst_pulls_trst} and
3438 @option{trst_pulls_srst}.
3441 The @var{gates} tokens control flags that describe some cases where
3442 JTAG may be unavailable during reset.
3443 @option{srst_gates_jtag} (default)
3444 indicates that asserting SRST gates the
3445 JTAG clock. This means that no communication can happen on JTAG
3446 while SRST is asserted.
3447 Its converse is @option{srst_nogate}, indicating that JTAG commands
3448 can safely be issued while SRST is active.
3451 The @var{connect_type} tokens control flags that describe some cases where
3452 SRST is asserted while connecting to the target. @option{srst_nogate}
3453 is required to use this option.
3454 @option{connect_deassert_srst} (default)
3455 indicates that SRST will not be asserted while connecting to the target.
3456 Its converse is @option{connect_assert_srst}, indicating that SRST will
3457 be asserted before any target connection.
3458 Only some targets support this feature, STM32 and STR9 are examples.
3459 This feature is useful if you are unable to connect to your target due
3460 to incorrect options byte config or illegal program execution.
3463 The optional @var{trst_type} and @var{srst_type} parameters allow the
3464 driver mode of each reset line to be specified. These values only affect
3465 JTAG interfaces with support for different driver modes, like the Amontec
3466 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3467 relevant signal (TRST or SRST) is not connected.
3471 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3472 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3473 Most boards connect this signal to a pulldown, so the JTAG TAPs
3474 never leave reset unless they are hooked up to a JTAG adapter.
3477 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3478 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3479 Most boards connect this signal to a pullup, and allow the
3480 signal to be pulled low by various events including system
3481 power-up and pressing a reset button.
3485 @section Custom Reset Handling
3488 OpenOCD has several ways to help support the various reset
3489 mechanisms provided by chip and board vendors.
3490 The commands shown in the previous section give standard parameters.
3491 There are also @emph{event handlers} associated with TAPs or Targets.
3492 Those handlers are Tcl procedures you can provide, which are invoked
3493 at particular points in the reset sequence.
3495 @emph{When SRST is not an option} you must set
3496 up a @code{reset-assert} event handler for your target.
3497 For example, some JTAG adapters don't include the SRST signal;
3498 and some boards have multiple targets, and you won't always
3499 want to reset everything at once.
3501 After configuring those mechanisms, you might still
3502 find your board doesn't start up or reset correctly.
3503 For example, maybe it needs a slightly different sequence
3504 of SRST and/or TRST manipulations, because of quirks that
3505 the @command{reset_config} mechanism doesn't address;
3506 or asserting both might trigger a stronger reset, which
3507 needs special attention.
3509 Experiment with lower level operations, such as @command{jtag_reset}
3510 and the @command{jtag arp_*} operations shown here,
3511 to find a sequence of operations that works.
3512 @xref{JTAG Commands}.
3513 When you find a working sequence, it can be used to override
3514 @command{jtag_init}, which fires during OpenOCD startup
3515 (@pxref{configurationstage,,Configuration Stage});
3516 or @command{init_reset}, which fires during reset processing.
3518 You might also want to provide some project-specific reset
3519 schemes. For example, on a multi-target board the standard
3520 @command{reset} command would reset all targets, but you
3521 may need the ability to reset only one target at time and
3522 thus want to avoid using the board-wide SRST signal.
3524 @deffn {Overridable Procedure} init_reset mode
3525 This is invoked near the beginning of the @command{reset} command,
3526 usually to provide as much of a cold (power-up) reset as practical.
3527 By default it is also invoked from @command{jtag_init} if
3528 the scan chain does not respond to pure JTAG operations.
3529 The @var{mode} parameter is the parameter given to the
3530 low level reset command (@option{halt},
3531 @option{init}, or @option{run}), @option{setup},
3532 or potentially some other value.
3534 The default implementation just invokes @command{jtag arp_init-reset}.
3535 Replacements will normally build on low level JTAG
3536 operations such as @command{jtag_reset}.
3537 Operations here must not address individual TAPs
3538 (or their associated targets)
3539 until the JTAG scan chain has first been verified to work.
3541 Implementations must have verified the JTAG scan chain before
3543 This is done by calling @command{jtag arp_init}
3544 (or @command{jtag arp_init-reset}).
3547 @deffn Command {jtag arp_init}
3548 This validates the scan chain using just the four
3549 standard JTAG signals (TMS, TCK, TDI, TDO).
3550 It starts by issuing a JTAG-only reset.
3551 Then it performs checks to verify that the scan chain configuration
3552 matches the TAPs it can observe.
3553 Those checks include checking IDCODE values for each active TAP,
3554 and verifying the length of their instruction registers using
3555 TAP @code{-ircapture} and @code{-irmask} values.
3556 If these tests all pass, TAP @code{setup} events are
3557 issued to all TAPs with handlers for that event.
3560 @deffn Command {jtag arp_init-reset}
3561 This uses TRST and SRST to try resetting
3562 everything on the JTAG scan chain
3563 (and anything else connected to SRST).
3564 It then invokes the logic of @command{jtag arp_init}.
3568 @node TAP Declaration
3569 @chapter TAP Declaration
3570 @cindex TAP declaration
3571 @cindex TAP configuration
3573 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3574 TAPs serve many roles, including:
3577 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3578 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3579 Others do it indirectly, making a CPU do it.
3580 @item @b{Program Download} Using the same CPU support GDB uses,
3581 you can initialize a DRAM controller, download code to DRAM, and then
3582 start running that code.
3583 @item @b{Boundary Scan} Most chips support boundary scan, which
3584 helps test for board assembly problems like solder bridges
3585 and missing connections.
3588 OpenOCD must know about the active TAPs on your board(s).
3589 Setting up the TAPs is the core task of your configuration files.
3590 Once those TAPs are set up, you can pass their names to code
3591 which sets up CPUs and exports them as GDB targets,
3592 probes flash memory, performs low-level JTAG operations, and more.
3594 @section Scan Chains
3597 TAPs are part of a hardware @dfn{scan chain},
3598 which is a daisy chain of TAPs.
3599 They also need to be added to
3600 OpenOCD's software mirror of that hardware list,
3601 giving each member a name and associating other data with it.
3602 Simple scan chains, with a single TAP, are common in
3603 systems with a single microcontroller or microprocessor.
3604 More complex chips may have several TAPs internally.
3605 Very complex scan chains might have a dozen or more TAPs:
3606 several in one chip, more in the next, and connecting
3607 to other boards with their own chips and TAPs.
3609 You can display the list with the @command{scan_chain} command.
3610 (Don't confuse this with the list displayed by the @command{targets}
3611 command, presented in the next chapter.
3612 That only displays TAPs for CPUs which are configured as
3614 Here's what the scan chain might look like for a chip more than one TAP:
3617 TapName Enabled IdCode Expected IrLen IrCap IrMask
3618 -- ------------------ ------- ---------- ---------- ----- ----- ------
3619 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3620 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3621 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3624 OpenOCD can detect some of that information, but not all
3625 of it. @xref{autoprobing,,Autoprobing}.
3626 Unfortunately, those TAPs can't always be autoconfigured,
3627 because not all devices provide good support for that.
3628 JTAG doesn't require supporting IDCODE instructions, and
3629 chips with JTAG routers may not link TAPs into the chain
3630 until they are told to do so.
3632 The configuration mechanism currently supported by OpenOCD
3633 requires explicit configuration of all TAP devices using
3634 @command{jtag newtap} commands, as detailed later in this chapter.
3635 A command like this would declare one tap and name it @code{chip1.cpu}:
3638 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3641 Each target configuration file lists the TAPs provided
3643 Board configuration files combine all the targets on a board,
3645 Note that @emph{the order in which TAPs are declared is very important.}
3646 That declaration order must match the order in the JTAG scan chain,
3647 both inside a single chip and between them.
3648 @xref{faqtaporder,,FAQ TAP Order}.
3650 For example, the STMicroelectronics STR912 chip has
3651 three separate TAPs@footnote{See the ST
3652 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3653 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3654 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3655 To configure those taps, @file{target/str912.cfg}
3656 includes commands something like this:
3659 jtag newtap str912 flash ... params ...
3660 jtag newtap str912 cpu ... params ...
3661 jtag newtap str912 bs ... params ...
3664 Actual config files typically use a variable such as @code{$_CHIPNAME}
3665 instead of literals like @option{str912}, to support more than one chip
3666 of each type. @xref{Config File Guidelines}.
3668 @deffn Command {jtag names}
3669 Returns the names of all current TAPs in the scan chain.
3670 Use @command{jtag cget} or @command{jtag tapisenabled}
3671 to examine attributes and state of each TAP.
3673 foreach t [jtag names] @{
3674 puts [format "TAP: %s\n" $t]
3679 @deffn Command {scan_chain}
3680 Displays the TAPs in the scan chain configuration,
3682 The set of TAPs listed by this command is fixed by
3683 exiting the OpenOCD configuration stage,
3684 but systems with a JTAG router can
3685 enable or disable TAPs dynamically.
3688 @c FIXME! "jtag cget" should be able to return all TAP
3689 @c attributes, like "$target_name cget" does for targets.
3691 @c Probably want "jtag eventlist", and a "tap-reset" event
3692 @c (on entry to RESET state).
3697 When TAP objects are declared with @command{jtag newtap},
3698 a @dfn{dotted.name} is created for the TAP, combining the
3699 name of a module (usually a chip) and a label for the TAP.
3700 For example: @code{xilinx.tap}, @code{str912.flash},
3701 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3702 Many other commands use that dotted.name to manipulate or
3703 refer to the TAP. For example, CPU configuration uses the
3704 name, as does declaration of NAND or NOR flash banks.
3706 The components of a dotted name should follow ``C'' symbol
3707 name rules: start with an alphabetic character, then numbers
3708 and underscores are OK; while others (including dots!) are not.
3710 @section TAP Declaration Commands
3712 @c shouldn't this be(come) a {Config Command}?
3713 @deffn Command {jtag newtap} chipname tapname configparams...
3714 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3715 and configured according to the various @var{configparams}.
3717 The @var{chipname} is a symbolic name for the chip.
3718 Conventionally target config files use @code{$_CHIPNAME},
3719 defaulting to the model name given by the chip vendor but
3722 @cindex TAP naming convention
3723 The @var{tapname} reflects the role of that TAP,
3724 and should follow this convention:
3727 @item @code{bs} -- For boundary scan if this is a separate TAP;
3728 @item @code{cpu} -- The main CPU of the chip, alternatively
3729 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3730 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3731 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3732 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3733 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3734 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3735 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3737 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3738 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3739 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3740 a JTAG TAP; that TAP should be named @code{sdma}.
3743 Every TAP requires at least the following @var{configparams}:
3746 @item @code{-irlen} @var{NUMBER}
3747 @*The length in bits of the
3748 instruction register, such as 4 or 5 bits.
3751 A TAP may also provide optional @var{configparams}:
3754 @item @code{-disable} (or @code{-enable})
3755 @*Use the @code{-disable} parameter to flag a TAP which is not
3756 linked into the scan chain after a reset using either TRST
3757 or the JTAG state machine's @sc{reset} state.
3758 You may use @code{-enable} to highlight the default state
3759 (the TAP is linked in).
3760 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3761 @item @code{-expected-id} @var{NUMBER}
3762 @*A non-zero @var{number} represents a 32-bit IDCODE
3763 which you expect to find when the scan chain is examined.
3764 These codes are not required by all JTAG devices.
3765 @emph{Repeat the option} as many times as required if more than one
3766 ID code could appear (for example, multiple versions).
3767 Specify @var{number} as zero to suppress warnings about IDCODE
3768 values that were found but not included in the list.
3770 Provide this value if at all possible, since it lets OpenOCD
3771 tell when the scan chain it sees isn't right. These values
3772 are provided in vendors' chip documentation, usually a technical
3773 reference manual. Sometimes you may need to probe the JTAG
3774 hardware to find these values.
3775 @xref{autoprobing,,Autoprobing}.
3776 @item @code{-ignore-version}
3777 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3778 option. When vendors put out multiple versions of a chip, or use the same
3779 JTAG-level ID for several largely-compatible chips, it may be more practical
3780 to ignore the version field than to update config files to handle all of
3781 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3782 @item @code{-ircapture} @var{NUMBER}
3783 @*The bit pattern loaded by the TAP into the JTAG shift register
3784 on entry to the @sc{ircapture} state, such as 0x01.
3785 JTAG requires the two LSBs of this value to be 01.
3786 By default, @code{-ircapture} and @code{-irmask} are set
3787 up to verify that two-bit value. You may provide
3788 additional bits if you know them, or indicate that
3789 a TAP doesn't conform to the JTAG specification.
3790 @item @code{-irmask} @var{NUMBER}
3791 @*A mask used with @code{-ircapture}
3792 to verify that instruction scans work correctly.
3793 Such scans are not used by OpenOCD except to verify that
3794 there seems to be no problems with JTAG scan chain operations.
3795 @item @code{-ignore-syspwrupack}
3796 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3797 register during initial examination and when checking the sticky error bit.
3798 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3799 devices do not set the ack bit until sometime later.
3803 @section Other TAP commands
3805 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3806 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3807 At this writing this TAP attribute
3808 mechanism is used only for event handling.
3809 (It is not a direct analogue of the @code{cget}/@code{configure}
3810 mechanism for debugger targets.)
3811 See the next section for information about the available events.
3813 The @code{configure} subcommand assigns an event handler,
3814 a TCL string which is evaluated when the event is triggered.
3815 The @code{cget} subcommand returns that handler.
3822 OpenOCD includes two event mechanisms.
3823 The one presented here applies to all JTAG TAPs.
3824 The other applies to debugger targets,
3825 which are associated with certain TAPs.
3827 The TAP events currently defined are:
3830 @item @b{post-reset}
3831 @* The TAP has just completed a JTAG reset.
3832 The tap may still be in the JTAG @sc{reset} state.
3833 Handlers for these events might perform initialization sequences
3834 such as issuing TCK cycles, TMS sequences to ensure
3835 exit from the ARM SWD mode, and more.
3837 Because the scan chain has not yet been verified, handlers for these events
3838 @emph{should not issue commands which scan the JTAG IR or DR registers}
3839 of any particular target.
3840 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3842 @* The scan chain has been reset and verified.
3843 This handler may enable TAPs as needed.
3844 @item @b{tap-disable}
3845 @* The TAP needs to be disabled. This handler should
3846 implement @command{jtag tapdisable}
3847 by issuing the relevant JTAG commands.
3848 @item @b{tap-enable}
3849 @* The TAP needs to be enabled. This handler should
3850 implement @command{jtag tapenable}
3851 by issuing the relevant JTAG commands.
3854 If you need some action after each JTAG reset which isn't actually
3855 specific to any TAP (since you can't yet trust the scan chain's
3856 contents to be accurate), you might:
3859 jtag configure CHIP.jrc -event post-reset @{
3860 echo "JTAG Reset done"
3861 ... non-scan jtag operations to be done after reset
3866 @anchor{enablinganddisablingtaps}
3867 @section Enabling and Disabling TAPs
3868 @cindex JTAG Route Controller
3871 In some systems, a @dfn{JTAG Route Controller} (JRC)
3872 is used to enable and/or disable specific JTAG TAPs.
3873 Many ARM-based chips from Texas Instruments include
3874 an ``ICEPick'' module, which is a JRC.
3875 Such chips include DaVinci and OMAP3 processors.
3877 A given TAP may not be visible until the JRC has been
3878 told to link it into the scan chain; and if the JRC
3879 has been told to unlink that TAP, it will no longer
3881 Such routers address problems that JTAG ``bypass mode''
3885 @item The scan chain can only go as fast as its slowest TAP.
3886 @item Having many TAPs slows instruction scans, since all
3887 TAPs receive new instructions.
3888 @item TAPs in the scan chain must be powered up, which wastes
3889 power and prevents debugging some power management mechanisms.
3892 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3893 as implied by the existence of JTAG routers.
3894 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3895 does include a kind of JTAG router functionality.
3897 @c (a) currently the event handlers don't seem to be able to
3898 @c fail in a way that could lead to no-change-of-state.
3900 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3901 shown below, and is implemented using TAP event handlers.
3902 So for example, when defining a TAP for a CPU connected to
3903 a JTAG router, your @file{target.cfg} file
3904 should define TAP event handlers using
3905 code that looks something like this:
3908 jtag configure CHIP.cpu -event tap-enable @{
3909 ... jtag operations using CHIP.jrc
3911 jtag configure CHIP.cpu -event tap-disable @{
3912 ... jtag operations using CHIP.jrc
3916 Then you might want that CPU's TAP enabled almost all the time:
3919 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3922 Note how that particular setup event handler declaration
3923 uses quotes to evaluate @code{$CHIP} when the event is configured.
3924 Using brackets @{ @} would cause it to be evaluated later,
3925 at runtime, when it might have a different value.
3927 @deffn Command {jtag tapdisable} dotted.name
3928 If necessary, disables the tap
3929 by sending it a @option{tap-disable} event.
3930 Returns the string "1" if the tap
3931 specified by @var{dotted.name} is enabled,
3932 and "0" if it is disabled.
3935 @deffn Command {jtag tapenable} dotted.name
3936 If necessary, enables the tap
3937 by sending it a @option{tap-enable} event.
3938 Returns the string "1" if the tap
3939 specified by @var{dotted.name} is enabled,
3940 and "0" if it is disabled.
3943 @deffn Command {jtag tapisenabled} dotted.name
3944 Returns the string "1" if the tap
3945 specified by @var{dotted.name} is enabled,
3946 and "0" if it is disabled.
3949 Humans will find the @command{scan_chain} command more helpful
3950 for querying the state of the JTAG taps.
3954 @anchor{autoprobing}
3955 @section Autoprobing
3957 @cindex JTAG autoprobe
3959 TAP configuration is the first thing that needs to be done
3960 after interface and reset configuration. Sometimes it's
3961 hard finding out what TAPs exist, or how they are identified.
3962 Vendor documentation is not always easy to find and use.
3964 To help you get past such problems, OpenOCD has a limited
3965 @emph{autoprobing} ability to look at the scan chain, doing
3966 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3967 To use this mechanism, start the OpenOCD server with only data
3968 that configures your JTAG interface, and arranges to come up
3969 with a slow clock (many devices don't support fast JTAG clocks
3970 right when they come out of reset).
3972 For example, your @file{openocd.cfg} file might have:
3975 source [find interface/olimex-arm-usb-tiny-h.cfg]
3976 reset_config trst_and_srst
3980 When you start the server without any TAPs configured, it will
3981 attempt to autoconfigure the TAPs. There are two parts to this:
3984 @item @emph{TAP discovery} ...
3985 After a JTAG reset (sometimes a system reset may be needed too),
3986 each TAP's data registers will hold the contents of either the
3987 IDCODE or BYPASS register.
3988 If JTAG communication is working, OpenOCD will see each TAP,
3989 and report what @option{-expected-id} to use with it.
3990 @item @emph{IR Length discovery} ...
3991 Unfortunately JTAG does not provide a reliable way to find out
3992 the value of the @option{-irlen} parameter to use with a TAP
3994 If OpenOCD can discover the length of a TAP's instruction
3995 register, it will report it.
3996 Otherwise you may need to consult vendor documentation, such
3997 as chip data sheets or BSDL files.
4000 In many cases your board will have a simple scan chain with just
4001 a single device. Here's what OpenOCD reported with one board
4002 that's a bit more complex:
4006 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4007 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4008 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4009 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4010 AUTO auto0.tap - use "... -irlen 4"
4011 AUTO auto1.tap - use "... -irlen 4"
4012 AUTO auto2.tap - use "... -irlen 6"
4013 no gdb ports allocated as no target has been specified
4016 Given that information, you should be able to either find some existing
4017 config files to use, or create your own. If you create your own, you
4018 would configure from the bottom up: first a @file{target.cfg} file
4019 with these TAPs, any targets associated with them, and any on-chip
4020 resources; then a @file{board.cfg} with off-chip resources, clocking,
4023 @anchor{dapdeclaration}
4024 @section DAP declaration (ARMv7 and ARMv8 targets)
4025 @cindex DAP declaration
4027 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4028 no longer implicitly created together with the target. It must be
4029 explicitly declared using the @command{dap create} command. For all
4030 ARMv7 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4031 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4033 The @command{dap} command group supports the following sub-commands:
4035 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4036 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4037 @var{dotted.name}. This also creates a new command (@command{dap_name})
4038 which is used for various purposes including additional configuration.
4039 There can only be one DAP for each JTAG tap in the system.
4041 A DAP may also provide optional @var{configparams}:
4044 @item @code{-ignore-syspwrupack}
4045 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4046 register during initial examination and when checking the sticky error bit.
4047 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4048 devices do not set the ack bit until sometime later.
4052 @deffn Command {dap names}
4053 This command returns a list of all registered DAP objects. It it useful mainly
4057 @deffn Command {dap info} [num]
4058 Displays the ROM table for MEM-AP @var{num},
4059 defaulting to the currently selected AP of the currently selected target.
4062 @deffn Command {dap init}
4063 Initialize all registered DAPs. This command is used internally
4064 during initialization. It can be issued at any time after the
4065 initialization, too.
4068 The following commands exist as subcommands of DAP instances:
4070 @deffn Command {$dap_name info} [num]
4071 Displays the ROM table for MEM-AP @var{num},
4072 defaulting to the currently selected AP.
4075 @deffn Command {$dap_name apid} [num]
4076 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4079 @anchor{DAP subcommand apreg}
4080 @deffn Command {$dap_name apreg} ap_num reg [value]
4081 Displays content of a register @var{reg} from AP @var{ap_num}
4082 or set a new value @var{value}.
4083 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4086 @deffn Command {$dap_name apsel} [num]
4087 Select AP @var{num}, defaulting to 0.
4090 @deffn Command {$dap_name baseaddr} [num]
4091 Displays debug base address from MEM-AP @var{num},
4092 defaulting to the currently selected AP.
4095 @deffn Command {$dap_name memaccess} [value]
4096 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4097 memory bus access [0-255], giving additional time to respond to reads.
4098 If @var{value} is defined, first assigns that.
4101 @deffn Command {$dap_name apcsw} [value [mask]]
4102 Displays or changes CSW bit pattern for MEM-AP transfers.
4104 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4105 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4106 and the result is written to the real CSW register. All bits except dynamically
4107 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4108 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4111 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4112 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4115 kx.dap apcsw 0x2000000
4118 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4119 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4120 and leaves the rest of the pattern intact. It configures memory access through
4121 DCache on Cortex-M7.
4123 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4124 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4127 Another example clears SPROT bit and leaves the rest of pattern intact:
4129 set CSW_SPROT [expr 1 << 30]
4130 samv.dap apcsw 0 $CSW_SPROT
4133 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4134 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4136 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4137 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4138 example with a proper dap name:
4140 xxx.dap apcsw default
4144 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4145 Set/get quirks mode for TI TMS450/TMS570 processors
4150 @node CPU Configuration
4151 @chapter CPU Configuration
4154 This chapter discusses how to set up GDB debug targets for CPUs.
4155 You can also access these targets without GDB
4156 (@pxref{Architecture and Core Commands},
4157 and @ref{targetstatehandling,,Target State handling}) and
4158 through various kinds of NAND and NOR flash commands.
4159 If you have multiple CPUs you can have multiple such targets.
4161 We'll start by looking at how to examine the targets you have,
4162 then look at how to add one more target and how to configure it.
4164 @section Target List
4165 @cindex target, current
4166 @cindex target, list
4168 All targets that have been set up are part of a list,
4169 where each member has a name.
4170 That name should normally be the same as the TAP name.
4171 You can display the list with the @command{targets}
4173 This display often has only one CPU; here's what it might
4174 look like with more than one:
4176 TargetName Type Endian TapName State
4177 -- ------------------ ---------- ------ ------------------ ------------
4178 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4179 1 MyTarget cortex_m little mychip.foo tap-disabled
4182 One member of that list is the @dfn{current target}, which
4183 is implicitly referenced by many commands.
4184 It's the one marked with a @code{*} near the target name.
4185 In particular, memory addresses often refer to the address
4186 space seen by that current target.
4187 Commands like @command{mdw} (memory display words)
4188 and @command{flash erase_address} (erase NOR flash blocks)
4189 are examples; and there are many more.
4191 Several commands let you examine the list of targets:
4193 @deffn Command {target current}
4194 Returns the name of the current target.
4197 @deffn Command {target names}
4198 Lists the names of all current targets in the list.
4200 foreach t [target names] @{
4201 puts [format "Target: %s\n" $t]
4206 @c yep, "target list" would have been better.
4207 @c plus maybe "target setdefault".
4209 @deffn Command targets [name]
4210 @emph{Note: the name of this command is plural. Other target
4211 command names are singular.}
4213 With no parameter, this command displays a table of all known
4214 targets in a user friendly form.
4216 With a parameter, this command sets the current target to
4217 the given target with the given @var{name}; this is
4218 only relevant on boards which have more than one target.
4221 @section Target CPU Types
4225 Each target has a @dfn{CPU type}, as shown in the output of
4226 the @command{targets} command. You need to specify that type
4227 when calling @command{target create}.
4228 The CPU type indicates more than just the instruction set.
4229 It also indicates how that instruction set is implemented,
4230 what kind of debug support it integrates,
4231 whether it has an MMU (and if so, what kind),
4232 what core-specific commands may be available
4233 (@pxref{Architecture and Core Commands}),
4236 It's easy to see what target types are supported,
4237 since there's a command to list them.
4239 @anchor{targettypes}
4240 @deffn Command {target types}
4241 Lists all supported target types.
4242 At this writing, the supported CPU types are:
4245 @item @code{arm11} -- this is a generation of ARMv6 cores
4246 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4247 @item @code{arm7tdmi} -- this is an ARMv4 core
4248 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4249 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4250 @item @code{arm966e} -- this is an ARMv5 core
4251 @item @code{arm9tdmi} -- this is an ARMv4 core
4252 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4253 (Support for this is preliminary and incomplete.)
4254 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4255 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4256 compact Thumb2 instruction set.
4257 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4258 @item @code{dragonite} -- resembles arm966e
4259 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4260 (Support for this is still incomplete.)
4261 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4262 @item @code{feroceon} -- resembles arm926
4263 @item @code{mips_m4k} -- a MIPS core
4264 @item @code{xscale} -- this is actually an architecture,
4265 not a CPU type. It is based on the ARMv5 architecture.
4266 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4267 The current implementation supports three JTAG TAP cores:
4268 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4269 allowing access to physical memory addresses independently of CPU cores.
4271 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4272 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4273 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4275 And two debug interfaces cores:
4277 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4278 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4283 To avoid being confused by the variety of ARM based cores, remember
4284 this key point: @emph{ARM is a technology licencing company}.
4285 (See: @url{http://www.arm.com}.)
4286 The CPU name used by OpenOCD will reflect the CPU design that was
4287 licensed, not a vendor brand which incorporates that design.
4288 Name prefixes like arm7, arm9, arm11, and cortex
4289 reflect design generations;
4290 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4291 reflect an architecture version implemented by a CPU design.
4293 @anchor{targetconfiguration}
4294 @section Target Configuration
4296 Before creating a ``target'', you must have added its TAP to the scan chain.
4297 When you've added that TAP, you will have a @code{dotted.name}
4298 which is used to set up the CPU support.
4299 The chip-specific configuration file will normally configure its CPU(s)
4300 right after it adds all of the chip's TAPs to the scan chain.
4302 Although you can set up a target in one step, it's often clearer if you
4303 use shorter commands and do it in two steps: create it, then configure
4305 All operations on the target after it's created will use a new
4306 command, created as part of target creation.
4308 The two main things to configure after target creation are
4309 a work area, which usually has target-specific defaults even
4310 if the board setup code overrides them later;
4311 and event handlers (@pxref{targetevents,,Target Events}), which tend
4312 to be much more board-specific.
4313 The key steps you use might look something like this
4316 dap create mychip.dap -chain-position mychip.cpu
4317 target create MyTarget cortex_m -dap mychip.dap
4318 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4319 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4320 MyTarget configure -event reset-init @{ myboard_reinit @}
4323 You should specify a working area if you can; typically it uses some
4325 Such a working area can speed up many things, including bulk
4326 writes to target memory;
4327 flash operations like checking to see if memory needs to be erased;
4328 GDB memory checksumming;
4332 On more complex chips, the work area can become
4333 inaccessible when application code
4334 (such as an operating system)
4335 enables or disables the MMU.
4336 For example, the particular MMU context used to access the virtual
4337 address will probably matter ... and that context might not have
4338 easy access to other addresses needed.
4339 At this writing, OpenOCD doesn't have much MMU intelligence.
4342 It's often very useful to define a @code{reset-init} event handler.
4343 For systems that are normally used with a boot loader,
4344 common tasks include updating clocks and initializing memory
4346 That may be needed to let you write the boot loader into flash,
4347 in order to ``de-brick'' your board; or to load programs into
4348 external DDR memory without having run the boot loader.
4350 @deffn Command {target create} target_name type configparams...
4351 This command creates a GDB debug target that refers to a specific JTAG tap.
4352 It enters that target into a list, and creates a new
4353 command (@command{@var{target_name}}) which is used for various
4354 purposes including additional configuration.
4357 @item @var{target_name} ... is the name of the debug target.
4358 By convention this should be the same as the @emph{dotted.name}
4359 of the TAP associated with this target, which must be specified here
4360 using the @code{-chain-position @var{dotted.name}} configparam.
4362 This name is also used to create the target object command,
4363 referred to here as @command{$target_name},
4364 and in other places the target needs to be identified.
4365 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4366 @item @var{configparams} ... all parameters accepted by
4367 @command{$target_name configure} are permitted.
4368 If the target is big-endian, set it here with @code{-endian big}.
4370 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4371 @code{-dap @var{dap_name}} here.
4375 @deffn Command {$target_name configure} configparams...
4376 The options accepted by this command may also be
4377 specified as parameters to @command{target create}.
4378 Their values can later be queried one at a time by
4379 using the @command{$target_name cget} command.
4381 @emph{Warning:} changing some of these after setup is dangerous.
4382 For example, moving a target from one TAP to another;
4383 and changing its endianness.
4387 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4388 used to access this target.
4390 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4391 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4392 create and manage DAP instances.
4394 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4395 whether the CPU uses big or little endian conventions
4397 @item @code{-event} @var{event_name} @var{event_body} --
4398 @xref{targetevents,,Target Events}.
4399 Note that this updates a list of named event handlers.
4400 Calling this twice with two different event names assigns
4401 two different handlers, but calling it twice with the
4402 same event name assigns only one handler.
4404 Current target is temporarily overridden to the event issuing target
4405 before handler code starts and switched back after handler is done.
4407 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4408 whether the work area gets backed up; by default,
4409 @emph{it is not backed up.}
4410 When possible, use a working_area that doesn't need to be backed up,
4411 since performing a backup slows down operations.
4412 For example, the beginning of an SRAM block is likely to
4413 be used by most build systems, but the end is often unused.
4415 @item @code{-work-area-size} @var{size} -- specify work are size,
4416 in bytes. The same size applies regardless of whether its physical
4417 or virtual address is being used.
4419 @item @code{-work-area-phys} @var{address} -- set the work area
4420 base @var{address} to be used when no MMU is active.
4422 @item @code{-work-area-virt} @var{address} -- set the work area
4423 base @var{address} to be used when an MMU is active.
4424 @emph{Do not specify a value for this except on targets with an MMU.}
4425 The value should normally correspond to a static mapping for the
4426 @code{-work-area-phys} address, set up by the current operating system.
4429 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4430 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4431 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4432 @option{embKernel}, @option{mqx}, @option{uCOS-III}
4433 @xref{gdbrtossupport,,RTOS Support}.
4435 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4436 scan and after a reset. A manual call to arp_examine is required to
4437 access the target for debugging.
4439 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4440 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4441 Use this option with systems where multiple, independent cores are connected
4442 to separate access ports of the same DAP.
4444 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4445 to the target. Currently, only the @code{aarch64} target makes use of this option,
4446 where it is a mandatory configuration for the target run control.
4447 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4448 for instruction on how to declare and control a CTI instance.
4452 @section Other $target_name Commands
4453 @cindex object command
4455 The Tcl/Tk language has the concept of object commands,
4456 and OpenOCD adopts that same model for targets.
4458 A good Tk example is a on screen button.
4459 Once a button is created a button
4460 has a name (a path in Tk terms) and that name is useable as a first
4461 class command. For example in Tk, one can create a button and later
4462 configure it like this:
4466 button .foobar -background red -command @{ foo @}
4468 .foobar configure -foreground blue
4470 set x [.foobar cget -background]
4472 puts [format "The button is %s" $x]
4475 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4476 button, and its object commands are invoked the same way.
4479 str912.cpu mww 0x1234 0x42
4480 omap3530.cpu mww 0x5555 123
4483 The commands supported by OpenOCD target objects are:
4485 @deffn Command {$target_name arp_examine} @option{allow-defer}
4486 @deffnx Command {$target_name arp_halt}
4487 @deffnx Command {$target_name arp_poll}
4488 @deffnx Command {$target_name arp_reset}
4489 @deffnx Command {$target_name arp_waitstate}
4490 Internal OpenOCD scripts (most notably @file{startup.tcl})
4491 use these to deal with specific reset cases.
4492 They are not otherwise documented here.
4495 @deffn Command {$target_name array2mem} arrayname width address count
4496 @deffnx Command {$target_name mem2array} arrayname width address count
4497 These provide an efficient script-oriented interface to memory.
4498 The @code{array2mem} primitive writes bytes, halfwords, or words;
4499 while @code{mem2array} reads them.
4500 In both cases, the TCL side uses an array, and
4501 the target side uses raw memory.
4503 The efficiency comes from enabling the use of
4504 bulk JTAG data transfer operations.
4505 The script orientation comes from working with data
4506 values that are packaged for use by TCL scripts;
4507 @command{mdw} type primitives only print data they retrieve,
4508 and neither store nor return those values.
4511 @item @var{arrayname} ... is the name of an array variable
4512 @item @var{width} ... is 8/16/32 - indicating the memory access size
4513 @item @var{address} ... is the target memory address
4514 @item @var{count} ... is the number of elements to process
4518 @deffn Command {$target_name cget} queryparm
4519 Each configuration parameter accepted by
4520 @command{$target_name configure}
4521 can be individually queried, to return its current value.
4522 The @var{queryparm} is a parameter name
4523 accepted by that command, such as @code{-work-area-phys}.
4524 There are a few special cases:
4527 @item @code{-event} @var{event_name} -- returns the handler for the
4528 event named @var{event_name}.
4529 This is a special case because setting a handler requires
4531 @item @code{-type} -- returns the target type.
4532 This is a special case because this is set using
4533 @command{target create} and can't be changed
4534 using @command{$target_name configure}.
4537 For example, if you wanted to summarize information about
4538 all the targets you might use something like this:
4541 foreach name [target names] @{
4542 set y [$name cget -endian]
4543 set z [$name cget -type]
4544 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4550 @anchor{targetcurstate}
4551 @deffn Command {$target_name curstate}
4552 Displays the current target state:
4553 @code{debug-running},
4556 @code{running}, or @code{unknown}.
4557 (Also, @pxref{eventpolling,,Event Polling}.)
4560 @deffn Command {$target_name eventlist}
4561 Displays a table listing all event handlers
4562 currently associated with this target.
4563 @xref{targetevents,,Target Events}.
4566 @deffn Command {$target_name invoke-event} event_name
4567 Invokes the handler for the event named @var{event_name}.
4568 (This is primarily intended for use by OpenOCD framework
4569 code, for example by the reset code in @file{startup.tcl}.)
4572 @deffn Command {$target_name mdw} addr [count]
4573 @deffnx Command {$target_name mdh} addr [count]
4574 @deffnx Command {$target_name mdb} addr [count]
4575 Display contents of address @var{addr}, as
4576 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4577 or 8-bit bytes (@command{mdb}).
4578 If @var{count} is specified, displays that many units.
4579 (If you want to manipulate the data instead of displaying it,
4580 see the @code{mem2array} primitives.)
4583 @deffn Command {$target_name mww} addr word
4584 @deffnx Command {$target_name mwh} addr halfword
4585 @deffnx Command {$target_name mwb} addr byte
4586 Writes the specified @var{word} (32 bits),
4587 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4588 at the specified address @var{addr}.
4591 @anchor{targetevents}
4592 @section Target Events
4593 @cindex target events
4595 At various times, certain things can happen, or you want them to happen.
4598 @item What should happen when GDB connects? Should your target reset?
4599 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4600 @item Is using SRST appropriate (and possible) on your system?
4601 Or instead of that, do you need to issue JTAG commands to trigger reset?
4602 SRST usually resets everything on the scan chain, which can be inappropriate.
4603 @item During reset, do you need to write to certain memory locations
4604 to set up system clocks or
4605 to reconfigure the SDRAM?
4606 How about configuring the watchdog timer, or other peripherals,
4607 to stop running while you hold the core stopped for debugging?
4610 All of the above items can be addressed by target event handlers.
4611 These are set up by @command{$target_name configure -event} or
4612 @command{target create ... -event}.
4614 The programmer's model matches the @code{-command} option used in Tcl/Tk
4615 buttons and events. The two examples below act the same, but one creates
4616 and invokes a small procedure while the other inlines it.
4619 proc my_init_proc @{ @} @{
4620 echo "Disabling watchdog..."
4621 mww 0xfffffd44 0x00008000
4623 mychip.cpu configure -event reset-init my_init_proc
4624 mychip.cpu configure -event reset-init @{
4625 echo "Disabling watchdog..."
4626 mww 0xfffffd44 0x00008000
4630 The following target events are defined:
4633 @item @b{debug-halted}
4634 @* The target has halted for debug reasons (i.e.: breakpoint)
4635 @item @b{debug-resumed}
4636 @* The target has resumed (i.e.: GDB said run)
4637 @item @b{early-halted}
4638 @* Occurs early in the halt process
4639 @item @b{examine-start}
4640 @* Before target examine is called.
4641 @item @b{examine-end}
4642 @* After target examine is called with no errors.
4643 @item @b{gdb-attach}
4644 @* When GDB connects. Issued before any GDB communication with the target
4645 starts. GDB expects the target is halted during attachment.
4646 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4647 connect GDB to running target.
4648 The event can be also used to set up the target so it is possible to probe flash.
4649 Probing flash is necessary during GDB connect if you want to use
4650 @pxref{programmingusinggdb,,programming using GDB}.
4651 Another use of the flash memory map is for GDB to automatically choose
4652 hardware or software breakpoints depending on whether the breakpoint
4653 is in RAM or read only memory.
4654 Default is @code{halt}
4655 @item @b{gdb-detach}
4656 @* When GDB disconnects
4658 @* When the target has halted and GDB is not doing anything (see early halt)
4659 @item @b{gdb-flash-erase-start}
4660 @* Before the GDB flash process tries to erase the flash (default is
4662 @item @b{gdb-flash-erase-end}
4663 @* After the GDB flash process has finished erasing the flash
4664 @item @b{gdb-flash-write-start}
4665 @* Before GDB writes to the flash
4666 @item @b{gdb-flash-write-end}
4667 @* After GDB writes to the flash (default is @code{reset halt})
4669 @* Before the target steps, GDB is trying to start/resume the target
4671 @* The target has halted
4672 @item @b{reset-assert-pre}
4673 @* Issued as part of @command{reset} processing
4674 after @command{reset-start} was triggered
4675 but before either SRST alone is asserted on the scan chain,
4676 or @code{reset-assert} is triggered.
4677 @item @b{reset-assert}
4678 @* Issued as part of @command{reset} processing
4679 after @command{reset-assert-pre} was triggered.
4680 When such a handler is present, cores which support this event will use
4681 it instead of asserting SRST.
4682 This support is essential for debugging with JTAG interfaces which
4683 don't include an SRST line (JTAG doesn't require SRST), and for
4684 selective reset on scan chains that have multiple targets.
4685 @item @b{reset-assert-post}
4686 @* Issued as part of @command{reset} processing
4687 after @code{reset-assert} has been triggered.
4688 or the target asserted SRST on the entire scan chain.
4689 @item @b{reset-deassert-pre}
4690 @* Issued as part of @command{reset} processing
4691 after @code{reset-assert-post} has been triggered.
4692 @item @b{reset-deassert-post}
4693 @* Issued as part of @command{reset} processing
4694 after @code{reset-deassert-pre} has been triggered
4695 and (if the target is using it) after SRST has been
4696 released on the scan chain.
4698 @* Issued as the final step in @command{reset} processing.
4699 @item @b{reset-init}
4700 @* Used by @b{reset init} command for board-specific initialization.
4701 This event fires after @emph{reset-deassert-post}.
4703 This is where you would configure PLLs and clocking, set up DRAM so
4704 you can download programs that don't fit in on-chip SRAM, set up pin
4705 multiplexing, and so on.
4706 (You may be able to switch to a fast JTAG clock rate here, after
4707 the target clocks are fully set up.)
4708 @item @b{reset-start}
4709 @* Issued as the first step in @command{reset} processing
4710 before @command{reset-assert-pre} is called.
4712 This is the most robust place to use @command{jtag_rclk}
4713 or @command{adapter_khz} to switch to a low JTAG clock rate,
4714 when reset disables PLLs needed to use a fast clock.
4715 @item @b{resume-start}
4716 @* Before any target is resumed
4717 @item @b{resume-end}
4718 @* After all targets have resumed
4720 @* Target has resumed
4721 @item @b{trace-config}
4722 @* After target hardware trace configuration was changed
4725 @node Flash Commands
4726 @chapter Flash Commands
4728 OpenOCD has different commands for NOR and NAND flash;
4729 the ``flash'' command works with NOR flash, while
4730 the ``nand'' command works with NAND flash.
4731 This partially reflects different hardware technologies:
4732 NOR flash usually supports direct CPU instruction and data bus access,
4733 while data from a NAND flash must be copied to memory before it can be
4734 used. (SPI flash must also be copied to memory before use.)
4735 However, the documentation also uses ``flash'' as a generic term;
4736 for example, ``Put flash configuration in board-specific files''.
4740 @item Configure via the command @command{flash bank}
4741 @* Do this in a board-specific configuration file,
4742 passing parameters as needed by the driver.
4743 @item Operate on the flash via @command{flash subcommand}
4744 @* Often commands to manipulate the flash are typed by a human, or run
4745 via a script in some automated way. Common tasks include writing a
4746 boot loader, operating system, or other data.
4748 @* Flashing via GDB requires the flash be configured via ``flash
4749 bank'', and the GDB flash features be enabled.
4750 @xref{gdbconfiguration,,GDB Configuration}.
4753 Many CPUs have the ability to ``boot'' from the first flash bank.
4754 This means that misprogramming that bank can ``brick'' a system,
4755 so that it can't boot.
4756 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4757 board by (re)installing working boot firmware.
4759 @anchor{norconfiguration}
4760 @section Flash Configuration Commands
4761 @cindex flash configuration
4763 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4764 Configures a flash bank which provides persistent storage
4765 for addresses from @math{base} to @math{base + size - 1}.
4766 These banks will often be visible to GDB through the target's memory map.
4767 In some cases, configuring a flash bank will activate extra commands;
4768 see the driver-specific documentation.
4771 @item @var{name} ... may be used to reference the flash bank
4772 in other flash commands. A number is also available.
4773 @item @var{driver} ... identifies the controller driver
4774 associated with the flash bank being declared.
4775 This is usually @code{cfi} for external flash, or else
4776 the name of a microcontroller with embedded flash memory.
4777 @xref{flashdriverlist,,Flash Driver List}.
4778 @item @var{base} ... Base address of the flash chip.
4779 @item @var{size} ... Size of the chip, in bytes.
4780 For some drivers, this value is detected from the hardware.
4781 @item @var{chip_width} ... Width of the flash chip, in bytes;
4782 ignored for most microcontroller drivers.
4783 @item @var{bus_width} ... Width of the data bus used to access the
4784 chip, in bytes; ignored for most microcontroller drivers.
4785 @item @var{target} ... Names the target used to issue
4786 commands to the flash controller.
4787 @comment Actually, it's currently a controller-specific parameter...
4788 @item @var{driver_options} ... drivers may support, or require,
4789 additional parameters. See the driver-specific documentation
4790 for more information.
4793 This command is not available after OpenOCD initialization has completed.
4794 Use it in board specific configuration files, not interactively.
4798 @comment the REAL name for this command is "ocd_flash_banks"
4799 @comment less confusing would be: "flash list" (like "nand list")
4800 @deffn Command {flash banks}
4801 Prints a one-line summary of each device that was
4802 declared using @command{flash bank}, numbered from zero.
4803 Note that this is the @emph{plural} form;
4804 the @emph{singular} form is a very different command.
4807 @deffn Command {flash list}
4808 Retrieves a list of associative arrays for each device that was
4809 declared using @command{flash bank}, numbered from zero.
4810 This returned list can be manipulated easily from within scripts.
4813 @deffn Command {flash probe} num
4814 Identify the flash, or validate the parameters of the configured flash. Operation
4815 depends on the flash type.
4816 The @var{num} parameter is a value shown by @command{flash banks}.
4817 Most flash commands will implicitly @emph{autoprobe} the bank;
4818 flash drivers can distinguish between probing and autoprobing,
4819 but most don't bother.
4822 @section Erasing, Reading, Writing to Flash
4823 @cindex flash erasing
4824 @cindex flash reading
4825 @cindex flash writing
4826 @cindex flash programming
4827 @anchor{flashprogrammingcommands}
4829 One feature distinguishing NOR flash from NAND or serial flash technologies
4830 is that for read access, it acts exactly like any other addressable memory.
4831 This means you can use normal memory read commands like @command{mdw} or
4832 @command{dump_image} with it, with no special @command{flash} subcommands.
4833 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4835 Write access works differently. Flash memory normally needs to be erased
4836 before it's written. Erasing a sector turns all of its bits to ones, and
4837 writing can turn ones into zeroes. This is why there are special commands
4838 for interactive erasing and writing, and why GDB needs to know which parts
4839 of the address space hold NOR flash memory.
4842 Most of these erase and write commands leverage the fact that NOR flash
4843 chips consume target address space. They implicitly refer to the current
4844 JTAG target, and map from an address in that target's address space
4845 back to a flash bank.
4846 @comment In May 2009, those mappings may fail if any bank associated
4847 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
4848 A few commands use abstract addressing based on bank and sector numbers,
4849 and don't depend on searching the current target and its address space.
4850 Avoid confusing the two command models.
4853 Some flash chips implement software protection against accidental writes,
4854 since such buggy writes could in some cases ``brick'' a system.
4855 For such systems, erasing and writing may require sector protection to be
4857 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4858 and AT91SAM7 on-chip flash.
4859 @xref{flashprotect,,flash protect}.
4861 @deffn Command {flash erase_sector} num first last
4862 Erase sectors in bank @var{num}, starting at sector @var{first}
4863 up to and including @var{last}.
4864 Sector numbering starts at 0.
4865 Providing a @var{last} sector of @option{last}
4866 specifies "to the end of the flash bank".
4867 The @var{num} parameter is a value shown by @command{flash banks}.
4870 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4871 Erase sectors starting at @var{address} for @var{length} bytes.
4872 Unless @option{pad} is specified, @math{address} must begin a
4873 flash sector, and @math{address + length - 1} must end a sector.
4874 Specifying @option{pad} erases extra data at the beginning and/or
4875 end of the specified region, as needed to erase only full sectors.
4876 The flash bank to use is inferred from the @var{address}, and
4877 the specified length must stay within that bank.
4878 As a special case, when @var{length} is zero and @var{address} is
4879 the start of the bank, the whole flash is erased.
4880 If @option{unlock} is specified, then the flash is unprotected
4881 before erase starts.
4884 @deffn Command {flash fillw} address word length
4885 @deffnx Command {flash fillh} address halfword length
4886 @deffnx Command {flash fillb} address byte length
4887 Fills flash memory with the specified @var{word} (32 bits),
4888 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4889 starting at @var{address} and continuing
4890 for @var{length} units (word/halfword/byte).
4891 No erasure is done before writing; when needed, that must be done
4892 before issuing this command.
4893 Writes are done in blocks of up to 1024 bytes, and each write is
4894 verified by reading back the data and comparing it to what was written.
4895 The flash bank to use is inferred from the @var{address} of
4896 each block, and the specified length must stay within that bank.
4898 @comment no current checks for errors if fill blocks touch multiple banks!
4900 @deffn Command {flash write_bank} num filename [offset]
4901 Write the binary @file{filename} to flash bank @var{num},
4902 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
4903 is omitted, start at the beginning of the flash bank.
4904 The @var{num} parameter is a value shown by @command{flash banks}.
4907 @deffn Command {flash read_bank} num filename [offset [length]]
4908 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4909 and write the contents to the binary @file{filename}. If @var{offset} is
4910 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
4911 read the remaining bytes from the flash bank.
4912 The @var{num} parameter is a value shown by @command{flash banks}.
4915 @deffn Command {flash verify_bank} num filename [offset]
4916 Compare the contents of the binary file @var{filename} with the contents of the
4917 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
4918 start at the beginning of the flash bank. Fail if the contents do not match.
4919 The @var{num} parameter is a value shown by @command{flash banks}.
4922 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4923 Write the image @file{filename} to the current target's flash bank(s).
4924 Only loadable sections from the image are written.
4925 A relocation @var{offset} may be specified, in which case it is added
4926 to the base address for each section in the image.
4927 The file [@var{type}] can be specified
4928 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4929 @option{elf} (ELF file), @option{s19} (Motorola s19).
4930 @option{mem}, or @option{builder}.
4931 The relevant flash sectors will be erased prior to programming
4932 if the @option{erase} parameter is given. If @option{unlock} is
4933 provided, then the flash banks are unlocked before erase and
4934 program. The flash bank to use is inferred from the address of
4938 Be careful using the @option{erase} flag when the flash is holding
4939 data you want to preserve.
4940 Portions of the flash outside those described in the image's
4941 sections might be erased with no notice.
4944 When a section of the image being written does not fill out all the
4945 sectors it uses, the unwritten parts of those sectors are necessarily
4946 also erased, because sectors can't be partially erased.
4948 Data stored in sector "holes" between image sections are also affected.
4949 For example, "@command{flash write_image erase ...}" of an image with
4950 one byte at the beginning of a flash bank and one byte at the end
4951 erases the entire bank -- not just the two sectors being written.
4953 Also, when flash protection is important, you must re-apply it after
4954 it has been removed by the @option{unlock} flag.
4959 @section Other Flash commands
4960 @cindex flash protection
4962 @deffn Command {flash erase_check} num
4963 Check erase state of sectors in flash bank @var{num},
4964 and display that status.
4965 The @var{num} parameter is a value shown by @command{flash banks}.
4968 @deffn Command {flash info} num [sectors]
4969 Print info about flash bank @var{num}, a list of protection blocks
4970 and their status. Use @option{sectors} to show a list of sectors instead.
4972 The @var{num} parameter is a value shown by @command{flash banks}.
4973 This command will first query the hardware, it does not print cached
4974 and possibly stale information.
4977 @anchor{flashprotect}
4978 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4979 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
4980 in flash bank @var{num}, starting at protection block @var{first}
4981 and continuing up to and including @var{last}.
4982 Providing a @var{last} block of @option{last}
4983 specifies "to the end of the flash bank".
4984 The @var{num} parameter is a value shown by @command{flash banks}.
4985 The protection block is usually identical to a flash sector.
4986 Some devices may utilize a protection block distinct from flash sector.
4987 See @command{flash info} for a list of protection blocks.
4990 @deffn Command {flash padded_value} num value
4991 Sets the default value used for padding any image sections, This should
4992 normally match the flash bank erased value. If not specified by this
4993 command or the flash driver then it defaults to 0xff.
4997 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4998 This is a helper script that simplifies using OpenOCD as a standalone
4999 programmer. The only required parameter is @option{filename}, the others are optional.
5000 @xref{Flash Programming}.
5003 @anchor{flashdriverlist}
5004 @section Flash Driver List
5005 As noted above, the @command{flash bank} command requires a driver name,
5006 and allows driver-specific options and behaviors.
5007 Some drivers also activate driver-specific commands.
5009 @deffn {Flash Driver} virtual
5010 This is a special driver that maps a previously defined bank to another
5011 address. All bank settings will be copied from the master physical bank.
5013 The @var{virtual} driver defines one mandatory parameters,
5016 @item @var{master_bank} The bank that this virtual address refers to.
5019 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5020 the flash bank defined at address 0x1fc00000. Any command executed on
5021 the virtual banks is actually performed on the physical banks.
5023 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5024 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5025 $_TARGETNAME $_FLASHNAME
5026 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5027 $_TARGETNAME $_FLASHNAME
5031 @subsection External Flash
5033 @deffn {Flash Driver} cfi
5034 @cindex Common Flash Interface
5036 The ``Common Flash Interface'' (CFI) is the main standard for
5037 external NOR flash chips, each of which connects to a
5038 specific external chip select on the CPU.
5039 Frequently the first such chip is used to boot the system.
5040 Your board's @code{reset-init} handler might need to
5041 configure additional chip selects using other commands (like: @command{mww} to
5042 configure a bus and its timings), or
5043 perhaps configure a GPIO pin that controls the ``write protect'' pin
5045 The CFI driver can use a target-specific working area to significantly
5048 The CFI driver can accept the following optional parameters, in any order:
5051 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5052 like AM29LV010 and similar types.
5053 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5054 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5055 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5056 swapped when writing data values (i.e. not CFI commands).
5059 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5060 wide on a sixteen bit bus:
5063 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5064 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5067 To configure one bank of 32 MBytes
5068 built from two sixteen bit (two byte) wide parts wired in parallel
5069 to create a thirty-two bit (four byte) bus with doubled throughput:
5072 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5075 @c "cfi part_id" disabled
5078 @deffn {Flash Driver} jtagspi
5079 @cindex Generic JTAG2SPI driver
5083 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5084 SPI flash connected to them. To access this flash from the host, the device
5085 is first programmed with a special proxy bitstream that
5086 exposes the SPI flash on the device's JTAG interface. The flash can then be
5087 accessed through JTAG.
5089 Since signaling between JTAG and SPI is compatible, all that is required for
5090 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5091 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5092 a bitstream for several Xilinx FPGAs can be found in
5093 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5094 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5096 This flash bank driver requires a target on a JTAG tap and will access that
5097 tap directly. Since no support from the target is needed, the target can be a
5098 "testee" dummy. Since the target does not expose the flash memory
5099 mapping, target commands that would otherwise be expected to access the flash
5100 will not work. These include all @command{*_image} and
5101 @command{$target_name m*} commands as well as @command{program}. Equivalent
5102 functionality is available through the @command{flash write_bank},
5103 @command{flash read_bank}, and @command{flash verify_bank} commands.
5106 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5107 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5108 @var{USER1} instruction.
5112 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5113 set _XILINX_USER1 0x02
5114 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5115 $_TARGETNAME $_XILINX_USER1
5119 @deffn {Flash Driver} xcf
5120 @cindex Xilinx Platform flash driver
5122 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5123 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5124 only difference is special registers controlling its FPGA specific behavior.
5125 They must be properly configured for successful FPGA loading using
5126 additional @var{xcf} driver command:
5128 @deffn Command {xcf ccb} <bank_id>
5129 command accepts additional parameters:
5131 @item @var{external|internal} ... selects clock source.
5132 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5133 @item @var{slave|master} ... selects slave of master mode for flash device.
5134 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5138 xcf ccb 0 external parallel slave 40
5140 All of them must be specified even if clock frequency is pointless
5141 in slave mode. If only bank id specified than command prints current
5142 CCB register value. Note: there is no need to write this register
5143 every time you erase/program data sectors because it stores in
5147 @deffn Command {xcf configure} <bank_id>
5148 Initiates FPGA loading procedure. Useful if your board has no "configure"
5155 Additional driver notes:
5157 @item Only single revision supported.
5158 @item Driver automatically detects need of bit reverse, but
5159 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5160 (Intel hex) file types supported.
5161 @item For additional info check xapp972.pdf and ug380.pdf.
5165 @deffn {Flash Driver} lpcspifi
5166 @cindex NXP SPI Flash Interface
5169 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5170 Flash Interface (SPIFI) peripheral that can drive and provide
5171 memory mapped access to external SPI flash devices.
5173 The lpcspifi driver initializes this interface and provides
5174 program and erase functionality for these serial flash devices.
5175 Use of this driver @b{requires} a working area of at least 1kB
5176 to be configured on the target device; more than this will
5177 significantly reduce flash programming times.
5179 The setup command only requires the @var{base} parameter. All
5180 other parameters are ignored, and the flash size and layout
5181 are configured by the driver.
5184 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5189 @deffn {Flash Driver} stmsmi
5190 @cindex STMicroelectronics Serial Memory Interface
5193 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5194 SPEAr MPU family) include a proprietary
5195 ``Serial Memory Interface'' (SMI) controller able to drive external
5197 Depending on specific device and board configuration, up to 4 external
5198 flash devices can be connected.
5200 SMI makes the flash content directly accessible in the CPU address
5201 space; each external device is mapped in a memory bank.
5202 CPU can directly read data, execute code and boot from SMI banks.
5203 Normal OpenOCD commands like @command{mdw} can be used to display
5206 The setup command only requires the @var{base} parameter in order
5207 to identify the memory bank.
5208 All other parameters are ignored. Additional information, like
5209 flash size, are detected automatically.
5212 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5217 @deffn {Flash Driver} mrvlqspi
5218 This driver supports QSPI flash controller of Marvell's Wireless
5219 Microcontroller platform.
5221 The flash size is autodetected based on the table of known JEDEC IDs
5222 hardcoded in the OpenOCD sources.
5225 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5230 @deffn {Flash Driver} ath79
5231 @cindex Atheros ath79 SPI driver
5233 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5235 On reset a SPI flash connected to the first chip select (CS0) is made
5236 directly read-accessible in the CPU address space (up to 16MBytes)
5237 and is usually used to store the bootloader and operating system.
5238 Normal OpenOCD commands like @command{mdw} can be used to display
5239 the flash content while it is in memory-mapped mode (only the first
5240 4MBytes are accessible without additional configuration on reset).
5242 The setup command only requires the @var{base} parameter in order
5243 to identify the memory bank. The actual value for the base address
5244 is not otherwise used by the driver. However the mapping is passed
5245 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5246 address should be the actual memory mapped base address. For unmapped
5247 chipselects (CS1 and CS2) care should be taken to use a base address
5248 that does not overlap with real memory regions.
5249 Additional information, like flash size, are detected automatically.
5250 An optional additional parameter sets the chipselect for the bank,
5251 with the default CS0.
5252 CS1 and CS2 require additional GPIO setup before they can be used
5253 since the alternate function must be enabled on the GPIO pin
5254 CS1/CS2 is routed to on the given SoC.
5257 flash bank $_FLASHNAME ath79 0 0 0 0 $_TARGETNAME
5259 # When using multiple chipselects the base should be different for each,
5260 # otherwise the write_image command is not able to distinguish the
5262 flash bank flash0 ath79 0x00000000 0 0 0 $_TARGETNAME cs0
5263 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5264 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5269 @subsection Internal Flash (Microcontrollers)
5271 @deffn {Flash Driver} aduc702x
5272 The ADUC702x analog microcontrollers from Analog Devices
5273 include internal flash and use ARM7TDMI cores.
5274 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5275 The setup command only requires the @var{target} argument
5276 since all devices in this family have the same memory layout.
5279 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5283 @deffn {Flash Driver} ambiqmicro
5286 All members of the Apollo microcontroller family from
5287 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5288 The host connects over USB to an FTDI interface that communicates
5289 with the target using SWD.
5291 The @var{ambiqmicro} driver reads the Chip Information Register detect
5292 the device class of the MCU.
5293 The Flash and SRAM sizes directly follow device class, and are used
5294 to set up the flash banks.
5295 If this fails, the driver will use default values set to the minimum
5296 sizes of an Apollo chip.
5298 All Apollo chips have two flash banks of the same size.
5299 In all cases the first flash bank starts at location 0,
5300 and the second bank starts after the first.
5304 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5305 # Flash bank 1 - same size as bank0, starts after bank 0.
5306 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5310 Flash is programmed using custom entry points into the bootloader.
5311 This is the only way to program the flash as no flash control registers
5312 are available to the user.
5314 The @var{ambiqmicro} driver adds some additional commands:
5316 @deffn Command {ambiqmicro mass_erase} <bank>
5319 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5322 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5323 Program OTP is a one time operation to create write protected flash.
5324 The user writes sectors to SRAM starting at 0x10000010.
5325 Program OTP will write these sectors from SRAM to flash, and write protect
5331 @deffn {Flash Driver} at91samd
5333 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
5334 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5335 This driver uses the same command names/syntax as @xref{at91sam3}.
5337 @deffn Command {at91samd chip-erase}
5338 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5339 used to erase a chip back to its factory state and does not require the
5340 processor to be halted.
5343 @deffn Command {at91samd set-security}
5344 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5345 to the Flash and can only be undone by using the chip-erase command which
5346 erases the Flash contents and turns off the security bit. Warning: at this
5347 time, openocd will not be able to communicate with a secured chip and it is
5348 therefore not possible to chip-erase it without using another tool.
5351 at91samd set-security enable
5355 @deffn Command {at91samd eeprom}
5356 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5357 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5358 must be one of the permitted sizes according to the datasheet. Settings are
5359 written immediately but only take effect on MCU reset. EEPROM emulation
5360 requires additional firmware support and the minimum EEPROM size may not be
5361 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5362 in order to disable this feature.
5366 at91samd eeprom 1024
5370 @deffn Command {at91samd bootloader}
5371 Shows or sets the bootloader size configuration, stored in the User Row of the
5372 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5373 must be specified in bytes and it must be one of the permitted sizes according
5374 to the datasheet. Settings are written immediately but only take effect on
5375 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5379 at91samd bootloader 16384
5383 @deffn Command {at91samd dsu_reset_deassert}
5384 This command releases internal reset held by DSU
5385 and prepares reset vector catch in case of reset halt.
5386 Command is used internally in event event reset-deassert-post.
5389 @deffn Command {at91samd nvmuserrow}
5390 Writes or reads the entire 64 bit wide NVM user row register which is located at
5391 0x804000. This register includes various fuses lock-bits and factory calibration
5392 data. Reading the register is done by invoking this command without any
5393 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
5394 is the register value to be written and the second one is an optional changemask.
5395 Every bit which value in changemask is 0 will stay unchanged. The lock- and
5396 reserved-bits are masked out and cannot be changed.
5400 >at91samd nvmuserrow
5401 NVMUSERROW: 0xFFFFFC5DD8E0C788
5402 # Write 0xFFFFFC5DD8E0C788 to user row
5403 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
5404 # Write 0x12300 to user row but leave other bits and low byte unchanged
5405 >at91samd nvmuserrow 0x12345 0xFFF00
5412 @deffn {Flash Driver} at91sam3
5414 All members of the AT91SAM3 microcontroller family from
5415 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5416 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5417 that the driver was orginaly developed and tested using the
5418 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5419 the family was cribbed from the data sheet. @emph{Note to future
5420 readers/updaters: Please remove this worrisome comment after other
5421 chips are confirmed.}
5423 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5424 have one flash bank. In all cases the flash banks are at
5425 the following fixed locations:
5428 # Flash bank 0 - all chips
5429 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5430 # Flash bank 1 - only 256K chips
5431 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5434 Internally, the AT91SAM3 flash memory is organized as follows.
5435 Unlike the AT91SAM7 chips, these are not used as parameters
5436 to the @command{flash bank} command:
5439 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5440 @item @emph{Bank Size:} 128K/64K Per flash bank
5441 @item @emph{Sectors:} 16 or 8 per bank
5442 @item @emph{SectorSize:} 8K Per Sector
5443 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5446 The AT91SAM3 driver adds some additional commands:
5448 @deffn Command {at91sam3 gpnvm}
5449 @deffnx Command {at91sam3 gpnvm clear} number
5450 @deffnx Command {at91sam3 gpnvm set} number
5451 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5452 With no parameters, @command{show} or @command{show all},
5453 shows the status of all GPNVM bits.
5454 With @command{show} @var{number}, displays that bit.
5456 With @command{set} @var{number} or @command{clear} @var{number},
5457 modifies that GPNVM bit.
5460 @deffn Command {at91sam3 info}
5461 This command attempts to display information about the AT91SAM3
5462 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5463 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5464 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5465 various clock configuration registers and attempts to display how it
5466 believes the chip is configured. By default, the SLOWCLK is assumed to
5467 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5470 @deffn Command {at91sam3 slowclk} [value]
5471 This command shows/sets the slow clock frequency used in the
5472 @command{at91sam3 info} command calculations above.
5476 @deffn {Flash Driver} at91sam4
5478 All members of the AT91SAM4 microcontroller family from
5479 Atmel include internal flash and use ARM's Cortex-M4 core.
5480 This driver uses the same command names/syntax as @xref{at91sam3}.
5483 @deffn {Flash Driver} at91sam4l
5485 All members of the AT91SAM4L microcontroller family from
5486 Atmel include internal flash and use ARM's Cortex-M4 core.
5487 This driver uses the same command names/syntax as @xref{at91sam3}.
5489 The AT91SAM4L driver adds some additional commands:
5490 @deffn Command {at91sam4l smap_reset_deassert}
5491 This command releases internal reset held by SMAP
5492 and prepares reset vector catch in case of reset halt.
5493 Command is used internally in event event reset-deassert-post.
5497 @deffn {Flash Driver} atsamv
5499 All members of the ATSAMV, ATSAMS, and ATSAME families from
5500 Atmel include internal flash and use ARM's Cortex-M7 core.
5501 This driver uses the same command names/syntax as @xref{at91sam3}.
5504 @deffn {Flash Driver} at91sam7
5505 All members of the AT91SAM7 microcontroller family from Atmel include
5506 internal flash and use ARM7TDMI cores. The driver automatically
5507 recognizes a number of these chips using the chip identification
5508 register, and autoconfigures itself.
5511 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5514 For chips which are not recognized by the controller driver, you must
5515 provide additional parameters in the following order:
5518 @item @var{chip_model} ... label used with @command{flash info}
5520 @item @var{sectors_per_bank}
5521 @item @var{pages_per_sector}
5522 @item @var{pages_size}
5523 @item @var{num_nvm_bits}
5524 @item @var{freq_khz} ... required if an external clock is provided,
5525 optional (but recommended) when the oscillator frequency is known
5528 It is recommended that you provide zeroes for all of those values
5529 except the clock frequency, so that everything except that frequency
5530 will be autoconfigured.
5531 Knowing the frequency helps ensure correct timings for flash access.
5533 The flash controller handles erases automatically on a page (128/256 byte)
5534 basis, so explicit erase commands are not necessary for flash programming.
5535 However, there is an ``EraseAll`` command that can erase an entire flash
5536 plane (of up to 256KB), and it will be used automatically when you issue
5537 @command{flash erase_sector} or @command{flash erase_address} commands.
5539 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5540 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5541 bit for the processor. Each processor has a number of such bits,
5542 used for controlling features such as brownout detection (so they
5543 are not truly general purpose).
5545 This assumes that the first flash bank (number 0) is associated with
5546 the appropriate at91sam7 target.
5551 @deffn {Flash Driver} avr
5552 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5553 @emph{The current implementation is incomplete.}
5554 @comment - defines mass_erase ... pointless given flash_erase_address
5557 @deffn {Flash Driver} bluenrg-x
5558 STMicroelectronics BlueNRG-1 and BlueNRG-2 Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0 core and internal flash memory.
5559 The driver automatically recognizes these chips using
5560 the chip identification registers, and autoconfigures itself.
5563 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
5566 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
5567 each single sector one by one.
5570 flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
5574 flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
5577 Triggering a mass erase is also useful when users want to disable readout protection.
5580 @deffn {Flash Driver} cc26xx
5581 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
5582 Instruments include internal flash. The cc26xx flash driver supports both the
5583 CC13xx and CC26xx family of devices. The driver automatically recognizes the
5584 specific version's flash parameters and autoconfigures itself. Flash bank 0
5585 starts at address 0.
5588 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
5592 @deffn {Flash Driver} cc3220sf
5593 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
5594 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
5595 supports the internal flash. The serial flash on SimpleLink boards is
5596 programmed via the bootloader over a UART connection. Security features of
5597 the CC3220SF may erase the internal flash during power on reset. Refer to
5598 documentation at @url{www.ti.com/cc3220sf} for details on security features
5599 and programming the serial flash.
5602 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
5606 @deffn {Flash Driver} efm32
5607 All members of the EFM32 microcontroller family from Energy Micro include
5608 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5609 a number of these chips using the chip identification register, and
5610 autoconfigures itself.
5612 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5614 A special feature of efm32 controllers is that it is possible to completely disable the
5615 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5616 this via the following command:
5620 The @var{num} parameter is a value shown by @command{flash banks}.
5621 Note that in order for this command to take effect, the target needs to be reset.
5622 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5626 @deffn {Flash Driver} fm3
5627 All members of the FM3 microcontroller family from Fujitsu
5628 include internal flash and use ARM Cortex-M3 cores.
5629 The @var{fm3} driver uses the @var{target} parameter to select the
5630 correct bank config, it can currently be one of the following:
5631 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5632 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5635 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5639 @deffn {Flash Driver} fm4
5640 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5641 include internal flash and use ARM Cortex-M4 cores.
5642 The @var{fm4} driver uses a @var{family} parameter to select the
5643 correct bank config, it can currently be one of the following:
5644 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5645 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5646 with @code{x} treated as wildcard and otherwise case (and any trailing
5647 characters) ignored.
5650 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
5651 $_TARGETNAME S6E2CCAJ0A
5652 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
5653 $_TARGETNAME S6E2CCAJ0A
5655 @emph{The current implementation is incomplete. Protection is not supported,
5656 nor is Chip Erase (only Sector Erase is implemented).}
5659 @deffn {Flash Driver} kinetis
5661 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
5662 from NXP (former Freescale) include
5663 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
5664 recognizes flash size and a number of flash banks (1-4) using the chip
5665 identification register, and autoconfigures itself.
5666 Use kinetis_ke driver for KE0x and KEAx devices.
5668 The @var{kinetis} driver defines option:
5670 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
5674 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5677 @deffn Command {kinetis create_banks}
5678 Configuration command enables automatic creation of additional flash banks
5679 based on real flash layout of device. Banks are created during device probe.
5680 Use 'flash probe 0' to force probe.
5683 @deffn Command {kinetis fcf_source} [protection|write]
5684 Select what source is used when writing to a Flash Configuration Field.
5685 @option{protection} mode builds FCF content from protection bits previously
5686 set by 'flash protect' command.
5687 This mode is default. MCU is protected from unwanted locking by immediate
5688 writing FCF after erase of relevant sector.
5689 @option{write} mode enables direct write to FCF.
5690 Protection cannot be set by 'flash protect' command. FCF is written along
5691 with the rest of a flash image.
5692 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
5695 @deffn Command {kinetis fopt} [num]
5696 Set value to write to FOPT byte of Flash Configuration Field.
5697 Used in kinetis 'fcf_source protection' mode only.
5700 @deffn Command {kinetis mdm check_security}
5701 Checks status of device security lock. Used internally in examine-end event.
5704 @deffn Command {kinetis mdm halt}
5705 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
5706 loop when connecting to an unsecured target.
5709 @deffn Command {kinetis mdm mass_erase}
5710 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
5711 back to its factory state, removing security. It does not require the processor
5712 to be halted, however the target will remain in a halted state after this
5716 @deffn Command {kinetis nvm_partition}
5717 For FlexNVM devices only (KxxDX and KxxFX).
5718 Command shows or sets data flash or EEPROM backup size in kilobytes,
5719 sets two EEPROM blocks sizes in bytes and enables/disables loading
5720 of EEPROM contents to FlexRAM during reset.
5722 For details see device reference manual, Flash Memory Module,
5723 Program Partition command.
5725 Setting is possible only once after mass_erase.
5726 Reset the device after partition setting.
5728 Show partition size:
5730 kinetis nvm_partition info
5733 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
5734 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
5736 kinetis nvm_partition dataflash 32 512 1536 on
5739 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
5740 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
5742 kinetis nvm_partition eebkp 16 1024 1024 off
5746 @deffn Command {kinetis mdm reset}
5747 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
5748 RESET pin, which can be used to reset other hardware on board.
5751 @deffn Command {kinetis disable_wdog}
5752 For Kx devices only (KLx has different COP watchdog, it is not supported).
5753 Command disables watchdog timer.
5757 @deffn {Flash Driver} kinetis_ke
5759 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
5760 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
5761 the KE0x sub-family using the chip identification register, and
5762 autoconfigures itself.
5763 Use kinetis (not kinetis_ke) driver for KE1x devices.
5766 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
5769 @deffn Command {kinetis_ke mdm check_security}
5770 Checks status of device security lock. Used internally in examine-end event.
5773 @deffn Command {kinetis_ke mdm mass_erase}
5774 Issues a complete Flash erase via the MDM-AP.
5775 This can be used to erase a chip back to its factory state.
5776 Command removes security lock from a device (use of SRST highly recommended).
5777 It does not require the processor to be halted.
5780 @deffn Command {kinetis_ke disable_wdog}
5781 Command disables watchdog timer.
5785 @deffn {Flash Driver} lpc2000
5786 This is the driver to support internal flash of all members of the
5787 LPC11(x)00 and LPC1300 microcontroller families and most members of
5788 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
5789 microcontroller families from NXP.
5792 There are LPC2000 devices which are not supported by the @var{lpc2000}
5794 The LPC2888 is supported by the @var{lpc288x} driver.
5795 The LPC29xx family is supported by the @var{lpc2900} driver.
5798 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5799 which must appear in the following order:
5802 @item @var{variant} ... required, may be
5803 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5804 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5805 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
5806 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5808 @option{lpc800} (LPC8xx)
5809 @option{lpc1100} (LPC11(x)xx and LPC13xx)
5810 @option{lpc1500} (LPC15xx)
5811 @option{lpc54100} (LPC541xx)
5812 @option{lpc4000} (LPC40xx)
5813 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
5814 LPC8xx, LPC13xx, LPC17xx and LPC40xx
5815 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5816 at which the core is running
5817 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5818 telling the driver to calculate a valid checksum for the exception vector table.
5820 If you don't provide @option{calc_checksum} when you're writing the vector
5821 table, the boot ROM will almost certainly ignore your flash image.
5822 However, if you do provide it,
5823 with most tool chains @command{verify_image} will fail.
5827 LPC flashes don't require the chip and bus width to be specified.
5830 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5831 lpc2000_v2 14765 calc_checksum
5834 @deffn {Command} {lpc2000 part_id} bank
5835 Displays the four byte part identifier associated with
5836 the specified flash @var{bank}.
5840 @deffn {Flash Driver} lpc288x
5841 The LPC2888 microcontroller from NXP needs slightly different flash
5842 support from its lpc2000 siblings.
5843 The @var{lpc288x} driver defines one mandatory parameter,
5844 the programming clock rate in Hz.
5845 LPC flashes don't require the chip and bus width to be specified.
5848 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5852 @deffn {Flash Driver} lpc2900
5853 This driver supports the LPC29xx ARM968E based microcontroller family
5856 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5857 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5858 sector layout are auto-configured by the driver.
5859 The driver has one additional mandatory parameter: The CPU clock rate
5860 (in kHz) at the time the flash operations will take place. Most of the time this
5861 will not be the crystal frequency, but a higher PLL frequency. The
5862 @code{reset-init} event handler in the board script is usually the place where
5865 The driver rejects flashless devices (currently the LPC2930).
5867 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5868 It must be handled much more like NAND flash memory, and will therefore be
5869 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5871 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5872 sector needs to be erased or programmed, it is automatically unprotected.
5873 What is shown as protection status in the @code{flash info} command, is
5874 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5875 sector from ever being erased or programmed again. As this is an irreversible
5876 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5877 and not by the standard @code{flash protect} command.
5879 Example for a 125 MHz clock frequency:
5881 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5884 Some @code{lpc2900}-specific commands are defined. In the following command list,
5885 the @var{bank} parameter is the bank number as obtained by the
5886 @code{flash banks} command.
5888 @deffn Command {lpc2900 signature} bank
5889 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
5890 content. This is a hardware feature of the flash block, hence the calculation is
5891 very fast. You may use this to verify the content of a programmed device against
5896 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
5900 @deffn Command {lpc2900 read_custom} bank filename
5901 Reads the 912 bytes of customer information from the flash index sector, and
5902 saves it to a file in binary format.
5905 lpc2900 read_custom 0 /path_to/customer_info.bin
5909 The index sector of the flash is a @emph{write-only} sector. It cannot be
5910 erased! In order to guard against unintentional write access, all following
5911 commands need to be preceded by a successful call to the @code{password}
5914 @deffn Command {lpc2900 password} bank password
5915 You need to use this command right before each of the following commands:
5916 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
5917 @code{lpc2900 secure_jtag}.
5919 The password string is fixed to "I_know_what_I_am_doing".
5922 lpc2900 password 0 I_know_what_I_am_doing
5923 Potentially dangerous operation allowed in next command!
5927 @deffn Command {lpc2900 write_custom} bank filename type
5928 Writes the content of the file into the customer info space of the flash index
5929 sector. The filetype can be specified with the @var{type} field. Possible values
5930 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
5931 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
5932 contain a single section, and the contained data length must be exactly
5934 @quotation Attention
5935 This cannot be reverted! Be careful!
5939 lpc2900 write_custom 0 /path_to/customer_info.bin bin
5943 @deffn Command {lpc2900 secure_sector} bank first last
5944 Secures the sector range from @var{first} to @var{last} (including) against
5945 further program and erase operations. The sector security will be effective
5946 after the next power cycle.
5947 @quotation Attention
5948 This cannot be reverted! Be careful!
5950 Secured sectors appear as @emph{protected} in the @code{flash info} command.
5953 lpc2900 secure_sector 0 1 1
5955 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
5956 # 0: 0x00000000 (0x2000 8kB) not protected
5957 # 1: 0x00002000 (0x2000 8kB) protected
5958 # 2: 0x00004000 (0x2000 8kB) not protected
5962 @deffn Command {lpc2900 secure_jtag} bank
5963 Irreversibly disable the JTAG port. The new JTAG security setting will be
5964 effective after the next power cycle.
5965 @quotation Attention
5966 This cannot be reverted! Be careful!
5970 lpc2900 secure_jtag 0
5975 @deffn {Flash Driver} mdr
5976 This drivers handles the integrated NOR flash on Milandr Cortex-M
5977 based controllers. A known limitation is that the Info memory can't be
5978 read or verified as it's not memory mapped.
5981 flash bank <name> mdr <base> <size> \
5982 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
5986 @item @var{type} - 0 for main memory, 1 for info memory
5987 @item @var{page_count} - total number of pages
5988 @item @var{sec_count} - number of sector per page count
5993 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
5994 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
5995 0 0 $_TARGETNAME 1 1 4
5997 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
5998 0 0 $_TARGETNAME 0 32 4
6003 @deffn {Flash Driver} niietcm4
6004 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6005 based controllers. Flash size and sector layout are auto-configured by the driver.
6006 Main flash memory is called "Bootflash" and has main region and info region.
6007 Info region is NOT memory mapped by default,
6008 but it can replace first part of main region if needed.
6009 Full erase, single and block writes are supported for both main and info regions.
6010 There is additional not memory mapped flash called "Userflash", which
6011 also have division into regions: main and info.
6012 Purpose of userflash - to store system and user settings.
6013 Driver has special commands to perform operations with this memory.
6016 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6019 Some niietcm4-specific commands are defined:
6021 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
6022 Read byte from main or info userflash region.
6025 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6026 Write byte to main or info userflash region.
6029 @deffn Command {niietcm4 uflash_full_erase} bank
6030 Erase all userflash including info region.
6033 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6034 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6037 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
6038 Check sectors protect.
6041 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6042 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6045 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
6046 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6049 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6050 Configure external memory interface for boot.
6053 @deffn Command {niietcm4 service_mode_erase} bank
6054 Perform emergency erase of all flash (bootflash and userflash).
6057 @deffn Command {niietcm4 driver_info} bank
6058 Show information about flash driver.
6063 @deffn {Flash Driver} nrf5
6064 All members of the nRF51 microcontroller families from Nordic Semiconductor
6065 include internal flash and use ARM Cortex-M0 core.
6066 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
6067 internal flash and use an ARM Cortex-M4F core.
6070 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6073 Some nrf5-specific commands are defined:
6075 @deffn Command {nrf5 mass_erase}
6076 Erases the contents of the code memory and user information
6077 configuration registers as well. It must be noted that this command
6078 works only for chips that do not have factory pre-programmed region 0
6084 @deffn {Flash Driver} ocl
6085 This driver is an implementation of the ``on chip flash loader''
6086 protocol proposed by Pavel Chromy.
6088 It is a minimalistic command-response protocol intended to be used
6089 over a DCC when communicating with an internal or external flash
6090 loader running from RAM. An example implementation for AT91SAM7x is
6091 available in @file{contrib/loaders/flash/at91sam7x/}.
6094 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6098 @deffn {Flash Driver} pic32mx
6099 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6100 and integrate flash memory.
6103 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6104 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6107 @comment numerous *disabled* commands are defined:
6108 @comment - chip_erase ... pointless given flash_erase_address
6109 @comment - lock, unlock ... pointless given protect on/off (yes?)
6110 @comment - pgm_word ... shouldn't bank be deduced from address??
6111 Some pic32mx-specific commands are defined:
6112 @deffn Command {pic32mx pgm_word} address value bank
6113 Programs the specified 32-bit @var{value} at the given @var{address}
6114 in the specified chip @var{bank}.
6116 @deffn Command {pic32mx unlock} bank
6117 Unlock and erase specified chip @var{bank}.
6118 This will remove any Code Protection.
6122 @deffn {Flash Driver} psoc4
6123 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6124 include internal flash and use ARM Cortex-M0 cores.
6125 The driver automatically recognizes a number of these chips using
6126 the chip identification register, and autoconfigures itself.
6128 Note: Erased internal flash reads as 00.
6129 System ROM of PSoC 4 does not implement erase of a flash sector.
6132 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6135 psoc4-specific commands
6136 @deffn Command {psoc4 flash_autoerase} num (on|off)
6137 Enables or disables autoerase mode for a flash bank.
6139 If flash_autoerase is off, use mass_erase before flash programming.
6140 Flash erase command fails if region to erase is not whole flash memory.
6142 If flash_autoerase is on, a sector is both erased and programmed in one
6143 system ROM call. Flash erase command is ignored.
6144 This mode is suitable for gdb load.
6146 The @var{num} parameter is a value shown by @command{flash banks}.
6149 @deffn Command {psoc4 mass_erase} num
6150 Erases the contents of the flash memory, protection and security lock.
6152 The @var{num} parameter is a value shown by @command{flash banks}.
6156 @deffn {Flash Driver} psoc5lp
6157 All members of the PSoC 5LP microcontroller family from Cypress
6158 include internal program flash and use ARM Cortex-M3 cores.
6159 The driver probes for a number of these chips and autoconfigures itself,
6160 apart from the base address.
6163 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
6166 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
6167 @quotation Attention
6168 If flash operations are performed in ECC-disabled mode, they will also affect
6169 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
6170 then also erase the corresponding 2k data bytes in the 0x48000000 area.
6171 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
6174 Commands defined in the @var{psoc5lp} driver:
6176 @deffn Command {psoc5lp mass_erase}
6177 Erases all flash data and ECC/configuration bytes, all flash protection rows,
6178 and all row latches in all flash arrays on the device.
6182 @deffn {Flash Driver} psoc5lp_eeprom
6183 All members of the PSoC 5LP microcontroller family from Cypress
6184 include internal EEPROM and use ARM Cortex-M3 cores.
6185 The driver probes for a number of these chips and autoconfigures itself,
6186 apart from the base address.
6189 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
6193 @deffn {Flash Driver} psoc5lp_nvl
6194 All members of the PSoC 5LP microcontroller family from Cypress
6195 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
6196 The driver probes for a number of these chips and autoconfigures itself.
6199 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
6202 PSoC 5LP chips have multiple NV Latches:
6205 @item Device Configuration NV Latch - 4 bytes
6206 @item Write Once (WO) NV Latch - 4 bytes
6209 @b{Note:} This driver only implements the Device Configuration NVL.
6211 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
6212 @quotation Attention
6213 Switching ECC mode via write to Device Configuration NVL will require a reset
6214 after successful write.
6218 @deffn {Flash Driver} psoc6
6219 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
6220 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6221 the same Flash/RAM/MMIO address space.
6223 Flash in PSoC6 is split into three regions:
6225 @item Main Flash - this is the main storage for user application.
6226 Total size varies among devices, sector size: 256 kBytes, row size:
6227 512 bytes. Supports erase operation on individual rows.
6228 @item Work Flash - intended to be used as storage for user data
6229 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
6230 row size: 512 bytes.
6231 @item Supervisory Flash - special region which contains device-specific
6232 service data. This region does not support erase operation. Only few rows can
6233 be programmed by the user, most of the rows are read only. Programming
6234 operation will erase row automatically.
6237 All three flash regions are supported by the driver. Flash geometry is detected
6238 automatically by parsing data in SPCIF_GEOMETRY register.
6240 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
6243 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm0
6244 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm0
6245 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm0
6246 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm0
6247 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm0
6248 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm0
6250 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm4
6251 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm4
6252 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm4
6253 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm4
6254 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm4
6255 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm4
6258 psoc6-specific commands
6259 @deffn Command {psoc6 reset_halt}
6260 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
6261 When invoked for CM0+ target, it will set break point at application entry point
6262 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
6263 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
6264 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
6267 @deffn Command {psoc6 mass_erase} num
6268 Erases the contents given flash bank. The @var{num} parameter is a value shown
6269 by @command{flash banks}.
6270 Note: only Main and Work flash regions support Erase operation.
6274 @deffn {Flash Driver} sim3x
6275 All members of the SiM3 microcontroller family from Silicon Laboratories
6276 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
6278 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
6279 If this fails, it will use the @var{size} parameter as the size of flash bank.
6282 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
6285 There are 2 commands defined in the @var{sim3x} driver:
6287 @deffn Command {sim3x mass_erase}
6288 Erases the complete flash. This is used to unlock the flash.
6289 And this command is only possible when using the SWD interface.
6292 @deffn Command {sim3x lock}
6293 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
6297 @deffn {Flash Driver} stellaris
6298 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
6299 families from Texas Instruments include internal flash. The driver
6300 automatically recognizes a number of these chips using the chip
6301 identification register, and autoconfigures itself.
6304 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
6307 @deffn Command {stellaris recover}
6308 Performs the @emph{Recovering a "Locked" Device} procedure to restore
6309 the flash and its associated nonvolatile registers to their factory
6310 default values (erased). This is the only way to remove flash
6311 protection or re-enable debugging if that capability has been
6314 Note that the final "power cycle the chip" step in this procedure
6315 must be performed by hand, since OpenOCD can't do it.
6317 if more than one Stellaris chip is connected, the procedure is
6318 applied to all of them.
6323 @deffn {Flash Driver} stm32f1x
6324 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
6325 from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
6326 The driver automatically recognizes a number of these chips using
6327 the chip identification register, and autoconfigures itself.
6330 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
6333 Note that some devices have been found that have a flash size register that contains
6334 an invalid value, to workaround this issue you can override the probed value used by
6338 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
6341 If you have a target with dual flash banks then define the second bank
6342 as per the following example.
6344 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
6347 Some stm32f1x-specific commands are defined:
6349 @deffn Command {stm32f1x lock} num
6350 Locks the entire stm32 device.
6351 The @var{num} parameter is a value shown by @command{flash banks}.
6354 @deffn Command {stm32f1x unlock} num
6355 Unlocks the entire stm32 device.
6356 The @var{num} parameter is a value shown by @command{flash banks}.
6359 @deffn Command {stm32f1x mass_erase} num
6360 Mass erases the entire stm32f1x device.
6361 The @var{num} parameter is a value shown by @command{flash banks}.
6364 @deffn Command {stm32f1x options_read} num
6365 Read and display the stm32 option bytes written by
6366 the @command{stm32f1x options_write} command.
6367 The @var{num} parameter is a value shown by @command{flash banks}.
6370 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
6371 Writes the stm32 option byte with the specified values.
6372 The @var{num} parameter is a value shown by @command{flash banks}.
6376 @deffn {Flash Driver} stm32f2x
6377 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from ST Microelectronics
6378 include internal flash and use ARM Cortex-M3/M4/M7 cores.
6379 The driver automatically recognizes a number of these chips using
6380 the chip identification register, and autoconfigures itself.
6383 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
6386 Note that some devices have been found that have a flash size register that contains
6387 an invalid value, to workaround this issue you can override the probed value used by
6391 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
6394 Some stm32f2x-specific commands are defined:
6396 @deffn Command {stm32f2x lock} num
6397 Locks the entire stm32 device.
6398 The @var{num} parameter is a value shown by @command{flash banks}.
6401 @deffn Command {stm32f2x unlock} num
6402 Unlocks the entire stm32 device.
6403 The @var{num} parameter is a value shown by @command{flash banks}.
6406 @deffn Command {stm32f2x mass_erase} num
6407 Mass erases the entire stm32f2x device.
6408 The @var{num} parameter is a value shown by @command{flash banks}.
6411 @deffn Command {stm32f2x options_read} num
6412 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
6413 The @var{num} parameter is a value shown by @command{flash banks}.
6416 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
6417 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
6418 Warning: The meaning of the various bits depends on the device, always check datasheet!
6419 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
6420 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
6421 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
6424 @deffn Command {stm32f2x optcr2_write} num optcr2
6425 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
6426 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
6430 @deffn {Flash Driver} stm32h7x
6431 All members of the STM32H7 microcontroller families from ST Microelectronics
6432 include internal flash and use ARM Cortex-M7 core.
6433 The driver automatically recognizes a number of these chips using
6434 the chip identification register, and autoconfigures itself.
6437 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
6440 Note that some devices have been found that have a flash size register that contains
6441 an invalid value, to workaround this issue you can override the probed value used by
6445 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
6448 Some stm32h7x-specific commands are defined:
6450 @deffn Command {stm32h7x lock} num
6451 Locks the entire stm32 device.
6452 The @var{num} parameter is a value shown by @command{flash banks}.
6455 @deffn Command {stm32h7x unlock} num
6456 Unlocks the entire stm32 device.
6457 The @var{num} parameter is a value shown by @command{flash banks}.
6460 @deffn Command {stm32h7x mass_erase} num
6461 Mass erases the entire stm32h7x device.
6462 The @var{num} parameter is a value shown by @command{flash banks}.
6466 @deffn {Flash Driver} stm32lx
6467 All members of the STM32L microcontroller families from ST Microelectronics
6468 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
6469 The driver automatically recognizes a number of these chips using
6470 the chip identification register, and autoconfigures itself.
6473 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
6476 Note that some devices have been found that have a flash size register that contains
6477 an invalid value, to workaround this issue you can override the probed value used by
6478 the flash driver. If you use 0 as the bank base address, it tells the
6479 driver to autodetect the bank location assuming you're configuring the
6483 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6486 Some stm32lx-specific commands are defined:
6488 @deffn Command {stm32lx lock} num
6489 Locks the entire stm32 device.
6490 The @var{num} parameter is a value shown by @command{flash banks}.
6493 @deffn Command {stm32lx unlock} num
6494 Unlocks the entire stm32 device.
6495 The @var{num} parameter is a value shown by @command{flash banks}.
6498 @deffn Command {stm32lx mass_erase} num
6499 Mass erases the entire stm32lx device (all flash banks and EEPROM
6500 data). This is the only way to unlock a protected flash (unless RDP
6501 Level is 2 which can't be unlocked at all).
6502 The @var{num} parameter is a value shown by @command{flash banks}.
6506 @deffn {Flash Driver} stm32l4x
6507 All members of the STM32L4 microcontroller families from ST Microelectronics
6508 include internal flash and use ARM Cortex-M4 cores.
6509 The driver automatically recognizes a number of these chips using
6510 the chip identification register, and autoconfigures itself.
6513 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
6516 Note that some devices have been found that have a flash size register that contains
6517 an invalid value, to workaround this issue you can override the probed value used by
6521 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
6524 Some stm32l4x-specific commands are defined:
6526 @deffn Command {stm32l4x lock} num
6527 Locks the entire stm32 device.
6528 The @var{num} parameter is a value shown by @command{flash banks}.
6531 @deffn Command {stm32l4x unlock} num
6532 Unlocks the entire stm32 device.
6533 The @var{num} parameter is a value shown by @command{flash banks}.
6536 @deffn Command {stm32l4x mass_erase} num
6537 Mass erases the entire stm32l4x device.
6538 The @var{num} parameter is a value shown by @command{flash banks}.
6542 @deffn {Flash Driver} str7x
6543 All members of the STR7 microcontroller family from ST Microelectronics
6544 include internal flash and use ARM7TDMI cores.
6545 The @var{str7x} driver defines one mandatory parameter, @var{variant},
6546 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
6549 flash bank $_FLASHNAME str7x \
6550 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
6553 @deffn Command {str7x disable_jtag} bank
6554 Activate the Debug/Readout protection mechanism
6555 for the specified flash bank.
6559 @deffn {Flash Driver} str9x
6560 Most members of the STR9 microcontroller family from ST Microelectronics
6561 include internal flash and use ARM966E cores.
6562 The str9 needs the flash controller to be configured using
6563 the @command{str9x flash_config} command prior to Flash programming.
6566 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
6567 str9x flash_config 0 4 2 0 0x80000
6570 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
6571 Configures the str9 flash controller.
6572 The @var{num} parameter is a value shown by @command{flash banks}.
6575 @item @var{bbsr} - Boot Bank Size register
6576 @item @var{nbbsr} - Non Boot Bank Size register
6577 @item @var{bbadr} - Boot Bank Start Address register
6578 @item @var{nbbadr} - Boot Bank Start Address register
6584 @deffn {Flash Driver} str9xpec
6587 Only use this driver for locking/unlocking the device or configuring the option bytes.
6588 Use the standard str9 driver for programming.
6589 Before using the flash commands the turbo mode must be enabled using the
6590 @command{str9xpec enable_turbo} command.
6592 Here is some background info to help
6593 you better understand how this driver works. OpenOCD has two flash drivers for
6597 Standard driver @option{str9x} programmed via the str9 core. Normally used for
6598 flash programming as it is faster than the @option{str9xpec} driver.
6600 Direct programming @option{str9xpec} using the flash controller. This is an
6601 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
6602 core does not need to be running to program using this flash driver. Typical use
6603 for this driver is locking/unlocking the target and programming the option bytes.
6606 Before we run any commands using the @option{str9xpec} driver we must first disable
6607 the str9 core. This example assumes the @option{str9xpec} driver has been
6608 configured for flash bank 0.
6610 # assert srst, we do not want core running
6611 # while accessing str9xpec flash driver
6613 # turn off target polling
6616 str9xpec enable_turbo 0
6618 str9xpec options_read 0
6619 # re-enable str9 core
6620 str9xpec disable_turbo 0
6624 The above example will read the str9 option bytes.
6625 When performing a unlock remember that you will not be able to halt the str9 - it
6626 has been locked. Halting the core is not required for the @option{str9xpec} driver
6627 as mentioned above, just issue the commands above manually or from a telnet prompt.
6629 Several str9xpec-specific commands are defined:
6631 @deffn Command {str9xpec disable_turbo} num
6632 Restore the str9 into JTAG chain.
6635 @deffn Command {str9xpec enable_turbo} num
6636 Enable turbo mode, will simply remove the str9 from the chain and talk
6637 directly to the embedded flash controller.
6640 @deffn Command {str9xpec lock} num
6641 Lock str9 device. The str9 will only respond to an unlock command that will
6645 @deffn Command {str9xpec part_id} num
6646 Prints the part identifier for bank @var{num}.
6649 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
6650 Configure str9 boot bank.
6653 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
6654 Configure str9 lvd source.
6657 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
6658 Configure str9 lvd threshold.
6661 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
6662 Configure str9 lvd reset warning source.
6665 @deffn Command {str9xpec options_read} num
6666 Read str9 option bytes.
6669 @deffn Command {str9xpec options_write} num
6670 Write str9 option bytes.
6673 @deffn Command {str9xpec unlock} num
6679 @deffn {Flash Driver} tms470
6680 Most members of the TMS470 microcontroller family from Texas Instruments
6681 include internal flash and use ARM7TDMI cores.
6682 This driver doesn't require the chip and bus width to be specified.
6684 Some tms470-specific commands are defined:
6686 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
6687 Saves programming keys in a register, to enable flash erase and write commands.
6690 @deffn Command {tms470 osc_mhz} clock_mhz
6691 Reports the clock speed, which is used to calculate timings.
6694 @deffn Command {tms470 plldis} (0|1)
6695 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
6700 @deffn {Flash Driver} xmc1xxx
6701 All members of the XMC1xxx microcontroller family from Infineon.
6702 This driver does not require the chip and bus width to be specified.
6705 @deffn {Flash Driver} xmc4xxx
6706 All members of the XMC4xxx microcontroller family from Infineon.
6707 This driver does not require the chip and bus width to be specified.
6709 Some xmc4xxx-specific commands are defined:
6711 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
6712 Saves flash protection passwords which are used to lock the user flash
6715 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
6716 Removes Flash write protection from the selected user bank
6721 @section NAND Flash Commands
6724 Compared to NOR or SPI flash, NAND devices are inexpensive
6725 and high density. Today's NAND chips, and multi-chip modules,
6726 commonly hold multiple GigaBytes of data.
6728 NAND chips consist of a number of ``erase blocks'' of a given
6729 size (such as 128 KBytes), each of which is divided into a
6730 number of pages (of perhaps 512 or 2048 bytes each). Each
6731 page of a NAND flash has an ``out of band'' (OOB) area to hold
6732 Error Correcting Code (ECC) and other metadata, usually 16 bytes
6733 of OOB for every 512 bytes of page data.
6735 One key characteristic of NAND flash is that its error rate
6736 is higher than that of NOR flash. In normal operation, that
6737 ECC is used to correct and detect errors. However, NAND
6738 blocks can also wear out and become unusable; those blocks
6739 are then marked "bad". NAND chips are even shipped from the
6740 manufacturer with a few bad blocks. The highest density chips
6741 use a technology (MLC) that wears out more quickly, so ECC
6742 support is increasingly important as a way to detect blocks
6743 that have begun to fail, and help to preserve data integrity
6744 with techniques such as wear leveling.
6746 Software is used to manage the ECC. Some controllers don't
6747 support ECC directly; in those cases, software ECC is used.
6748 Other controllers speed up the ECC calculations with hardware.
6749 Single-bit error correction hardware is routine. Controllers
6750 geared for newer MLC chips may correct 4 or more errors for
6751 every 512 bytes of data.
6753 You will need to make sure that any data you write using
6754 OpenOCD includes the appropriate kind of ECC. For example,
6755 that may mean passing the @code{oob_softecc} flag when
6756 writing NAND data, or ensuring that the correct hardware
6759 The basic steps for using NAND devices include:
6761 @item Declare via the command @command{nand device}
6762 @* Do this in a board-specific configuration file,
6763 passing parameters as needed by the controller.
6764 @item Configure each device using @command{nand probe}.
6765 @* Do this only after the associated target is set up,
6766 such as in its reset-init script or in procures defined
6767 to access that device.
6768 @item Operate on the flash via @command{nand subcommand}
6769 @* Often commands to manipulate the flash are typed by a human, or run
6770 via a script in some automated way. Common task include writing a
6771 boot loader, operating system, or other data needed to initialize or
6775 @b{NOTE:} At the time this text was written, the largest NAND
6776 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
6777 This is because the variables used to hold offsets and lengths
6778 are only 32 bits wide.
6779 (Larger chips may work in some cases, unless an offset or length
6780 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
6781 Some larger devices will work, since they are actually multi-chip
6782 modules with two smaller chips and individual chipselect lines.
6784 @anchor{nandconfiguration}
6785 @subsection NAND Configuration Commands
6786 @cindex NAND configuration
6788 NAND chips must be declared in configuration scripts,
6789 plus some additional configuration that's done after
6790 OpenOCD has initialized.
6792 @deffn {Config Command} {nand device} name driver target [configparams...]
6793 Declares a NAND device, which can be read and written to
6794 after it has been configured through @command{nand probe}.
6795 In OpenOCD, devices are single chips; this is unlike some
6796 operating systems, which may manage multiple chips as if
6797 they were a single (larger) device.
6798 In some cases, configuring a device will activate extra
6799 commands; see the controller-specific documentation.
6801 @b{NOTE:} This command is not available after OpenOCD
6802 initialization has completed. Use it in board specific
6803 configuration files, not interactively.
6806 @item @var{name} ... may be used to reference the NAND bank
6807 in most other NAND commands. A number is also available.
6808 @item @var{driver} ... identifies the NAND controller driver
6809 associated with the NAND device being declared.
6810 @xref{nanddriverlist,,NAND Driver List}.
6811 @item @var{target} ... names the target used when issuing
6812 commands to the NAND controller.
6813 @comment Actually, it's currently a controller-specific parameter...
6814 @item @var{configparams} ... controllers may support, or require,
6815 additional parameters. See the controller-specific documentation
6816 for more information.
6820 @deffn Command {nand list}
6821 Prints a summary of each device declared
6822 using @command{nand device}, numbered from zero.
6823 Note that un-probed devices show no details.
6826 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6827 blocksize: 131072, blocks: 8192
6828 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6829 blocksize: 131072, blocks: 8192
6834 @deffn Command {nand probe} num
6835 Probes the specified device to determine key characteristics
6836 like its page and block sizes, and how many blocks it has.
6837 The @var{num} parameter is the value shown by @command{nand list}.
6838 You must (successfully) probe a device before you can use
6839 it with most other NAND commands.
6842 @subsection Erasing, Reading, Writing to NAND Flash
6844 @deffn Command {nand dump} num filename offset length [oob_option]
6845 @cindex NAND reading
6846 Reads binary data from the NAND device and writes it to the file,
6847 starting at the specified offset.
6848 The @var{num} parameter is the value shown by @command{nand list}.
6850 Use a complete path name for @var{filename}, so you don't depend
6851 on the directory used to start the OpenOCD server.
6853 The @var{offset} and @var{length} must be exact multiples of the
6854 device's page size. They describe a data region; the OOB data
6855 associated with each such page may also be accessed.
6857 @b{NOTE:} At the time this text was written, no error correction
6858 was done on the data that's read, unless raw access was disabled
6859 and the underlying NAND controller driver had a @code{read_page}
6860 method which handled that error correction.
6862 By default, only page data is saved to the specified file.
6863 Use an @var{oob_option} parameter to save OOB data:
6865 @item no oob_* parameter
6866 @*Output file holds only page data; OOB is discarded.
6867 @item @code{oob_raw}
6868 @*Output file interleaves page data and OOB data;
6869 the file will be longer than "length" by the size of the
6870 spare areas associated with each data page.
6871 Note that this kind of "raw" access is different from
6872 what's implied by @command{nand raw_access}, which just
6873 controls whether a hardware-aware access method is used.
6874 @item @code{oob_only}
6875 @*Output file has only raw OOB data, and will
6876 be smaller than "length" since it will contain only the
6877 spare areas associated with each data page.
6881 @deffn Command {nand erase} num [offset length]
6882 @cindex NAND erasing
6883 @cindex NAND programming
6884 Erases blocks on the specified NAND device, starting at the
6885 specified @var{offset} and continuing for @var{length} bytes.
6886 Both of those values must be exact multiples of the device's
6887 block size, and the region they specify must fit entirely in the chip.
6888 If those parameters are not specified,
6889 the whole NAND chip will be erased.
6890 The @var{num} parameter is the value shown by @command{nand list}.
6892 @b{NOTE:} This command will try to erase bad blocks, when told
6893 to do so, which will probably invalidate the manufacturer's bad
6895 For the remainder of the current server session, @command{nand info}
6896 will still report that the block ``is'' bad.
6899 @deffn Command {nand write} num filename offset [option...]
6900 @cindex NAND writing
6901 @cindex NAND programming
6902 Writes binary data from the file into the specified NAND device,
6903 starting at the specified offset. Those pages should already
6904 have been erased; you can't change zero bits to one bits.
6905 The @var{num} parameter is the value shown by @command{nand list}.
6907 Use a complete path name for @var{filename}, so you don't depend
6908 on the directory used to start the OpenOCD server.
6910 The @var{offset} must be an exact multiple of the device's page size.
6911 All data in the file will be written, assuming it doesn't run
6912 past the end of the device.
6913 Only full pages are written, and any extra space in the last
6914 page will be filled with 0xff bytes. (That includes OOB data,
6915 if that's being written.)
6917 @b{NOTE:} At the time this text was written, bad blocks are
6918 ignored. That is, this routine will not skip bad blocks,
6919 but will instead try to write them. This can cause problems.
6921 Provide at most one @var{option} parameter. With some
6922 NAND drivers, the meanings of these parameters may change
6923 if @command{nand raw_access} was used to disable hardware ECC.
6925 @item no oob_* parameter
6926 @*File has only page data, which is written.
6927 If raw access is in use, the OOB area will not be written.
6928 Otherwise, if the underlying NAND controller driver has
6929 a @code{write_page} routine, that routine may write the OOB
6930 with hardware-computed ECC data.
6931 @item @code{oob_only}
6932 @*File has only raw OOB data, which is written to the OOB area.
6933 Each page's data area stays untouched. @i{This can be a dangerous
6934 option}, since it can invalidate the ECC data.
6935 You may need to force raw access to use this mode.
6936 @item @code{oob_raw}
6937 @*File interleaves data and OOB data, both of which are written
6938 If raw access is enabled, the data is written first, then the
6940 Otherwise, if the underlying NAND controller driver has
6941 a @code{write_page} routine, that routine may modify the OOB
6942 before it's written, to include hardware-computed ECC data.
6943 @item @code{oob_softecc}
6944 @*File has only page data, which is written.
6945 The OOB area is filled with 0xff, except for a standard 1-bit
6946 software ECC code stored in conventional locations.
6947 You might need to force raw access to use this mode, to prevent
6948 the underlying driver from applying hardware ECC.
6949 @item @code{oob_softecc_kw}
6950 @*File has only page data, which is written.
6951 The OOB area is filled with 0xff, except for a 4-bit software ECC
6952 specific to the boot ROM in Marvell Kirkwood SoCs.
6953 You might need to force raw access to use this mode, to prevent
6954 the underlying driver from applying hardware ECC.
6958 @deffn Command {nand verify} num filename offset [option...]
6959 @cindex NAND verification
6960 @cindex NAND programming
6961 Verify the binary data in the file has been programmed to the
6962 specified NAND device, starting at the specified offset.
6963 The @var{num} parameter is the value shown by @command{nand list}.
6965 Use a complete path name for @var{filename}, so you don't depend
6966 on the directory used to start the OpenOCD server.
6968 The @var{offset} must be an exact multiple of the device's page size.
6969 All data in the file will be read and compared to the contents of the
6970 flash, assuming it doesn't run past the end of the device.
6971 As with @command{nand write}, only full pages are verified, so any extra
6972 space in the last page will be filled with 0xff bytes.
6974 The same @var{options} accepted by @command{nand write},
6975 and the file will be processed similarly to produce the buffers that
6976 can be compared against the contents produced from @command{nand dump}.
6978 @b{NOTE:} This will not work when the underlying NAND controller
6979 driver's @code{write_page} routine must update the OOB with a
6980 hardware-computed ECC before the data is written. This limitation may
6981 be removed in a future release.
6984 @subsection Other NAND commands
6985 @cindex NAND other commands
6987 @deffn Command {nand check_bad_blocks} num [offset length]
6988 Checks for manufacturer bad block markers on the specified NAND
6989 device. If no parameters are provided, checks the whole
6990 device; otherwise, starts at the specified @var{offset} and
6991 continues for @var{length} bytes.
6992 Both of those values must be exact multiples of the device's
6993 block size, and the region they specify must fit entirely in the chip.
6994 The @var{num} parameter is the value shown by @command{nand list}.
6996 @b{NOTE:} Before using this command you should force raw access
6997 with @command{nand raw_access enable} to ensure that the underlying
6998 driver will not try to apply hardware ECC.
7001 @deffn Command {nand info} num
7002 The @var{num} parameter is the value shown by @command{nand list}.
7003 This prints the one-line summary from "nand list", plus for
7004 devices which have been probed this also prints any known
7005 status for each block.
7008 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
7009 Sets or clears an flag affecting how page I/O is done.
7010 The @var{num} parameter is the value shown by @command{nand list}.
7012 This flag is cleared (disabled) by default, but changing that
7013 value won't affect all NAND devices. The key factor is whether
7014 the underlying driver provides @code{read_page} or @code{write_page}
7015 methods. If it doesn't provide those methods, the setting of
7016 this flag is irrelevant; all access is effectively ``raw''.
7018 When those methods exist, they are normally used when reading
7019 data (@command{nand dump} or reading bad block markers) or
7020 writing it (@command{nand write}). However, enabling
7021 raw access (setting the flag) prevents use of those methods,
7022 bypassing hardware ECC logic.
7023 @i{This can be a dangerous option}, since writing blocks
7024 with the wrong ECC data can cause them to be marked as bad.
7027 @anchor{nanddriverlist}
7028 @subsection NAND Driver List
7029 As noted above, the @command{nand device} command allows
7030 driver-specific options and behaviors.
7031 Some controllers also activate controller-specific commands.
7033 @deffn {NAND Driver} at91sam9
7034 This driver handles the NAND controllers found on AT91SAM9 family chips from
7035 Atmel. It takes two extra parameters: address of the NAND chip;
7036 address of the ECC controller.
7038 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
7040 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
7041 @code{read_page} methods are used to utilize the ECC hardware unless they are
7042 disabled by using the @command{nand raw_access} command. There are four
7043 additional commands that are needed to fully configure the AT91SAM9 NAND
7044 controller. Two are optional; most boards use the same wiring for ALE/CLE:
7045 @deffn Command {at91sam9 cle} num addr_line
7046 Configure the address line used for latching commands. The @var{num}
7047 parameter is the value shown by @command{nand list}.
7049 @deffn Command {at91sam9 ale} num addr_line
7050 Configure the address line used for latching addresses. The @var{num}
7051 parameter is the value shown by @command{nand list}.
7054 For the next two commands, it is assumed that the pins have already been
7055 properly configured for input or output.
7056 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
7057 Configure the RDY/nBUSY input from the NAND device. The @var{num}
7058 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7059 is the base address of the PIO controller and @var{pin} is the pin number.
7061 @deffn Command {at91sam9 ce} num pio_base_addr pin
7062 Configure the chip enable input to the NAND device. The @var{num}
7063 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7064 is the base address of the PIO controller and @var{pin} is the pin number.
7068 @deffn {NAND Driver} davinci
7069 This driver handles the NAND controllers found on DaVinci family
7070 chips from Texas Instruments.
7071 It takes three extra parameters:
7072 address of the NAND chip;
7073 hardware ECC mode to use (@option{hwecc1},
7074 @option{hwecc4}, @option{hwecc4_infix});
7075 address of the AEMIF controller on this processor.
7077 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
7079 All DaVinci processors support the single-bit ECC hardware,
7080 and newer ones also support the four-bit ECC hardware.
7081 The @code{write_page} and @code{read_page} methods are used
7082 to implement those ECC modes, unless they are disabled using
7083 the @command{nand raw_access} command.
7086 @deffn {NAND Driver} lpc3180
7087 These controllers require an extra @command{nand device}
7088 parameter: the clock rate used by the controller.
7089 @deffn Command {lpc3180 select} num [mlc|slc]
7090 Configures use of the MLC or SLC controller mode.
7091 MLC implies use of hardware ECC.
7092 The @var{num} parameter is the value shown by @command{nand list}.
7095 At this writing, this driver includes @code{write_page}
7096 and @code{read_page} methods. Using @command{nand raw_access}
7097 to disable those methods will prevent use of hardware ECC
7098 in the MLC controller mode, but won't change SLC behavior.
7100 @comment current lpc3180 code won't issue 5-byte address cycles
7102 @deffn {NAND Driver} mx3
7103 This driver handles the NAND controller in i.MX31. The mxc driver
7104 should work for this chip as well.
7107 @deffn {NAND Driver} mxc
7108 This driver handles the NAND controller found in Freescale i.MX
7109 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
7110 The driver takes 3 extra arguments, chip (@option{mx27},
7111 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
7112 and optionally if bad block information should be swapped between
7113 main area and spare area (@option{biswap}), defaults to off.
7115 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
7117 @deffn Command {mxc biswap} bank_num [enable|disable]
7118 Turns on/off bad block information swapping from main area,
7119 without parameter query status.
7123 @deffn {NAND Driver} orion
7124 These controllers require an extra @command{nand device}
7125 parameter: the address of the controller.
7127 nand device orion 0xd8000000
7129 These controllers don't define any specialized commands.
7130 At this writing, their drivers don't include @code{write_page}
7131 or @code{read_page} methods, so @command{nand raw_access} won't
7132 change any behavior.
7135 @deffn {NAND Driver} s3c2410
7136 @deffnx {NAND Driver} s3c2412
7137 @deffnx {NAND Driver} s3c2440
7138 @deffnx {NAND Driver} s3c2443
7139 @deffnx {NAND Driver} s3c6400
7140 These S3C family controllers don't have any special
7141 @command{nand device} options, and don't define any
7142 specialized commands.
7143 At this writing, their drivers don't include @code{write_page}
7144 or @code{read_page} methods, so @command{nand raw_access} won't
7145 change any behavior.
7150 @subsection mFlash Configuration
7151 @cindex mFlash Configuration
7153 @deffn {Config Command} {mflash bank} soc base RST_pin target
7154 Configures a mflash for @var{soc} host bank at
7156 The pin number format depends on the host GPIO naming convention.
7157 Currently, the mflash driver supports s3c2440 and pxa270.
7159 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
7162 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
7165 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
7168 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
7172 @subsection mFlash commands
7173 @cindex mFlash commands
7175 @deffn Command {mflash config pll} frequency
7176 Configure mflash PLL.
7177 The @var{frequency} is the mflash input frequency, in Hz.
7178 Issuing this command will erase mflash's whole internal nand and write new pll.
7179 After this command, mflash needs power-on-reset for normal operation.
7180 If pll was newly configured, storage and boot(optional) info also need to be update.
7183 @deffn Command {mflash config boot}
7184 Configure bootable option.
7185 If bootable option is set, mflash offer the first 8 sectors
7189 @deffn Command {mflash config storage}
7190 Configure storage information.
7191 For the normal storage operation, this information must be
7195 @deffn Command {mflash dump} num filename offset size
7196 Dump @var{size} bytes, starting at @var{offset} bytes from the
7197 beginning of the bank @var{num}, to the file named @var{filename}.
7200 @deffn Command {mflash probe}
7204 @deffn Command {mflash write} num filename offset
7205 Write the binary file @var{filename} to mflash bank @var{num}, starting at
7206 @var{offset} bytes from the beginning of the bank.
7209 @node Flash Programming
7210 @chapter Flash Programming
7212 OpenOCD implements numerous ways to program the target flash, whether internal or external.
7213 Programming can be achieved by either using GDB @ref{programmingusinggdb,,Programming using GDB},
7214 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
7216 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
7217 OpenOCD will program/verify/reset the target and optionally shutdown.
7219 The script is executed as follows and by default the following actions will be performed.
7221 @item 'init' is executed.
7222 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
7223 @item @code{flash write_image} is called to erase and write any flash using the filename given.
7224 @item @code{verify_image} is called if @option{verify} parameter is given.
7225 @item @code{reset run} is called if @option{reset} parameter is given.
7226 @item OpenOCD is shutdown if @option{exit} parameter is given.
7229 An example of usage is given below. @xref{program}.
7232 # program and verify using elf/hex/s19. verify and reset
7233 # are optional parameters
7234 openocd -f board/stm32f3discovery.cfg \
7235 -c "program filename.elf verify reset exit"
7237 # binary files need the flash address passing
7238 openocd -f board/stm32f3discovery.cfg \
7239 -c "program filename.bin exit 0x08000000"
7242 @node PLD/FPGA Commands
7243 @chapter PLD/FPGA Commands
7247 Programmable Logic Devices (PLDs) and the more flexible
7248 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
7249 OpenOCD can support programming them.
7250 Although PLDs are generally restrictive (cells are less functional, and
7251 there are no special purpose cells for memory or computational tasks),
7252 they share the same OpenOCD infrastructure.
7253 Accordingly, both are called PLDs here.
7255 @section PLD/FPGA Configuration and Commands
7257 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
7258 OpenOCD maintains a list of PLDs available for use in various commands.
7259 Also, each such PLD requires a driver.
7261 They are referenced by the number shown by the @command{pld devices} command,
7262 and new PLDs are defined by @command{pld device driver_name}.
7264 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
7265 Defines a new PLD device, supported by driver @var{driver_name},
7266 using the TAP named @var{tap_name}.
7267 The driver may make use of any @var{driver_options} to configure its
7271 @deffn {Command} {pld devices}
7272 Lists the PLDs and their numbers.
7275 @deffn {Command} {pld load} num filename
7276 Loads the file @file{filename} into the PLD identified by @var{num}.
7277 The file format must be inferred by the driver.
7280 @section PLD/FPGA Drivers, Options, and Commands
7282 Drivers may support PLD-specific options to the @command{pld device}
7283 definition command, and may also define commands usable only with
7284 that particular type of PLD.
7286 @deffn {FPGA Driver} virtex2 [no_jstart]
7287 Virtex-II is a family of FPGAs sold by Xilinx.
7288 It supports the IEEE 1532 standard for In-System Configuration (ISC).
7290 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
7291 loading the bitstream. While required for Series2, Series3, and Series6, it
7292 breaks bitstream loading on Series7.
7294 @deffn {Command} {virtex2 read_stat} num
7295 Reads and displays the Virtex-II status register (STAT)
7300 @node General Commands
7301 @chapter General Commands
7304 The commands documented in this chapter here are common commands that
7305 you, as a human, may want to type and see the output of. Configuration type
7306 commands are documented elsewhere.
7310 @item @b{Source Of Commands}
7311 @* OpenOCD commands can occur in a configuration script (discussed
7312 elsewhere) or typed manually by a human or supplied programmatically,
7313 or via one of several TCP/IP Ports.
7315 @item @b{From the human}
7316 @* A human should interact with the telnet interface (default port: 4444)
7317 or via GDB (default port 3333).
7319 To issue commands from within a GDB session, use the @option{monitor}
7320 command, e.g. use @option{monitor poll} to issue the @option{poll}
7321 command. All output is relayed through the GDB session.
7323 @item @b{Machine Interface}
7324 The Tcl interface's intent is to be a machine interface. The default Tcl
7329 @section Server Commands
7331 @deffn {Command} exit
7332 Exits the current telnet session.
7335 @deffn {Command} help [string]
7336 With no parameters, prints help text for all commands.
7337 Otherwise, prints each helptext containing @var{string}.
7338 Not every command provides helptext.
7340 Configuration commands, and commands valid at any time, are
7341 explicitly noted in parenthesis.
7342 In most cases, no such restriction is listed; this indicates commands
7343 which are only available after the configuration stage has completed.
7346 @deffn Command sleep msec [@option{busy}]
7347 Wait for at least @var{msec} milliseconds before resuming.
7348 If @option{busy} is passed, busy-wait instead of sleeping.
7349 (This option is strongly discouraged.)
7350 Useful in connection with script files
7351 (@command{script} command and @command{target_name} configuration).
7354 @deffn Command shutdown [@option{error}]
7355 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
7356 other). If option @option{error} is used, OpenOCD will return a
7357 non-zero exit code to the parent process.
7361 @deffn Command debug_level [n]
7362 @cindex message level
7363 Display debug level.
7364 If @var{n} (from 0..4) is provided, then set it to that level.
7365 This affects the kind of messages sent to the server log.
7366 Level 0 is error messages only;
7367 level 1 adds warnings;
7368 level 2 adds informational messages;
7369 level 3 adds debugging messages;
7370 and level 4 adds verbose low-level debug messages.
7371 The default is level 2, but that can be overridden on
7372 the command line along with the location of that log
7373 file (which is normally the server's standard output).
7377 @deffn Command echo [-n] message
7378 Logs a message at "user" priority.
7379 Output @var{message} to stdout.
7380 Option "-n" suppresses trailing newline.
7382 echo "Downloading kernel -- please wait"
7386 @deffn Command log_output [filename]
7387 Redirect logging to @var{filename};
7388 the initial log output channel is stderr.
7391 @deffn Command add_script_search_dir [directory]
7392 Add @var{directory} to the file/script search path.
7395 @deffn Command bindto [@var{name}]
7396 Specify hostname or IPv4 address on which to listen for incoming
7397 TCP/IP connections. By default, OpenOCD will listen on the loopback
7398 interface only. If your network environment is safe, @code{bindto
7399 0.0.0.0} can be used to cover all available interfaces.
7402 @anchor{targetstatehandling}
7403 @section Target State handling
7406 @cindex target initialization
7408 In this section ``target'' refers to a CPU configured as
7409 shown earlier (@pxref{CPU Configuration}).
7410 These commands, like many, implicitly refer to
7411 a current target which is used to perform the
7412 various operations. The current target may be changed
7413 by using @command{targets} command with the name of the
7414 target which should become current.
7416 @deffn Command reg [(number|name) [(value|'force')]]
7417 Access a single register by @var{number} or by its @var{name}.
7418 The target must generally be halted before access to CPU core
7419 registers is allowed. Depending on the hardware, some other
7420 registers may be accessible while the target is running.
7422 @emph{With no arguments}:
7423 list all available registers for the current target,
7424 showing number, name, size, value, and cache status.
7425 For valid entries, a value is shown; valid entries
7426 which are also dirty (and will be written back later)
7427 are flagged as such.
7429 @emph{With number/name}: display that register's value.
7430 Use @var{force} argument to read directly from the target,
7431 bypassing any internal cache.
7433 @emph{With both number/name and value}: set register's value.
7434 Writes may be held in a writeback cache internal to OpenOCD,
7435 so that setting the value marks the register as dirty instead
7436 of immediately flushing that value. Resuming CPU execution
7437 (including by single stepping) or otherwise activating the
7438 relevant module will flush such values.
7440 Cores may have surprisingly many registers in their
7441 Debug and trace infrastructure:
7446 (0) r0 (/32): 0x0000D3C2 (dirty)
7447 (1) r1 (/32): 0xFD61F31C
7450 (164) ETM_contextid_comparator_mask (/32)
7455 @deffn Command halt [ms]
7456 @deffnx Command wait_halt [ms]
7457 The @command{halt} command first sends a halt request to the target,
7458 which @command{wait_halt} doesn't.
7459 Otherwise these behave the same: wait up to @var{ms} milliseconds,
7460 or 5 seconds if there is no parameter, for the target to halt
7461 (and enter debug mode).
7462 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
7465 On ARM cores, software using the @emph{wait for interrupt} operation
7466 often blocks the JTAG access needed by a @command{halt} command.
7467 This is because that operation also puts the core into a low
7468 power mode by gating the core clock;
7469 but the core clock is needed to detect JTAG clock transitions.
7471 One partial workaround uses adaptive clocking: when the core is
7472 interrupted the operation completes, then JTAG clocks are accepted
7473 at least until the interrupt handler completes.
7474 However, this workaround is often unusable since the processor, board,
7475 and JTAG adapter must all support adaptive JTAG clocking.
7476 Also, it can't work until an interrupt is issued.
7478 A more complete workaround is to not use that operation while you
7479 work with a JTAG debugger.
7480 Tasking environments generally have idle loops where the body is the
7481 @emph{wait for interrupt} operation.
7482 (On older cores, it is a coprocessor action;
7483 newer cores have a @option{wfi} instruction.)
7484 Such loops can just remove that operation, at the cost of higher
7485 power consumption (because the CPU is needlessly clocked).
7490 @deffn Command resume [address]
7491 Resume the target at its current code position,
7492 or the optional @var{address} if it is provided.
7493 OpenOCD will wait 5 seconds for the target to resume.
7496 @deffn Command step [address]
7497 Single-step the target at its current code position,
7498 or the optional @var{address} if it is provided.
7501 @anchor{resetcommand}
7502 @deffn Command reset
7503 @deffnx Command {reset run}
7504 @deffnx Command {reset halt}
7505 @deffnx Command {reset init}
7506 Perform as hard a reset as possible, using SRST if possible.
7507 @emph{All defined targets will be reset, and target
7508 events will fire during the reset sequence.}
7510 The optional parameter specifies what should
7511 happen after the reset.
7512 If there is no parameter, a @command{reset run} is executed.
7513 The other options will not work on all systems.
7514 @xref{Reset Configuration}.
7517 @item @b{run} Let the target run
7518 @item @b{halt} Immediately halt the target
7519 @item @b{init} Immediately halt the target, and execute the reset-init script
7523 @deffn Command soft_reset_halt
7524 Requesting target halt and executing a soft reset. This is often used
7525 when a target cannot be reset and halted. The target, after reset is
7526 released begins to execute code. OpenOCD attempts to stop the CPU and
7527 then sets the program counter back to the reset vector. Unfortunately
7528 the code that was executed may have left the hardware in an unknown
7532 @section I/O Utilities
7534 These commands are available when
7535 OpenOCD is built with @option{--enable-ioutil}.
7536 They are mainly useful on embedded targets,
7538 Hosts with operating systems have complementary tools.
7540 @emph{Note:} there are several more such commands.
7542 @deffn Command append_file filename [string]*
7543 Appends the @var{string} parameters to
7544 the text file @file{filename}.
7545 Each string except the last one is followed by one space.
7546 The last string is followed by a newline.
7549 @deffn Command cat filename
7550 Reads and displays the text file @file{filename}.
7553 @deffn Command cp src_filename dest_filename
7554 Copies contents from the file @file{src_filename}
7555 into @file{dest_filename}.
7559 @emph{No description provided.}
7563 @emph{No description provided.}
7567 @emph{No description provided.}
7570 @deffn Command meminfo
7571 Display available RAM memory on OpenOCD host.
7572 Used in OpenOCD regression testing scripts.
7576 @emph{No description provided.}
7580 @emph{No description provided.}
7583 @deffn Command rm filename
7584 @c "rm" has both normal and Jim-level versions??
7585 Unlinks the file @file{filename}.
7588 @deffn Command trunc filename
7589 Removes all data in the file @file{filename}.
7592 @anchor{memoryaccess}
7593 @section Memory access commands
7594 @cindex memory access
7596 These commands allow accesses of a specific size to the memory
7597 system. Often these are used to configure the current target in some
7598 special way. For example - one may need to write certain values to the
7599 SDRAM controller to enable SDRAM.
7602 @item Use the @command{targets} (plural) command
7603 to change the current target.
7604 @item In system level scripts these commands are deprecated.
7605 Please use their TARGET object siblings to avoid making assumptions
7606 about what TAP is the current target, or about MMU configuration.
7609 @deffn Command mdw [phys] addr [count]
7610 @deffnx Command mdh [phys] addr [count]
7611 @deffnx Command mdb [phys] addr [count]
7612 Display contents of address @var{addr}, as
7613 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
7614 or 8-bit bytes (@command{mdb}).
7615 When the current target has an MMU which is present and active,
7616 @var{addr} is interpreted as a virtual address.
7617 Otherwise, or if the optional @var{phys} flag is specified,
7618 @var{addr} is interpreted as a physical address.
7619 If @var{count} is specified, displays that many units.
7620 (If you want to manipulate the data instead of displaying it,
7621 see the @code{mem2array} primitives.)
7624 @deffn Command mww [phys] addr word
7625 @deffnx Command mwh [phys] addr halfword
7626 @deffnx Command mwb [phys] addr byte
7627 Writes the specified @var{word} (32 bits),
7628 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
7629 at the specified address @var{addr}.
7630 When the current target has an MMU which is present and active,
7631 @var{addr} is interpreted as a virtual address.
7632 Otherwise, or if the optional @var{phys} flag is specified,
7633 @var{addr} is interpreted as a physical address.
7636 @anchor{imageaccess}
7637 @section Image loading commands
7638 @cindex image loading
7639 @cindex image dumping
7641 @deffn Command {dump_image} filename address size
7642 Dump @var{size} bytes of target memory starting at @var{address} to the
7643 binary file named @var{filename}.
7646 @deffn Command {fast_load}
7647 Loads an image stored in memory by @command{fast_load_image} to the
7648 current target. Must be preceded by fast_load_image.
7651 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
7652 Normally you should be using @command{load_image} or GDB load. However, for
7653 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
7654 host), storing the image in memory and uploading the image to the target
7655 can be a way to upload e.g. multiple debug sessions when the binary does not change.
7656 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
7657 memory, i.e. does not affect target. This approach is also useful when profiling
7658 target programming performance as I/O and target programming can easily be profiled
7662 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
7663 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
7664 The file format may optionally be specified
7665 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
7666 In addition the following arguments may be specified:
7667 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
7668 @var{max_length} - maximum number of bytes to load.
7670 proc load_image_bin @{fname foffset address length @} @{
7671 # Load data from fname filename at foffset offset to
7672 # target at address. Load at most length bytes.
7673 load_image $fname [expr $address - $foffset] bin \
7679 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
7680 Displays image section sizes and addresses
7681 as if @var{filename} were loaded into target memory
7682 starting at @var{address} (defaults to zero).
7683 The file format may optionally be specified
7684 (@option{bin}, @option{ihex}, or @option{elf})
7687 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
7688 Verify @var{filename} against target memory starting at @var{address}.
7689 The file format may optionally be specified
7690 (@option{bin}, @option{ihex}, or @option{elf})
7691 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
7694 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
7695 Verify @var{filename} against target memory starting at @var{address}.
7696 The file format may optionally be specified
7697 (@option{bin}, @option{ihex}, or @option{elf})
7698 This perform a comparison using a CRC checksum only
7702 @section Breakpoint and Watchpoint commands
7706 CPUs often make debug modules accessible through JTAG, with
7707 hardware support for a handful of code breakpoints and data
7709 In addition, CPUs almost always support software breakpoints.
7711 @deffn Command {bp} [address len [@option{hw}]]
7712 With no parameters, lists all active breakpoints.
7713 Else sets a breakpoint on code execution starting
7714 at @var{address} for @var{length} bytes.
7715 This is a software breakpoint, unless @option{hw} is specified
7716 in which case it will be a hardware breakpoint.
7718 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
7719 for similar mechanisms that do not consume hardware breakpoints.)
7722 @deffn Command {rbp} address
7723 Remove the breakpoint at @var{address}.
7726 @deffn Command {rwp} address
7727 Remove data watchpoint on @var{address}
7730 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
7731 With no parameters, lists all active watchpoints.
7732 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
7733 The watch point is an "access" watchpoint unless
7734 the @option{r} or @option{w} parameter is provided,
7735 defining it as respectively a read or write watchpoint.
7736 If a @var{value} is provided, that value is used when determining if
7737 the watchpoint should trigger. The value may be first be masked
7738 using @var{mask} to mark ``don't care'' fields.
7741 @section Misc Commands
7744 @deffn Command {profile} seconds filename [start end]
7745 Profiling samples the CPU's program counter as quickly as possible,
7746 which is useful for non-intrusive stochastic profiling.
7747 Saves up to 10000 samples in @file{filename} using ``gmon.out''
7748 format. Optional @option{start} and @option{end} parameters allow to
7749 limit the address range.
7752 @deffn Command {version}
7753 Displays a string identifying the version of this OpenOCD server.
7756 @deffn Command {virt2phys} virtual_address
7757 Requests the current target to map the specified @var{virtual_address}
7758 to its corresponding physical address, and displays the result.
7761 @node Architecture and Core Commands
7762 @chapter Architecture and Core Commands
7763 @cindex Architecture Specific Commands
7764 @cindex Core Specific Commands
7766 Most CPUs have specialized JTAG operations to support debugging.
7767 OpenOCD packages most such operations in its standard command framework.
7768 Some of those operations don't fit well in that framework, so they are
7769 exposed here as architecture or implementation (core) specific commands.
7771 @anchor{armhardwaretracing}
7772 @section ARM Hardware Tracing
7777 CPUs based on ARM cores may include standard tracing interfaces,
7778 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
7779 address and data bus trace records to a ``Trace Port''.
7783 Development-oriented boards will sometimes provide a high speed
7784 trace connector for collecting that data, when the particular CPU
7785 supports such an interface.
7786 (The standard connector is a 38-pin Mictor, with both JTAG
7787 and trace port support.)
7788 Those trace connectors are supported by higher end JTAG adapters
7789 and some logic analyzer modules; frequently those modules can
7790 buffer several megabytes of trace data.
7791 Configuring an ETM coupled to such an external trace port belongs
7792 in the board-specific configuration file.
7794 If the CPU doesn't provide an external interface, it probably
7795 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
7796 dedicated SRAM. 4KBytes is one common ETB size.
7797 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
7798 (target) configuration file, since it works the same on all boards.
7801 ETM support in OpenOCD doesn't seem to be widely used yet.
7804 ETM support may be buggy, and at least some @command{etm config}
7805 parameters should be detected by asking the ETM for them.
7807 ETM trigger events could also implement a kind of complex
7808 hardware breakpoint, much more powerful than the simple
7809 watchpoint hardware exported by EmbeddedICE modules.
7810 @emph{Such breakpoints can be triggered even when using the
7811 dummy trace port driver}.
7813 It seems like a GDB hookup should be possible,
7814 as well as tracing only during specific states
7815 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
7817 There should be GUI tools to manipulate saved trace data and help
7818 analyse it in conjunction with the source code.
7819 It's unclear how much of a common interface is shared
7820 with the current XScale trace support, or should be
7821 shared with eventual Nexus-style trace module support.
7823 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
7824 for ETM modules is available. The code should be able to
7825 work with some newer cores; but not all of them support
7826 this original style of JTAG access.
7829 @subsection ETM Configuration
7830 ETM setup is coupled with the trace port driver configuration.
7832 @deffn {Config Command} {etm config} target width mode clocking driver
7833 Declares the ETM associated with @var{target}, and associates it
7834 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
7836 Several of the parameters must reflect the trace port capabilities,
7837 which are a function of silicon capabilities (exposed later
7838 using @command{etm info}) and of what hardware is connected to
7839 that port (such as an external pod, or ETB).
7840 The @var{width} must be either 4, 8, or 16,
7841 except with ETMv3.0 and newer modules which may also
7842 support 1, 2, 24, 32, 48, and 64 bit widths.
7843 (With those versions, @command{etm info} also shows whether
7844 the selected port width and mode are supported.)
7846 The @var{mode} must be @option{normal}, @option{multiplexed},
7847 or @option{demultiplexed}.
7848 The @var{clocking} must be @option{half} or @option{full}.
7851 With ETMv3.0 and newer, the bits set with the @var{mode} and
7852 @var{clocking} parameters both control the mode.
7853 This modified mode does not map to the values supported by
7854 previous ETM modules, so this syntax is subject to change.
7858 You can see the ETM registers using the @command{reg} command.
7859 Not all possible registers are present in every ETM.
7860 Most of the registers are write-only, and are used to configure
7861 what CPU activities are traced.
7865 @deffn Command {etm info}
7866 Displays information about the current target's ETM.
7867 This includes resource counts from the @code{ETM_CONFIG} register,
7868 as well as silicon capabilities (except on rather old modules).
7869 from the @code{ETM_SYS_CONFIG} register.
7872 @deffn Command {etm status}
7873 Displays status of the current target's ETM and trace port driver:
7874 is the ETM idle, or is it collecting data?
7875 Did trace data overflow?
7879 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
7880 Displays what data that ETM will collect.
7881 If arguments are provided, first configures that data.
7882 When the configuration changes, tracing is stopped
7883 and any buffered trace data is invalidated.
7886 @item @var{type} ... describing how data accesses are traced,
7887 when they pass any ViewData filtering that that was set up.
7889 @option{none} (save nothing),
7890 @option{data} (save data),
7891 @option{address} (save addresses),
7892 @option{all} (save data and addresses)
7893 @item @var{context_id_bits} ... 0, 8, 16, or 32
7894 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
7895 cycle-accurate instruction tracing.
7896 Before ETMv3, enabling this causes much extra data to be recorded.
7897 @item @var{branch_output} ... @option{enable} or @option{disable}.
7898 Disable this unless you need to try reconstructing the instruction
7899 trace stream without an image of the code.
7903 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
7904 Displays whether ETM triggering debug entry (like a breakpoint) is
7905 enabled or disabled, after optionally modifying that configuration.
7906 The default behaviour is @option{disable}.
7907 Any change takes effect after the next @command{etm start}.
7909 By using script commands to configure ETM registers, you can make the
7910 processor enter debug state automatically when certain conditions,
7911 more complex than supported by the breakpoint hardware, happen.
7914 @subsection ETM Trace Operation
7916 After setting up the ETM, you can use it to collect data.
7917 That data can be exported to files for later analysis.
7918 It can also be parsed with OpenOCD, for basic sanity checking.
7920 To configure what is being traced, you will need to write
7921 various trace registers using @command{reg ETM_*} commands.
7922 For the definitions of these registers, read ARM publication
7923 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
7924 Be aware that most of the relevant registers are write-only,
7925 and that ETM resources are limited. There are only a handful
7926 of address comparators, data comparators, counters, and so on.
7928 Examples of scenarios you might arrange to trace include:
7931 @item Code flow within a function, @emph{excluding} subroutines
7932 it calls. Use address range comparators to enable tracing
7933 for instruction access within that function's body.
7934 @item Code flow within a function, @emph{including} subroutines
7935 it calls. Use the sequencer and address comparators to activate
7936 tracing on an ``entered function'' state, then deactivate it by
7937 exiting that state when the function's exit code is invoked.
7938 @item Code flow starting at the fifth invocation of a function,
7939 combining one of the above models with a counter.
7940 @item CPU data accesses to the registers for a particular device,
7941 using address range comparators and the ViewData logic.
7942 @item Such data accesses only during IRQ handling, combining the above
7943 model with sequencer triggers which on entry and exit to the IRQ handler.
7944 @item @emph{... more}
7947 At this writing, September 2009, there are no Tcl utility
7948 procedures to help set up any common tracing scenarios.
7950 @deffn Command {etm analyze}
7951 Reads trace data into memory, if it wasn't already present.
7952 Decodes and prints the data that was collected.
7955 @deffn Command {etm dump} filename
7956 Stores the captured trace data in @file{filename}.
7959 @deffn Command {etm image} filename [base_address] [type]
7960 Opens an image file.
7963 @deffn Command {etm load} filename
7964 Loads captured trace data from @file{filename}.
7967 @deffn Command {etm start}
7968 Starts trace data collection.
7971 @deffn Command {etm stop}
7972 Stops trace data collection.
7975 @anchor{traceportdrivers}
7976 @subsection Trace Port Drivers
7978 To use an ETM trace port it must be associated with a driver.
7980 @deffn {Trace Port Driver} dummy
7981 Use the @option{dummy} driver if you are configuring an ETM that's
7982 not connected to anything (on-chip ETB or off-chip trace connector).
7983 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
7984 any trace data collection.}
7985 @deffn {Config Command} {etm_dummy config} target
7986 Associates the ETM for @var{target} with a dummy driver.
7990 @deffn {Trace Port Driver} etb
7991 Use the @option{etb} driver if you are configuring an ETM
7992 to use on-chip ETB memory.
7993 @deffn {Config Command} {etb config} target etb_tap
7994 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
7995 You can see the ETB registers using the @command{reg} command.
7997 @deffn Command {etb trigger_percent} [percent]
7998 This displays, or optionally changes, ETB behavior after the
7999 ETM's configured @emph{trigger} event fires.
8000 It controls how much more trace data is saved after the (single)
8001 trace trigger becomes active.
8004 @item The default corresponds to @emph{trace around} usage,
8005 recording 50 percent data before the event and the rest
8007 @item The minimum value of @var{percent} is 2 percent,
8008 recording almost exclusively data before the trigger.
8009 Such extreme @emph{trace before} usage can help figure out
8010 what caused that event to happen.
8011 @item The maximum value of @var{percent} is 100 percent,
8012 recording data almost exclusively after the event.
8013 This extreme @emph{trace after} usage might help sort out
8014 how the event caused trouble.
8016 @c REVISIT allow "break" too -- enter debug mode.
8021 @deffn {Trace Port Driver} oocd_trace
8022 This driver isn't available unless OpenOCD was explicitly configured
8023 with the @option{--enable-oocd_trace} option. You probably don't want
8024 to configure it unless you've built the appropriate prototype hardware;
8025 it's @emph{proof-of-concept} software.
8027 Use the @option{oocd_trace} driver if you are configuring an ETM that's
8028 connected to an off-chip trace connector.
8030 @deffn {Config Command} {oocd_trace config} target tty
8031 Associates the ETM for @var{target} with a trace driver which
8032 collects data through the serial port @var{tty}.
8035 @deffn Command {oocd_trace resync}
8036 Re-synchronizes with the capture clock.
8039 @deffn Command {oocd_trace status}
8040 Reports whether the capture clock is locked or not.
8044 @anchor{armcrosstrigger}
8045 @section ARM Cross-Trigger Interface
8048 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
8049 that connects event sources like tracing components or CPU cores with each
8050 other through a common trigger matrix (CTM). For ARMv8 architecture, a
8051 CTI is mandatory for core run control and each core has an individual
8052 CTI instance attached to it. OpenOCD has limited support for CTI using
8053 the @emph{cti} group of commands.
8055 @deffn Command {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-ctibase} base_address
8056 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
8057 @var{apn}. The @var{base_address} must match the base address of the CTI
8058 on the respective MEM-AP. All arguments are mandatory. This creates a
8059 new command @command{$cti_name} which is used for various purposes
8060 including additional configuration.
8063 @deffn Command {$cti_name enable} @option{on|off}
8064 Enable (@option{on}) or disable (@option{off}) the CTI.
8067 @deffn Command {$cti_name dump}
8068 Displays a register dump of the CTI.
8071 @deffn Command {$cti_name write } @var{reg_name} @var{value}
8072 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
8075 @deffn Command {$cti_name read} @var{reg_name}
8076 Print the value read from the CTI register with the symbolic name @var{reg_name}.
8079 @deffn Command {$cti_name testmode} @option{on|off}
8080 Enable (@option{on}) or disable (@option{off}) the integration test mode
8084 @deffn Command {cti names}
8085 Prints a list of names of all CTI objects created. This command is mainly
8086 useful in TCL scripting.
8089 @section Generic ARM
8092 These commands should be available on all ARM processors.
8093 They are available in addition to other core-specific
8094 commands that may be available.
8096 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
8097 Displays the core_state, optionally changing it to process
8098 either @option{arm} or @option{thumb} instructions.
8099 The target may later be resumed in the currently set core_state.
8100 (Processors may also support the Jazelle state, but
8101 that is not currently supported in OpenOCD.)
8104 @deffn Command {arm disassemble} address [count [@option{thumb}]]
8106 Disassembles @var{count} instructions starting at @var{address}.
8107 If @var{count} is not specified, a single instruction is disassembled.
8108 If @option{thumb} is specified, or the low bit of the address is set,
8109 Thumb2 (mixed 16/32-bit) instructions are used;
8110 else ARM (32-bit) instructions are used.
8111 (Processors may also support the Jazelle state, but
8112 those instructions are not currently understood by OpenOCD.)
8114 Note that all Thumb instructions are Thumb2 instructions,
8115 so older processors (without Thumb2 support) will still
8116 see correct disassembly of Thumb code.
8117 Also, ThumbEE opcodes are the same as Thumb2,
8118 with a handful of exceptions.
8119 ThumbEE disassembly currently has no explicit support.
8122 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
8123 Write @var{value} to a coprocessor @var{pX} register
8124 passing parameters @var{CRn},
8125 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8126 and using the MCR instruction.
8127 (Parameter sequence matches the ARM instruction, but omits
8131 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
8132 Read a coprocessor @var{pX} register passing parameters @var{CRn},
8133 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8134 and the MRC instruction.
8135 Returns the result so it can be manipulated by Jim scripts.
8136 (Parameter sequence matches the ARM instruction, but omits
8140 @deffn Command {arm reg}
8141 Display a table of all banked core registers, fetching the current value from every
8142 core mode if necessary.
8145 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
8146 @cindex ARM semihosting
8147 Display status of semihosting, after optionally changing that status.
8149 Semihosting allows for code executing on an ARM target to use the
8150 I/O facilities on the host computer i.e. the system where OpenOCD
8151 is running. The target application must be linked against a library
8152 implementing the ARM semihosting convention that forwards operation
8153 requests by using a special SVC instruction that is trapped at the
8154 Supervisor Call vector by OpenOCD.
8157 @deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
8158 @cindex ARM semihosting
8159 Set the command line to be passed to the debugger.
8162 arm semihosting_cmdline argv0 argv1 argv2 ...
8165 This option lets one set the command line arguments to be passed to
8166 the program. The first argument (argv0) is the program name in a
8167 standard C environment (argv[0]). Depending on the program (not much
8168 programs look at argv[0]), argv0 is ignored and can be any string.
8171 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
8172 @cindex ARM semihosting
8173 Display status of semihosting fileio, after optionally changing that
8176 Enabling this option forwards semihosting I/O to GDB process using the
8177 File-I/O remote protocol extension. This is especially useful for
8178 interacting with remote files or displaying console messages in the
8182 @deffn Command {arm semihosting_resexit} [@option{enable}|@option{disable}]
8183 @cindex ARM semihosting
8184 Enable resumable SEMIHOSTING_SYS_EXIT.
8186 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
8187 things are simple, the openocd process calls exit() and passes
8188 the value returned by the target.
8190 When SEMIHOSTING_SYS_EXIT is called during a debug session,
8191 by default execution returns to the debugger, leaving the
8192 debugger in a HALT state, similar to the state entered when
8193 encountering a break.
8195 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
8196 return normally, as any semihosting call, and do not break
8198 The standard allows this to happen, but the condition
8199 to trigger it is a bit obscure ("by performing an RDI_Execute
8200 request or equivalent").
8202 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
8203 this option (default: disabled).
8206 @section ARMv4 and ARMv5 Architecture
8210 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
8211 and introduced core parts of the instruction set in use today.
8212 That includes the Thumb instruction set, introduced in the ARMv4T
8215 @subsection ARM7 and ARM9 specific commands
8219 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
8220 ARM9TDMI, ARM920T or ARM926EJ-S.
8221 They are available in addition to the ARM commands,
8222 and any other core-specific commands that may be available.
8224 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
8225 Displays the value of the flag controlling use of the
8226 the EmbeddedIce DBGRQ signal to force entry into debug mode,
8227 instead of breakpoints.
8228 If a boolean parameter is provided, first assigns that flag.
8231 safe for all but ARM7TDMI-S cores (like NXP LPC).
8232 This feature is enabled by default on most ARM9 cores,
8233 including ARM9TDMI, ARM920T, and ARM926EJ-S.
8236 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
8238 Displays the value of the flag controlling use of the debug communications
8239 channel (DCC) to write larger (>128 byte) amounts of memory.
8240 If a boolean parameter is provided, first assigns that flag.
8242 DCC downloads offer a huge speed increase, but might be
8243 unsafe, especially with targets running at very low speeds. This command was introduced
8244 with OpenOCD rev. 60, and requires a few bytes of working area.
8247 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
8248 Displays the value of the flag controlling use of memory writes and reads
8249 that don't check completion of the operation.
8250 If a boolean parameter is provided, first assigns that flag.
8252 This provides a huge speed increase, especially with USB JTAG
8253 cables (FT2232), but might be unsafe if used with targets running at very low
8254 speeds, like the 32kHz startup clock of an AT91RM9200.
8257 @subsection ARM720T specific commands
8260 These commands are available to ARM720T based CPUs,
8261 which are implementations of the ARMv4T architecture
8262 based on the ARM7TDMI-S integer core.
8263 They are available in addition to the ARM and ARM7/ARM9 commands.
8265 @deffn Command {arm720t cp15} opcode [value]
8266 @emph{DEPRECATED -- avoid using this.
8267 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8269 Display cp15 register returned by the ARM instruction @var{opcode};
8270 else if a @var{value} is provided, that value is written to that register.
8271 The @var{opcode} should be the value of either an MRC or MCR instruction.
8274 @subsection ARM9 specific commands
8277 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
8279 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
8281 @c 9-june-2009: tried this on arm920t, it didn't work.
8282 @c no-params always lists nothing caught, and that's how it acts.
8283 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
8284 @c versions have different rules about when they commit writes.
8286 @anchor{arm9vectorcatch}
8287 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
8288 @cindex vector_catch
8289 Vector Catch hardware provides a sort of dedicated breakpoint
8290 for hardware events such as reset, interrupt, and abort.
8291 You can use this to conserve normal breakpoint resources,
8292 so long as you're not concerned with code that branches directly
8293 to those hardware vectors.
8295 This always finishes by listing the current configuration.
8296 If parameters are provided, it first reconfigures the
8297 vector catch hardware to intercept
8298 @option{all} of the hardware vectors,
8299 @option{none} of them,
8300 or a list with one or more of the following:
8301 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
8302 @option{irq} @option{fiq}.
8305 @subsection ARM920T specific commands
8308 These commands are available to ARM920T based CPUs,
8309 which are implementations of the ARMv4T architecture
8310 built using the ARM9TDMI integer core.
8311 They are available in addition to the ARM, ARM7/ARM9,
8314 @deffn Command {arm920t cache_info}
8315 Print information about the caches found. This allows to see whether your target
8316 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
8319 @deffn Command {arm920t cp15} regnum [value]
8320 Display cp15 register @var{regnum};
8321 else if a @var{value} is provided, that value is written to that register.
8322 This uses "physical access" and the register number is as
8323 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
8324 (Not all registers can be written.)
8327 @deffn Command {arm920t cp15i} opcode [value [address]]
8328 @emph{DEPRECATED -- avoid using this.
8329 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8331 Interpreted access using ARM instruction @var{opcode}, which should
8332 be the value of either an MRC or MCR instruction
8333 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
8334 If no @var{value} is provided, the result is displayed.
8335 Else if that value is written using the specified @var{address},
8336 or using zero if no other address is provided.
8339 @deffn Command {arm920t read_cache} filename
8340 Dump the content of ICache and DCache to a file named @file{filename}.
8343 @deffn Command {arm920t read_mmu} filename
8344 Dump the content of the ITLB and DTLB to a file named @file{filename}.
8347 @subsection ARM926ej-s specific commands
8350 These commands are available to ARM926ej-s based CPUs,
8351 which are implementations of the ARMv5TEJ architecture
8352 based on the ARM9EJ-S integer core.
8353 They are available in addition to the ARM, ARM7/ARM9,
8356 The Feroceon cores also support these commands, although
8357 they are not built from ARM926ej-s designs.
8359 @deffn Command {arm926ejs cache_info}
8360 Print information about the caches found.
8363 @subsection ARM966E specific commands
8366 These commands are available to ARM966 based CPUs,
8367 which are implementations of the ARMv5TE architecture.
8368 They are available in addition to the ARM, ARM7/ARM9,
8371 @deffn Command {arm966e cp15} regnum [value]
8372 Display cp15 register @var{regnum};
8373 else if a @var{value} is provided, that value is written to that register.
8374 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
8376 There is no current control over bits 31..30 from that table,
8377 as required for BIST support.
8380 @subsection XScale specific commands
8383 Some notes about the debug implementation on the XScale CPUs:
8385 The XScale CPU provides a special debug-only mini-instruction cache
8386 (mini-IC) in which exception vectors and target-resident debug handler
8387 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
8388 must point vector 0 (the reset vector) to the entry of the debug
8389 handler. However, this means that the complete first cacheline in the
8390 mini-IC is marked valid, which makes the CPU fetch all exception
8391 handlers from the mini-IC, ignoring the code in RAM.
8393 To address this situation, OpenOCD provides the @code{xscale
8394 vector_table} command, which allows the user to explicitly write
8395 individual entries to either the high or low vector table stored in
8398 It is recommended to place a pc-relative indirect branch in the vector
8399 table, and put the branch destination somewhere in memory. Doing so
8400 makes sure the code in the vector table stays constant regardless of
8401 code layout in memory:
8404 ldr pc,[pc,#0x100-8]
8405 ldr pc,[pc,#0x100-8]
8406 ldr pc,[pc,#0x100-8]
8407 ldr pc,[pc,#0x100-8]
8408 ldr pc,[pc,#0x100-8]
8409 ldr pc,[pc,#0x100-8]
8410 ldr pc,[pc,#0x100-8]
8411 ldr pc,[pc,#0x100-8]
8413 .long real_reset_vector
8414 .long real_ui_handler
8415 .long real_swi_handler
8417 .long real_data_abort
8418 .long 0 /* unused */
8419 .long real_irq_handler
8420 .long real_fiq_handler
8423 Alternatively, you may choose to keep some or all of the mini-IC
8424 vector table entries synced with those written to memory by your
8425 system software. The mini-IC can not be modified while the processor
8426 is executing, but for each vector table entry not previously defined
8427 using the @code{xscale vector_table} command, OpenOCD will copy the
8428 value from memory to the mini-IC every time execution resumes from a
8429 halt. This is done for both high and low vector tables (although the
8430 table not in use may not be mapped to valid memory, and in this case
8431 that copy operation will silently fail). This means that you will
8432 need to briefly halt execution at some strategic point during system
8433 start-up; e.g., after the software has initialized the vector table,
8434 but before exceptions are enabled. A breakpoint can be used to
8435 accomplish this once the appropriate location in the start-up code has
8436 been identified. A watchpoint over the vector table region is helpful
8437 in finding the location if you're not sure. Note that the same
8438 situation exists any time the vector table is modified by the system
8441 The debug handler must be placed somewhere in the address space using
8442 the @code{xscale debug_handler} command. The allowed locations for the
8443 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
8444 0xfffff800). The default value is 0xfe000800.
8446 XScale has resources to support two hardware breakpoints and two
8447 watchpoints. However, the following restrictions on watchpoint
8448 functionality apply: (1) the value and mask arguments to the @code{wp}
8449 command are not supported, (2) the watchpoint length must be a
8450 power of two and not less than four, and can not be greater than the
8451 watchpoint address, and (3) a watchpoint with a length greater than
8452 four consumes all the watchpoint hardware resources. This means that
8453 at any one time, you can have enabled either two watchpoints with a
8454 length of four, or one watchpoint with a length greater than four.
8456 These commands are available to XScale based CPUs,
8457 which are implementations of the ARMv5TE architecture.
8459 @deffn Command {xscale analyze_trace}
8460 Displays the contents of the trace buffer.
8463 @deffn Command {xscale cache_clean_address} address
8464 Changes the address used when cleaning the data cache.
8467 @deffn Command {xscale cache_info}
8468 Displays information about the CPU caches.
8471 @deffn Command {xscale cp15} regnum [value]
8472 Display cp15 register @var{regnum};
8473 else if a @var{value} is provided, that value is written to that register.
8476 @deffn Command {xscale debug_handler} target address
8477 Changes the address used for the specified target's debug handler.
8480 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
8481 Enables or disable the CPU's data cache.
8484 @deffn Command {xscale dump_trace} filename
8485 Dumps the raw contents of the trace buffer to @file{filename}.
8488 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
8489 Enables or disable the CPU's instruction cache.
8492 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
8493 Enables or disable the CPU's memory management unit.
8496 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
8497 Displays the trace buffer status, after optionally
8498 enabling or disabling the trace buffer
8499 and modifying how it is emptied.
8502 @deffn Command {xscale trace_image} filename [offset [type]]
8503 Opens a trace image from @file{filename}, optionally rebasing
8504 its segment addresses by @var{offset}.
8505 The image @var{type} may be one of
8506 @option{bin} (binary), @option{ihex} (Intel hex),
8507 @option{elf} (ELF file), @option{s19} (Motorola s19),
8508 @option{mem}, or @option{builder}.
8511 @anchor{xscalevectorcatch}
8512 @deffn Command {xscale vector_catch} [mask]
8513 @cindex vector_catch
8514 Display a bitmask showing the hardware vectors to catch.
8515 If the optional parameter is provided, first set the bitmask to that value.
8517 The mask bits correspond with bit 16..23 in the DCSR:
8520 0x02 Trap Undefined Instructions
8521 0x04 Trap Software Interrupt
8522 0x08 Trap Prefetch Abort
8523 0x10 Trap Data Abort
8530 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
8531 @cindex vector_table
8533 Set an entry in the mini-IC vector table. There are two tables: one for
8534 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
8535 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
8536 points to the debug handler entry and can not be overwritten.
8537 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
8539 Without arguments, the current settings are displayed.
8543 @section ARMv6 Architecture
8546 @subsection ARM11 specific commands
8549 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
8550 Displays the value of the memwrite burst-enable flag,
8551 which is enabled by default.
8552 If a boolean parameter is provided, first assigns that flag.
8553 Burst writes are only used for memory writes larger than 1 word.
8554 They improve performance by assuming that the CPU has read each data
8555 word over JTAG and completed its write before the next word arrives,
8556 instead of polling for a status flag to verify that completion.
8557 This is usually safe, because JTAG runs much slower than the CPU.
8560 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
8561 Displays the value of the memwrite error_fatal flag,
8562 which is enabled by default.
8563 If a boolean parameter is provided, first assigns that flag.
8564 When set, certain memory write errors cause earlier transfer termination.
8567 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
8568 Displays the value of the flag controlling whether
8569 IRQs are enabled during single stepping;
8570 they are disabled by default.
8571 If a boolean parameter is provided, first assigns that.
8574 @deffn Command {arm11 vcr} [value]
8575 @cindex vector_catch
8576 Displays the value of the @emph{Vector Catch Register (VCR)},
8577 coprocessor 14 register 7.
8578 If @var{value} is defined, first assigns that.
8580 Vector Catch hardware provides dedicated breakpoints
8581 for certain hardware events.
8582 The specific bit values are core-specific (as in fact is using
8583 coprocessor 14 register 7 itself) but all current ARM11
8584 cores @emph{except the ARM1176} use the same six bits.
8587 @section ARMv7 and ARMv8 Architecture
8591 @subsection ARMv7-A specific commands
8594 @deffn Command {cortex_a cache_info}
8595 display information about target caches
8598 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
8599 Work around issues with software breakpoints when the program text is
8600 mapped read-only by the operating system. This option sets the CP15 DACR
8601 to "all-manager" to bypass MMU permission checks on memory access.
8605 @deffn Command {cortex_a dbginit}
8606 Initialize core debug
8607 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8610 @deffn Command {cortex_a smp_off}
8614 @deffn Command {cortex_a smp_on}
8618 @deffn Command {cortex_a smp_gdb} [core_id]
8619 Display/set the current core displayed in GDB
8622 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
8623 Selects whether interrupts will be processed when single stepping
8626 @deffn Command {cache_config l2x} [base way]
8631 @subsection ARMv7-R specific commands
8634 @deffn Command {cortex_r dbginit}
8635 Initialize core debug
8636 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8639 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
8640 Selects whether interrupts will be processed when single stepping
8644 @subsection ARMv7-M specific commands
8652 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
8653 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
8654 @var{TRACECLKIN_freq} [@var{trace_freq}]))
8656 ARMv7-M architecture provides several modules to generate debugging
8657 information internally (ITM, DWT and ETM). Their output is directed
8658 through TPIU to be captured externally either on an SWO pin (this
8659 configuration is called SWV) or on a synchronous parallel trace port.
8661 This command configures the TPIU module of the target and, if internal
8662 capture mode is selected, starts to capture trace output by using the
8663 debugger adapter features.
8665 Some targets require additional actions to be performed in the
8666 @b{trace-config} handler for trace port to be activated.
8670 @item @option{disable} disable TPIU handling;
8671 @item @option{external} configure TPIU to let user capture trace
8672 output externally (with an additional UART or logic analyzer hardware);
8673 @item @option{internal @var{filename}} configure TPIU and debug adapter to
8674 gather trace data and append it to @var{filename} (which can be
8675 either a regular file or a named pipe);
8676 @item @option{internal -} configure TPIU and debug adapter to
8677 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
8678 @item @option{sync @var{port_width}} use synchronous parallel trace output
8679 mode, and set port width to @var{port_width};
8680 @item @option{manchester} use asynchronous SWO mode with Manchester
8682 @item @option{uart} use asynchronous SWO mode with NRZ (same as
8683 regular UART 8N1) coding;
8684 @item @var{formatter_enable} is @option{on} or @option{off} to enable
8685 or disable TPIU formatter which needs to be used when both ITM and ETM
8686 data is to be output via SWO;
8687 @item @var{TRACECLKIN_freq} this should be specified to match target's
8688 current TRACECLKIN frequency (usually the same as HCLK);
8689 @item @var{trace_freq} trace port frequency. Can be omitted in
8690 internal mode to let the adapter driver select the maximum supported
8696 @item STM32L152 board is programmed with an application that configures
8697 PLL to provide core clock with 24MHz frequency; to use ITM output it's
8700 #include <libopencm3/cm3/itm.h>
8705 (the most obvious way is to use the first stimulus port for printf,
8706 for that this ITM_STIM8 assignment can be used inside _write(); to make it
8707 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
8708 ITM_STIM_FIFOREADY));});
8709 @item An FT2232H UART is connected to the SWO pin of the board;
8710 @item Commands to configure UART for 12MHz baud rate:
8712 $ setserial /dev/ttyUSB1 spd_cust divisor 5
8713 $ stty -F /dev/ttyUSB1 38400
8715 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
8716 baud with our custom divisor to get 12MHz)
8717 @item @code{itmdump -f /dev/ttyUSB1 -d1}
8718 @item OpenOCD invocation line:
8720 openocd -f interface/stlink-v2-1.cfg \
8721 -c "transport select hla_swd" \
8722 -f target/stm32l1.cfg \
8723 -c "tpiu config external uart off 24000000 12000000"
8728 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
8729 Enable or disable trace output for ITM stimulus @var{port} (counting
8730 from 0). Port 0 is enabled on target creation automatically.
8733 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
8734 Enable or disable trace output for all ITM stimulus ports.
8737 @subsection Cortex-M specific commands
8740 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
8741 Control masking (disabling) interrupts during target step/resume.
8743 The @option{auto} option handles interrupts during stepping a way they get
8744 served but don't disturb the program flow. The step command first allows
8745 pending interrupt handlers to execute, then disables interrupts and steps over
8746 the next instruction where the core was halted. After the step interrupts
8747 are enabled again. If the interrupt handlers don't complete within 500ms,
8748 the step command leaves with the core running.
8750 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
8751 option. If no breakpoint is available at the time of the step, then the step
8752 is taken with interrupts enabled, i.e. the same way the @option{off} option
8755 Default is @option{auto}.
8758 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
8759 @cindex vector_catch
8760 Vector Catch hardware provides dedicated breakpoints
8761 for certain hardware events.
8763 Parameters request interception of
8764 @option{all} of these hardware event vectors,
8765 @option{none} of them,
8766 or one or more of the following:
8767 @option{hard_err} for a HardFault exception;
8768 @option{mm_err} for a MemManage exception;
8769 @option{bus_err} for a BusFault exception;
8772 @option{chk_err}, or
8773 @option{nocp_err} for various UsageFault exceptions; or
8775 If NVIC setup code does not enable them,
8776 MemManage, BusFault, and UsageFault exceptions
8777 are mapped to HardFault.
8778 UsageFault checks for
8779 divide-by-zero and unaligned access
8780 must also be explicitly enabled.
8782 This finishes by listing the current vector catch configuration.
8785 @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
8786 Control reset handling. The default @option{srst} is to use srst if fitted,
8787 otherwise fallback to @option{vectreset}.
8789 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
8790 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
8791 @item @option{vectreset} use NVIC VECTRESET to reset system.
8793 Using @option{vectreset} is a safe option for all current Cortex-M cores.
8794 This however has the disadvantage of only resetting the core, all peripherals
8795 are unaffected. A solution would be to use a @code{reset-init} event handler to manually reset
8797 @xref{targetevents,,Target Events}.
8800 @subsection ARMv8-A specific commands
8804 @deffn Command {aarch64 cache_info}
8805 Display information about target caches
8808 @deffn Command {aarch64 dbginit}
8809 This command enables debugging by clearing the OS Lock and sticky power-down and reset
8810 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
8811 target code relies on. In a configuration file, the command would typically be called from a
8812 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
8813 However, normally it is not necessary to use the command at all.
8816 @deffn Command {aarch64 smp_on|smp_off}
8817 Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group
8818 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
8819 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
8820 group. With SMP handling disabled, all targets need to be treated individually.
8823 @deffn Command {aarch64 maskisr} [@option{on}|@option{off}]
8824 Selects whether interrupts will be processed when single stepping. The default configuration is
8828 @section Intel Architecture
8830 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
8831 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
8832 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
8833 software debug and the CLTAP is used for SoC level operations.
8834 Useful docs are here: https://communities.intel.com/community/makers/documentation
8836 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
8837 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
8838 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
8841 @subsection x86 32-bit specific commands
8842 The three main address spaces for x86 are memory, I/O and configuration space.
8843 These commands allow a user to read and write to the 64Kbyte I/O address space.
8845 @deffn Command {x86_32 idw} address
8846 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
8849 @deffn Command {x86_32 idh} address
8850 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
8853 @deffn Command {x86_32 idb} address
8854 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
8857 @deffn Command {x86_32 iww} address
8858 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
8861 @deffn Command {x86_32 iwh} address
8862 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
8865 @deffn Command {x86_32 iwb} address
8866 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
8869 @section OpenRISC Architecture
8871 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
8872 configured with any of the TAP / Debug Unit available.
8874 @subsection TAP and Debug Unit selection commands
8875 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
8876 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
8878 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
8879 Select between the Advanced Debug Interface and the classic one.
8881 An option can be passed as a second argument to the debug unit.
8883 When using the Advanced Debug Interface, option = 1 means the RTL core is
8884 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
8885 between bytes while doing read or write bursts.
8888 @subsection Registers commands
8889 @deffn Command {addreg} [name] [address] [feature] [reg_group]
8890 Add a new register in the cpu register list. This register will be
8891 included in the generated target descriptor file.
8893 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
8895 @strong{[reg_group]} can be anything. The default register list defines "system",
8896 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
8901 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
8906 @deffn Command {readgroup} (@option{group})
8907 Display all registers in @emph{group}.
8909 @emph{group} can be "system",
8910 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
8911 "timer" or any new group created with addreg command.
8914 @anchor{softwaredebugmessagesandtracing}
8915 @section Software Debug Messages and Tracing
8916 @cindex Linux-ARM DCC support
8920 OpenOCD can process certain requests from target software, when
8921 the target uses appropriate libraries.
8922 The most powerful mechanism is semihosting, but there is also
8923 a lighter weight mechanism using only the DCC channel.
8925 Currently @command{target_request debugmsgs}
8926 is supported only for @option{arm7_9} and @option{cortex_m} cores.
8927 These messages are received as part of target polling, so
8928 you need to have @command{poll on} active to receive them.
8929 They are intrusive in that they will affect program execution
8930 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
8932 See @file{libdcc} in the contrib dir for more details.
8933 In addition to sending strings, characters, and
8934 arrays of various size integers from the target,
8935 @file{libdcc} also exports a software trace point mechanism.
8936 The target being debugged may
8937 issue trace messages which include a 24-bit @dfn{trace point} number.
8938 Trace point support includes two distinct mechanisms,
8939 each supported by a command:
8942 @item @emph{History} ... A circular buffer of trace points
8943 can be set up, and then displayed at any time.
8944 This tracks where code has been, which can be invaluable in
8945 finding out how some fault was triggered.
8947 The buffer may overflow, since it collects records continuously.
8948 It may be useful to use some of the 24 bits to represent a
8949 particular event, and other bits to hold data.
8951 @item @emph{Counting} ... An array of counters can be set up,
8952 and then displayed at any time.
8953 This can help establish code coverage and identify hot spots.
8955 The array of counters is directly indexed by the trace point
8956 number, so trace points with higher numbers are not counted.
8959 Linux-ARM kernels have a ``Kernel low-level debugging
8960 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
8961 depends on CONFIG_DEBUG_LL) which uses this mechanism to
8962 deliver messages before a serial console can be activated.
8963 This is not the same format used by @file{libdcc}.
8964 Other software, such as the U-Boot boot loader, sometimes
8965 does the same thing.
8967 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
8968 Displays current handling of target DCC message requests.
8969 These messages may be sent to the debugger while the target is running.
8970 The optional @option{enable} and @option{charmsg} parameters
8971 both enable the messages, while @option{disable} disables them.
8973 With @option{charmsg} the DCC words each contain one character,
8974 as used by Linux with CONFIG_DEBUG_ICEDCC;
8975 otherwise the libdcc format is used.
8978 @deffn Command {trace history} [@option{clear}|count]
8979 With no parameter, displays all the trace points that have triggered
8980 in the order they triggered.
8981 With the parameter @option{clear}, erases all current trace history records.
8982 With a @var{count} parameter, allocates space for that many
8986 @deffn Command {trace point} [@option{clear}|identifier]
8987 With no parameter, displays all trace point identifiers and how many times
8988 they have been triggered.
8989 With the parameter @option{clear}, erases all current trace point counters.
8990 With a numeric @var{identifier} parameter, creates a new a trace point counter
8991 and associates it with that identifier.
8993 @emph{Important:} The identifier and the trace point number
8994 are not related except by this command.
8995 These trace point numbers always start at zero (from server startup,
8996 or after @command{trace point clear}) and count up from there.
9001 @chapter JTAG Commands
9002 @cindex JTAG Commands
9003 Most general purpose JTAG commands have been presented earlier.
9004 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
9005 Lower level JTAG commands, as presented here,
9006 may be needed to work with targets which require special
9007 attention during operations such as reset or initialization.
9009 To use these commands you will need to understand some
9010 of the basics of JTAG, including:
9013 @item A JTAG scan chain consists of a sequence of individual TAP
9014 devices such as a CPUs.
9015 @item Control operations involve moving each TAP through the same
9016 standard state machine (in parallel)
9017 using their shared TMS and clock signals.
9018 @item Data transfer involves shifting data through the chain of
9019 instruction or data registers of each TAP, writing new register values
9020 while the reading previous ones.
9021 @item Data register sizes are a function of the instruction active in
9022 a given TAP, while instruction register sizes are fixed for each TAP.
9023 All TAPs support a BYPASS instruction with a single bit data register.
9024 @item The way OpenOCD differentiates between TAP devices is by
9025 shifting different instructions into (and out of) their instruction
9029 @section Low Level JTAG Commands
9031 These commands are used by developers who need to access
9032 JTAG instruction or data registers, possibly controlling
9033 the order of TAP state transitions.
9034 If you're not debugging OpenOCD internals, or bringing up a
9035 new JTAG adapter or a new type of TAP device (like a CPU or
9036 JTAG router), you probably won't need to use these commands.
9037 In a debug session that doesn't use JTAG for its transport protocol,
9038 these commands are not available.
9040 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
9041 Loads the data register of @var{tap} with a series of bit fields
9042 that specify the entire register.
9043 Each field is @var{numbits} bits long with
9044 a numeric @var{value} (hexadecimal encouraged).
9045 The return value holds the original value of each
9048 For example, a 38 bit number might be specified as one
9049 field of 32 bits then one of 6 bits.
9050 @emph{For portability, never pass fields which are more
9051 than 32 bits long. Many OpenOCD implementations do not
9052 support 64-bit (or larger) integer values.}
9054 All TAPs other than @var{tap} must be in BYPASS mode.
9055 The single bit in their data registers does not matter.
9057 When @var{tap_state} is specified, the JTAG state machine is left
9059 For example @sc{drpause} might be specified, so that more
9060 instructions can be issued before re-entering the @sc{run/idle} state.
9061 If the end state is not specified, the @sc{run/idle} state is entered.
9064 OpenOCD does not record information about data register lengths,
9065 so @emph{it is important that you get the bit field lengths right}.
9066 Remember that different JTAG instructions refer to different
9067 data registers, which may have different lengths.
9068 Moreover, those lengths may not be fixed;
9069 the SCAN_N instruction can change the length of
9070 the register accessed by the INTEST instruction
9071 (by connecting a different scan chain).
9075 @deffn Command {flush_count}
9076 Returns the number of times the JTAG queue has been flushed.
9077 This may be used for performance tuning.
9079 For example, flushing a queue over USB involves a
9080 minimum latency, often several milliseconds, which does
9081 not change with the amount of data which is written.
9082 You may be able to identify performance problems by finding
9083 tasks which waste bandwidth by flushing small transfers too often,
9084 instead of batching them into larger operations.
9087 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
9088 For each @var{tap} listed, loads the instruction register
9089 with its associated numeric @var{instruction}.
9090 (The number of bits in that instruction may be displayed
9091 using the @command{scan_chain} command.)
9092 For other TAPs, a BYPASS instruction is loaded.
9094 When @var{tap_state} is specified, the JTAG state machine is left
9096 For example @sc{irpause} might be specified, so the data register
9097 can be loaded before re-entering the @sc{run/idle} state.
9098 If the end state is not specified, the @sc{run/idle} state is entered.
9101 OpenOCD currently supports only a single field for instruction
9102 register values, unlike data register values.
9103 For TAPs where the instruction register length is more than 32 bits,
9104 portable scripts currently must issue only BYPASS instructions.
9108 @deffn Command {jtag_reset} trst srst
9109 Set values of reset signals.
9110 The @var{trst} and @var{srst} parameter values may be
9111 @option{0}, indicating that reset is inactive (pulled or driven high),
9112 or @option{1}, indicating it is active (pulled or driven low).
9113 The @command{reset_config} command should already have been used
9114 to configure how the board and JTAG adapter treat these two
9115 signals, and to say if either signal is even present.
9116 @xref{Reset Configuration}.
9118 Note that TRST is specially handled.
9119 It actually signifies JTAG's @sc{reset} state.
9120 So if the board doesn't support the optional TRST signal,
9121 or it doesn't support it along with the specified SRST value,
9122 JTAG reset is triggered with TMS and TCK signals
9123 instead of the TRST signal.
9124 And no matter how that JTAG reset is triggered, once
9125 the scan chain enters @sc{reset} with TRST inactive,
9126 TAP @code{post-reset} events are delivered to all TAPs
9127 with handlers for that event.
9130 @deffn Command {pathmove} start_state [next_state ...]
9131 Start by moving to @var{start_state}, which
9132 must be one of the @emph{stable} states.
9133 Unless it is the only state given, this will often be the
9134 current state, so that no TCK transitions are needed.
9135 Then, in a series of single state transitions
9136 (conforming to the JTAG state machine) shift to
9137 each @var{next_state} in sequence, one per TCK cycle.
9138 The final state must also be stable.
9141 @deffn Command {runtest} @var{num_cycles}
9142 Move to the @sc{run/idle} state, and execute at least
9143 @var{num_cycles} of the JTAG clock (TCK).
9144 Instructions often need some time
9145 to execute before they take effect.
9148 @c tms_sequence (short|long)
9149 @c ... temporary, debug-only, other than USBprog bug workaround...
9151 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
9152 Verify values captured during @sc{ircapture} and returned
9153 during IR scans. Default is enabled, but this can be
9154 overridden by @command{verify_jtag}.
9155 This flag is ignored when validating JTAG chain configuration.
9158 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
9159 Enables verification of DR and IR scans, to help detect
9160 programming errors. For IR scans, @command{verify_ircapture}
9161 must also be enabled.
9165 @section TAP state names
9166 @cindex TAP state names
9168 The @var{tap_state} names used by OpenOCD in the @command{drscan},
9169 @command{irscan}, and @command{pathmove} commands are the same
9170 as those used in SVF boundary scan documents, except that
9171 SVF uses @sc{idle} instead of @sc{run/idle}.
9174 @item @b{RESET} ... @emph{stable} (with TMS high);
9175 acts as if TRST were pulsed
9176 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
9179 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
9180 through the data register
9182 @item @b{DRPAUSE} ... @emph{stable}; data register ready
9183 for update or more shifting
9188 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
9189 through the instruction register
9191 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
9192 for update or more shifting
9197 Note that only six of those states are fully ``stable'' in the
9198 face of TMS fixed (low except for @sc{reset})
9199 and a free-running JTAG clock. For all the
9200 others, the next TCK transition changes to a new state.
9203 @item From @sc{drshift} and @sc{irshift}, clock transitions will
9204 produce side effects by changing register contents. The values
9205 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
9206 may not be as expected.
9207 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
9208 choices after @command{drscan} or @command{irscan} commands,
9209 since they are free of JTAG side effects.
9210 @item @sc{run/idle} may have side effects that appear at non-JTAG
9211 levels, such as advancing the ARM9E-S instruction pipeline.
9212 Consult the documentation for the TAP(s) you are working with.
9215 @node Boundary Scan Commands
9216 @chapter Boundary Scan Commands
9218 One of the original purposes of JTAG was to support
9219 boundary scan based hardware testing.
9220 Although its primary focus is to support On-Chip Debugging,
9221 OpenOCD also includes some boundary scan commands.
9223 @section SVF: Serial Vector Format
9224 @cindex Serial Vector Format
9227 The Serial Vector Format, better known as @dfn{SVF}, is a
9228 way to represent JTAG test patterns in text files.
9229 In a debug session using JTAG for its transport protocol,
9230 OpenOCD supports running such test files.
9232 @deffn Command {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
9233 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
9234 This issues a JTAG reset (Test-Logic-Reset) and then
9235 runs the SVF script from @file{filename}.
9237 Arguments can be specified in any order; the optional dash doesn't
9238 affect their semantics.
9242 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
9243 specified by the SVF file with HIR, TIR, HDR and TDR commands;
9244 instead, calculate them automatically according to the current JTAG
9245 chain configuration, targeting @var{tapname};
9246 @item @option{[-]quiet} do not log every command before execution;
9247 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
9248 on the real interface;
9249 @item @option{[-]progress} enable progress indication;
9250 @item @option{[-]ignore_error} continue execution despite TDO check
9255 @section XSVF: Xilinx Serial Vector Format
9256 @cindex Xilinx Serial Vector Format
9259 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
9260 binary representation of SVF which is optimized for use with
9262 In a debug session using JTAG for its transport protocol,
9263 OpenOCD supports running such test files.
9265 @quotation Important
9266 Not all XSVF commands are supported.
9269 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
9270 This issues a JTAG reset (Test-Logic-Reset) and then
9271 runs the XSVF script from @file{filename}.
9272 When a @var{tapname} is specified, the commands are directed at
9274 When @option{virt2} is specified, the @sc{xruntest} command counts
9275 are interpreted as TCK cycles instead of microseconds.
9276 Unless the @option{quiet} option is specified,
9277 messages are logged for comments and some retries.
9280 The OpenOCD sources also include two utility scripts
9281 for working with XSVF; they are not currently installed
9282 after building the software.
9283 You may find them useful:
9286 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
9287 syntax understood by the @command{xsvf} command; see notes below.
9288 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
9289 understands the OpenOCD extensions.
9292 The input format accepts a handful of non-standard extensions.
9293 These include three opcodes corresponding to SVF extensions
9294 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
9295 two opcodes supporting a more accurate translation of SVF
9296 (XTRST, XWAITSTATE).
9297 If @emph{xsvfdump} shows a file is using those opcodes, it
9298 probably will not be usable with other XSVF tools.
9301 @node Utility Commands
9302 @chapter Utility Commands
9303 @cindex Utility Commands
9305 @section RAM testing
9308 There is often a need to stress-test random access memory (RAM) for
9309 errors. OpenOCD comes with a Tcl implementation of well-known memory
9310 testing procedures allowing the detection of all sorts of issues with
9311 electrical wiring, defective chips, PCB layout and other common
9314 To use them, you usually need to initialise your RAM controller first;
9315 consult your SoC's documentation to get the recommended list of
9316 register operations and translate them to the corresponding
9317 @command{mww}/@command{mwb} commands.
9319 Load the memory testing functions with
9322 source [find tools/memtest.tcl]
9325 to get access to the following facilities:
9327 @deffn Command {memTestDataBus} address
9328 Test the data bus wiring in a memory region by performing a walking
9329 1's test at a fixed address within that region.
9332 @deffn Command {memTestAddressBus} baseaddress size
9333 Perform a walking 1's test on the relevant bits of the address and
9334 check for aliasing. This test will find single-bit address failures
9335 such as stuck-high, stuck-low, and shorted pins.
9338 @deffn Command {memTestDevice} baseaddress size
9339 Test the integrity of a physical memory device by performing an
9340 increment/decrement test over the entire region. In the process every
9341 storage bit in the device is tested as zero and as one.
9344 @deffn Command {runAllMemTests} baseaddress size
9345 Run all of the above tests over a specified memory region.
9348 @section Firmware recovery helpers
9349 @cindex Firmware recovery
9351 OpenOCD includes an easy-to-use script to facilitate mass-market
9352 devices recovery with JTAG.
9354 For quickstart instructions run:
9356 openocd -f tools/firmware-recovery.tcl -c firmware_help
9362 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
9363 be used to access files on PCs (either the developer's PC or some other PC).
9365 The way this works on the ZY1000 is to prefix a filename by
9366 "/tftp/ip/" and append the TFTP path on the TFTP
9367 server (tftpd). For example,
9370 load_image /tftp/10.0.0.96/c:\temp\abc.elf
9373 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
9374 if the file was hosted on the embedded host.
9376 In order to achieve decent performance, you must choose a TFTP server
9377 that supports a packet size bigger than the default packet size (512 bytes). There
9378 are numerous TFTP servers out there (free and commercial) and you will have to do
9379 a bit of googling to find something that fits your requirements.
9381 @node GDB and OpenOCD
9382 @chapter GDB and OpenOCD
9384 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
9385 to debug remote targets.
9386 Setting up GDB to work with OpenOCD can involve several components:
9389 @item The OpenOCD server support for GDB may need to be configured.
9390 @xref{gdbconfiguration,,GDB Configuration}.
9391 @item GDB's support for OpenOCD may need configuration,
9392 as shown in this chapter.
9393 @item If you have a GUI environment like Eclipse,
9394 that also will probably need to be configured.
9397 Of course, the version of GDB you use will need to be one which has
9398 been built to know about the target CPU you're using. It's probably
9399 part of the tool chain you're using. For example, if you are doing
9400 cross-development for ARM on an x86 PC, instead of using the native
9401 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
9402 if that's the tool chain used to compile your code.
9404 @section Connecting to GDB
9405 @cindex Connecting to GDB
9406 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
9407 instance GDB 6.3 has a known bug that produces bogus memory access
9408 errors, which has since been fixed; see
9409 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
9411 OpenOCD can communicate with GDB in two ways:
9415 A socket (TCP/IP) connection is typically started as follows:
9417 target remote localhost:3333
9419 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
9421 It is also possible to use the GDB extended remote protocol as follows:
9423 target extended-remote localhost:3333
9426 A pipe connection is typically started as follows:
9428 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
9430 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
9431 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
9432 session. log_output sends the log output to a file to ensure that the pipe is
9433 not saturated when using higher debug level outputs.
9436 To list the available OpenOCD commands type @command{monitor help} on the
9439 @section Sample GDB session startup
9441 With the remote protocol, GDB sessions start a little differently
9442 than they do when you're debugging locally.
9443 Here's an example showing how to start a debug session with a
9445 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
9446 Most programs would be written into flash (address 0) and run from there.
9449 $ arm-none-eabi-gdb example.elf
9450 (gdb) target remote localhost:3333
9451 Remote debugging using localhost:3333
9453 (gdb) monitor reset halt
9456 Loading section .vectors, size 0x100 lma 0x20000000
9457 Loading section .text, size 0x5a0 lma 0x20000100
9458 Loading section .data, size 0x18 lma 0x200006a0
9459 Start address 0x2000061c, load size 1720
9460 Transfer rate: 22 KB/sec, 573 bytes/write.
9466 You could then interrupt the GDB session to make the program break,
9467 type @command{where} to show the stack, @command{list} to show the
9468 code around the program counter, @command{step} through code,
9469 set breakpoints or watchpoints, and so on.
9471 @section Configuring GDB for OpenOCD
9473 OpenOCD supports the gdb @option{qSupported} packet, this enables information
9474 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
9475 packet size and the device's memory map.
9476 You do not need to configure the packet size by hand,
9477 and the relevant parts of the memory map should be automatically
9478 set up when you declare (NOR) flash banks.
9480 However, there are other things which GDB can't currently query.
9481 You may need to set those up by hand.
9482 As OpenOCD starts up, you will often see a line reporting
9486 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
9489 You can pass that information to GDB with these commands:
9492 set remote hardware-breakpoint-limit 6
9493 set remote hardware-watchpoint-limit 4
9496 With that particular hardware (Cortex-M3) the hardware breakpoints
9497 only work for code running from flash memory. Most other ARM systems
9498 do not have such restrictions.
9500 Rather than typing such commands interactively, you may prefer to
9501 save them in a file and have GDB execute them as it starts, perhaps
9502 using a @file{.gdbinit} in your project directory or starting GDB
9503 using @command{gdb -x filename}.
9505 @section Programming using GDB
9506 @cindex Programming using GDB
9507 @anchor{programmingusinggdb}
9509 By default the target memory map is sent to GDB. This can be disabled by
9510 the following OpenOCD configuration option:
9512 gdb_memory_map disable
9514 For this to function correctly a valid flash configuration must also be set
9515 in OpenOCD. For faster performance you should also configure a valid
9518 Informing GDB of the memory map of the target will enable GDB to protect any
9519 flash areas of the target and use hardware breakpoints by default. This means
9520 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
9521 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
9523 To view the configured memory map in GDB, use the GDB command @option{info mem}.
9524 All other unassigned addresses within GDB are treated as RAM.
9526 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
9527 This can be changed to the old behaviour by using the following GDB command
9529 set mem inaccessible-by-default off
9532 If @command{gdb_flash_program enable} is also used, GDB will be able to
9533 program any flash memory using the vFlash interface.
9535 GDB will look at the target memory map when a load command is given, if any
9536 areas to be programmed lie within the target flash area the vFlash packets
9539 If the target needs configuring before GDB programming, set target
9540 event gdb-flash-erase-start:
9542 $_TARGETNAME configure -event gdb-flash-erase-start BODY
9544 @xref{targetevents,,Target Events}, for other GDB programming related events.
9546 To verify any flash programming the GDB command @option{compare-sections}
9549 @section Using GDB as a non-intrusive memory inspector
9550 @cindex Using GDB as a non-intrusive memory inspector
9551 @anchor{gdbmeminspect}
9553 If your project controls more than a blinking LED, let's say a heavy industrial
9554 robot or an experimental nuclear reactor, stopping the controlling process
9555 just because you want to attach GDB is not a good option.
9557 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
9558 Though there is a possible setup where the target does not get stopped
9559 and GDB treats it as it were running.
9560 If the target supports background access to memory while it is running,
9561 you can use GDB in this mode to inspect memory (mainly global variables)
9562 without any intrusion of the target process.
9564 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
9565 Place following command after target configuration:
9567 $_TARGETNAME configure -event gdb-attach @{@}
9570 If any of installed flash banks does not support probe on running target,
9571 switch off gdb_memory_map:
9573 gdb_memory_map disable
9576 Ensure GDB is configured without interrupt-on-connect.
9577 Some GDB versions set it by default, some does not.
9579 set remote interrupt-on-connect off
9582 If you switched gdb_memory_map off, you may want to setup GDB memory map
9583 manually or issue @command{set mem inaccessible-by-default off}
9585 Now you can issue GDB command @command{target remote ...} and inspect memory
9586 of a running target. Do not use GDB commands @command{continue},
9587 @command{step} or @command{next} as they synchronize GDB with your target
9588 and GDB would require stopping the target to get the prompt back.
9590 Do not use this mode under an IDE like Eclipse as it caches values of
9591 previously shown varibles.
9593 @anchor{usingopenocdsmpwithgdb}
9594 @section Using OpenOCD SMP with GDB
9596 For SMP support following GDB serial protocol packet have been defined :
9598 @item j - smp status request
9599 @item J - smp set request
9602 OpenOCD implements :
9604 @item @option{jc} packet for reading core id displayed by
9605 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
9606 @option{E01} for target not smp.
9607 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
9608 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
9609 for target not smp or @option{OK} on success.
9612 Handling of this packet within GDB can be done :
9614 @item by the creation of an internal variable (i.e @option{_core}) by mean
9615 of function allocate_computed_value allowing following GDB command.
9618 #Jc01 packet is sent
9620 #jc packet is sent and result is affected in $
9623 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
9624 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
9627 # toggle0 : force display of coreid 0
9633 # toggle1 : force display of coreid 1
9642 @section RTOS Support
9643 @cindex RTOS Support
9644 @anchor{gdbrtossupport}
9646 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
9647 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
9649 @xref{Threads, Debugging Programs with Multiple Threads,
9650 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
9653 @* An example setup is below:
9656 $_TARGETNAME configure -rtos auto
9659 This will attempt to auto detect the RTOS within your application.
9661 Currently supported rtos's include:
9664 @item @option{ThreadX}
9665 @item @option{FreeRTOS}
9666 @item @option{linux}
9667 @item @option{ChibiOS}
9668 @item @option{embKernel}
9670 @item @option{uCOS-III}
9674 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
9675 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
9680 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
9681 @item ThreadX symbols
9682 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
9683 @item FreeRTOS symbols
9684 @c The following is taken from recent texinfo to provide compatibility
9685 @c with ancient versions that do not support @raggedright
9688 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
9689 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
9690 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
9691 uxCurrentNumberOfTasks, uxTopUsedPriority.
9697 @item ChibiOS symbols
9698 rlist, ch_debug, chSysInit.
9699 @item embKernel symbols
9700 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
9701 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
9703 _mqx_kernel_data, MQX_init_struct.
9704 @item uC/OS-III symbols
9705 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
9708 For most RTOS supported the above symbols will be exported by default. However for
9709 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
9711 These RTOSes may require additional OpenOCD-specific file to be linked
9712 along with the project:
9716 contrib/rtos-helpers/FreeRTOS-openocd.c
9718 contrib/rtos-helpers/uCOS-III-openocd.c
9721 @node Tcl Scripting API
9722 @chapter Tcl Scripting API
9723 @cindex Tcl Scripting API
9727 Tcl commands are stateless; e.g. the @command{telnet} command has
9728 a concept of currently active target, the Tcl API proc's take this sort
9729 of state information as an argument to each proc.
9731 There are three main types of return values: single value, name value
9732 pair list and lists.
9734 Name value pair. The proc 'foo' below returns a name/value pair
9739 > set foo(you) Oyvind
9740 > set foo(mouse) Micky
9741 > set foo(duck) Donald
9753 me Duane you Oyvind mouse Micky duck Donald
9756 Thus, to get the names of the associative array is easy:
9759 foreach { name value } [set foo] {
9760 puts "Name: $name, Value: $value"
9764 Lists returned should be relatively small. Otherwise, a range
9765 should be passed in to the proc in question.
9767 @section Internal low-level Commands
9769 By "low-level," we mean commands that a human would typically not
9772 Some low-level commands need to be prefixed with "ocd_"; e.g.
9773 @command{ocd_flash_banks}
9774 is the low-level API upon which @command{flash banks} is implemented.
9777 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9779 Read memory and return as a Tcl array for script processing
9780 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9782 Convert a Tcl array to memory locations and write the values
9783 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
9785 Return information about the flash banks
9787 @item @b{capture} <@var{command}>
9789 Run <@var{command}> and return full log output that was produced during
9790 its execution. Example:
9793 > capture "reset init"
9798 OpenOCD commands can consist of two words, e.g. "flash banks". The
9799 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
9800 called "flash_banks".
9802 @section OpenOCD specific Global Variables
9804 Real Tcl has ::tcl_platform(), and platform::identify, and many other
9805 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
9806 holds one of the following values:
9809 @item @b{cygwin} Running under Cygwin
9810 @item @b{darwin} Darwin (Mac-OS) is the underlying operating system.
9811 @item @b{freebsd} Running under FreeBSD
9812 @item @b{openbsd} Running under OpenBSD
9813 @item @b{netbsd} Running under NetBSD
9814 @item @b{linux} Linux is the underlying operating system
9815 @item @b{mingw32} Running under MingW32
9816 @item @b{winxx} Built using Microsoft Visual Studio
9817 @item @b{ecos} Running under eCos
9818 @item @b{other} Unknown, none of the above.
9821 Note: 'winxx' was chosen because today (March-2009) no distinction is made between Win32 and Win64.
9824 We should add support for a variable like Tcl variable
9825 @code{tcl_platform(platform)}, it should be called
9826 @code{jim_platform} (because it
9827 is jim, not real tcl).
9830 @section Tcl RPC server
9833 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
9834 commands and receive the results.
9836 To access it, your application needs to connect to a configured TCP port
9837 (see @command{tcl_port}). Then it can pass any string to the
9838 interpreter terminating it with @code{0x1a} and wait for the return
9839 value (it will be terminated with @code{0x1a} as well). This can be
9840 repeated as many times as desired without reopening the connection.
9842 Remember that most of the OpenOCD commands need to be prefixed with
9843 @code{ocd_} to get the results back. Sometimes you might also need the
9844 @command{capture} command.
9846 See @file{contrib/rpc_examples/} for specific client implementations.
9848 @section Tcl RPC server notifications
9849 @cindex RPC Notifications
9851 Notifications are sent asynchronously to other commands being executed over
9852 the RPC server, so the port must be polled continuously.
9854 Target event, state and reset notifications are emitted as Tcl associative arrays
9855 in the following format.
9858 type target_event event [event-name]
9859 type target_state state [state-name]
9860 type target_reset mode [reset-mode]
9863 @deffn {Command} tcl_notifications [on/off]
9864 Toggle output of target notifications to the current Tcl RPC server.
9865 Only available from the Tcl RPC server.
9870 @section Tcl RPC server trace output
9871 @cindex RPC trace output
9873 Trace data is sent asynchronously to other commands being executed over
9874 the RPC server, so the port must be polled continuously.
9876 Target trace data is emitted as a Tcl associative array in the following format.
9879 type target_trace data [trace-data-hex-encoded]
9882 @deffn {Command} tcl_trace [on/off]
9883 Toggle output of target trace data to the current Tcl RPC server.
9884 Only available from the Tcl RPC server.
9887 See an example application here:
9888 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
9897 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
9899 @cindex adaptive clocking
9902 In digital circuit design it is often referred to as ``clock
9903 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
9904 operating at some speed, your CPU target is operating at another.
9905 The two clocks are not synchronised, they are ``asynchronous''
9907 In order for the two to work together they must be synchronised
9908 well enough to work; JTAG can't go ten times faster than the CPU,
9909 for example. There are 2 basic options:
9912 Use a special "adaptive clocking" circuit to change the JTAG
9913 clock rate to match what the CPU currently supports.
9915 The JTAG clock must be fixed at some speed that's enough slower than
9916 the CPU clock that all TMS and TDI transitions can be detected.
9919 @b{Does this really matter?} For some chips and some situations, this
9920 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
9921 the CPU has no difficulty keeping up with JTAG.
9922 Startup sequences are often problematic though, as are other
9923 situations where the CPU clock rate changes (perhaps to save
9926 For example, Atmel AT91SAM chips start operation from reset with
9927 a 32kHz system clock. Boot firmware may activate the main oscillator
9928 and PLL before switching to a faster clock (perhaps that 500 MHz
9930 If you're using JTAG to debug that startup sequence, you must slow
9931 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
9932 JTAG can use a faster clock.
9934 Consider also debugging a 500MHz ARM926 hand held battery powered
9935 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
9936 clock, between keystrokes unless it has work to do. When would
9937 that 5 MHz JTAG clock be usable?
9939 @b{Solution #1 - A special circuit}
9941 In order to make use of this,
9942 your CPU, board, and JTAG adapter must all support the RTCK
9943 feature. Not all of them support this; keep reading!
9945 The RTCK ("Return TCK") signal in some ARM chips is used to help with
9946 this problem. ARM has a good description of the problem described at
9947 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
9948 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
9949 work? / how does adaptive clocking work?''.
9951 The nice thing about adaptive clocking is that ``battery powered hand
9952 held device example'' - the adaptiveness works perfectly all the
9953 time. One can set a break point or halt the system in the deep power
9954 down code, slow step out until the system speeds up.
9956 Note that adaptive clocking may also need to work at the board level,
9957 when a board-level scan chain has multiple chips.
9958 Parallel clock voting schemes are good way to implement this,
9959 both within and between chips, and can easily be implemented
9961 It's not difficult to have logic fan a module's input TCK signal out
9962 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
9963 back with the right polarity before changing the output RTCK signal.
9964 Texas Instruments makes some clock voting logic available
9965 for free (with no support) in VHDL form; see
9966 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
9968 @b{Solution #2 - Always works - but may be slower}
9970 Often this is a perfectly acceptable solution.
9972 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
9973 the target clock speed. But what that ``magic division'' is varies
9974 depending on the chips on your board.
9975 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
9976 ARM11 cores use an 8:1 division.
9977 @b{Xilinx rule of thumb} is 1/12 the clock speed.
9979 Note: most full speed FT2232 based JTAG adapters are limited to a
9980 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
9981 often support faster clock rates (and adaptive clocking).
9983 You can still debug the 'low power' situations - you just need to
9984 either use a fixed and very slow JTAG clock rate ... or else
9985 manually adjust the clock speed at every step. (Adjusting is painful
9986 and tedious, and is not always practical.)
9988 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
9989 have a special debug mode in your application that does a ``high power
9990 sleep''. If you are careful - 98% of your problems can be debugged
9993 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
9994 operation in your idle loops even if you don't otherwise change the CPU
9996 That operation gates the CPU clock, and thus the JTAG clock; which
9997 prevents JTAG access. One consequence is not being able to @command{halt}
9998 cores which are executing that @emph{wait for interrupt} operation.
10000 To set the JTAG frequency use the command:
10003 # Example: 1.234MHz
10008 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
10010 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
10011 around Windows filenames.
10024 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
10026 Make sure you have Cygwin installed, or at least a version of OpenOCD that
10027 claims to come with all the necessary DLLs. When using Cygwin, try launching
10028 OpenOCD from the Cygwin shell.
10030 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
10031 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
10032 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
10034 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
10035 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
10036 software breakpoints consume one of the two available hardware breakpoints.
10038 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
10040 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
10041 clock at the time you're programming the flash. If you've specified the crystal's
10042 frequency, make sure the PLL is disabled. If you've specified the full core speed
10043 (e.g. 60MHz), make sure the PLL is enabled.
10045 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
10046 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
10047 out while waiting for end of scan, rtck was disabled".
10049 Make sure your PC's parallel port operates in EPP mode. You might have to try several
10050 settings in your PC BIOS (ECP, EPP, and different versions of those).
10052 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
10053 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
10054 memory read caused data abort".
10056 The errors are non-fatal, and are the result of GDB trying to trace stack frames
10057 beyond the last valid frame. It might be possible to prevent this by setting up
10058 a proper "initial" stack frame, if you happen to know what exactly has to
10059 be done, feel free to add this here.
10061 @b{Simple:} In your startup code - push 8 registers of zeros onto the
10062 stack before calling main(). What GDB is doing is ``climbing'' the run
10063 time stack by reading various values on the stack using the standard
10064 call frame for the target. GDB keeps going - until one of 2 things
10065 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
10066 stackframes have been processed. By pushing zeros on the stack, GDB
10069 @b{Debugging Interrupt Service Routines} - In your ISR before you call
10070 your C code, do the same - artificially push some zeros onto the stack,
10071 remember to pop them off when the ISR is done.
10073 @b{Also note:} If you have a multi-threaded operating system, they
10074 often do not @b{in the intrest of saving memory} waste these few
10078 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
10079 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
10081 This warning doesn't indicate any serious problem, as long as you don't want to
10082 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
10083 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
10084 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
10085 independently. With this setup, it's not possible to halt the core right out of
10086 reset, everything else should work fine.
10088 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
10089 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
10090 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
10091 quit with an error message. Is there a stability issue with OpenOCD?
10093 No, this is not a stability issue concerning OpenOCD. Most users have solved
10094 this issue by simply using a self-powered USB hub, which they connect their
10095 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
10096 supply stable enough for the Amontec JTAGkey to be operated.
10098 @b{Laptops running on battery have this problem too...}
10100 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
10101 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
10102 What does that mean and what might be the reason for this?
10104 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
10105 has closed the connection to OpenOCD. This might be a GDB issue.
10107 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
10108 are described, there is a parameter for specifying the clock frequency
10109 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
10110 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
10111 specified in kilohertz. However, I do have a quartz crystal of a
10112 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
10113 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
10116 No. The clock frequency specified here must be given as an integral number.
10117 However, this clock frequency is used by the In-Application-Programming (IAP)
10118 routines of the LPC2000 family only, which seems to be very tolerant concerning
10119 the given clock frequency, so a slight difference between the specified clock
10120 frequency and the actual clock frequency will not cause any trouble.
10122 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
10124 Well, yes and no. Commands can be given in arbitrary order, yet the
10125 devices listed for the JTAG scan chain must be given in the right
10126 order (jtag newdevice), with the device closest to the TDO-Pin being
10127 listed first. In general, whenever objects of the same type exist
10128 which require an index number, then these objects must be given in the
10129 right order (jtag newtap, targets and flash banks - a target
10130 references a jtag newtap and a flash bank references a target).
10132 You can use the ``scan_chain'' command to verify and display the tap order.
10134 Also, some commands can't execute until after @command{init} has been
10135 processed. Such commands include @command{nand probe} and everything
10136 else that needs to write to controller registers, perhaps for setting
10137 up DRAM and loading it with code.
10139 @anchor{faqtaporder}
10140 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
10143 Yes; whenever you have more than one, you must declare them in
10144 the same order used by the hardware.
10146 Many newer devices have multiple JTAG TAPs. For example:
10147 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
10148 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
10149 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
10150 connected to the boundary scan TAP, which then connects to the
10151 Cortex-M3 TAP, which then connects to the TDO pin.
10153 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
10154 (2) The boundary scan TAP. If your board includes an additional JTAG
10155 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
10156 place it before or after the STM32 chip in the chain. For example:
10159 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
10160 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
10161 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
10162 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
10163 @item Xilinx TDO Pin -> OpenOCD TDO (input)
10166 The ``jtag device'' commands would thus be in the order shown below. Note:
10169 @item jtag newtap Xilinx tap -irlen ...
10170 @item jtag newtap stm32 cpu -irlen ...
10171 @item jtag newtap stm32 bs -irlen ...
10172 @item # Create the debug target and say where it is
10173 @item target create stm32.cpu -chain-position stm32.cpu ...
10177 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
10178 log file, I can see these error messages: Error: arm7_9_common.c:561
10179 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
10185 @node Tcl Crash Course
10186 @chapter Tcl Crash Course
10189 Not everyone knows Tcl - this is not intended to be a replacement for
10190 learning Tcl, the intent of this chapter is to give you some idea of
10191 how the Tcl scripts work.
10193 This chapter is written with two audiences in mind. (1) OpenOCD users
10194 who need to understand a bit more of how Jim-Tcl works so they can do
10195 something useful, and (2) those that want to add a new command to
10198 @section Tcl Rule #1
10199 There is a famous joke, it goes like this:
10201 @item Rule #1: The wife is always correct
10202 @item Rule #2: If you think otherwise, See Rule #1
10205 The Tcl equal is this:
10208 @item Rule #1: Everything is a string
10209 @item Rule #2: If you think otherwise, See Rule #1
10212 As in the famous joke, the consequences of Rule #1 are profound. Once
10213 you understand Rule #1, you will understand Tcl.
10215 @section Tcl Rule #1b
10216 There is a second pair of rules.
10218 @item Rule #1: Control flow does not exist. Only commands
10219 @* For example: the classic FOR loop or IF statement is not a control
10220 flow item, they are commands, there is no such thing as control flow
10222 @item Rule #2: If you think otherwise, See Rule #1
10223 @* Actually what happens is this: There are commands that by
10224 convention, act like control flow key words in other languages. One of
10225 those commands is the word ``for'', another command is ``if''.
10228 @section Per Rule #1 - All Results are strings
10229 Every Tcl command results in a string. The word ``result'' is used
10230 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
10231 Everything is a string}
10233 @section Tcl Quoting Operators
10234 In life of a Tcl script, there are two important periods of time, the
10235 difference is subtle.
10238 @item Evaluation Time
10241 The two key items here are how ``quoted things'' work in Tcl. Tcl has
10242 three primary quoting constructs, the [square-brackets] the
10243 @{curly-braces@} and ``double-quotes''
10245 By now you should know $VARIABLES always start with a $DOLLAR
10246 sign. BTW: To set a variable, you actually use the command ``set'', as
10247 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
10248 = 1'' statement, but without the equal sign.
10251 @item @b{[square-brackets]}
10252 @* @b{[square-brackets]} are command substitutions. It operates much
10253 like Unix Shell `back-ticks`. The result of a [square-bracket]
10254 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
10255 string}. These two statements are roughly identical:
10259 echo "The Date is: $X"
10262 puts "The Date is: $X"
10264 @item @b{``double-quoted-things''}
10265 @* @b{``double-quoted-things''} are just simply quoted
10266 text. $VARIABLES and [square-brackets] are expanded in place - the
10267 result however is exactly 1 string. @i{Remember Rule #1 - Everything
10271 puts "It is now \"[date]\", $x is in 1 hour"
10273 @item @b{@{Curly-Braces@}}
10274 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
10275 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
10276 'single-quote' operators in BASH shell scripts, with the added
10277 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
10278 nested 3 times@}@}@} NOTE: [date] is a bad example;
10279 at this writing, Jim/OpenOCD does not have a date command.
10282 @section Consequences of Rule 1/2/3/4
10284 The consequences of Rule 1 are profound.
10286 @subsection Tokenisation & Execution.
10288 Of course, whitespace, blank lines and #comment lines are handled in
10291 As a script is parsed, each (multi) line in the script file is
10292 tokenised and according to the quoting rules. After tokenisation, that
10293 line is immediately executed.
10295 Multi line statements end with one or more ``still-open''
10296 @{curly-braces@} which - eventually - closes a few lines later.
10298 @subsection Command Execution
10300 Remember earlier: There are no ``control flow''
10301 statements in Tcl. Instead there are COMMANDS that simply act like
10302 control flow operators.
10304 Commands are executed like this:
10307 @item Parse the next line into (argc) and (argv[]).
10308 @item Look up (argv[0]) in a table and call its function.
10309 @item Repeat until End Of File.
10312 It sort of works like this:
10315 ReadAndParse( &argc, &argv );
10317 cmdPtr = LookupCommand( argv[0] );
10319 (*cmdPtr->Execute)( argc, argv );
10323 When the command ``proc'' is parsed (which creates a procedure
10324 function) it gets 3 parameters on the command line. @b{1} the name of
10325 the proc (function), @b{2} the list of parameters, and @b{3} the body
10326 of the function. Not the choice of words: LIST and BODY. The PROC
10327 command stores these items in a table somewhere so it can be found by
10328 ``LookupCommand()''
10330 @subsection The FOR command
10332 The most interesting command to look at is the FOR command. In Tcl,
10333 the FOR command is normally implemented in C. Remember, FOR is a
10334 command just like any other command.
10336 When the ascii text containing the FOR command is parsed, the parser
10337 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
10341 @item The ascii text 'for'
10342 @item The start text
10343 @item The test expression
10344 @item The next text
10345 @item The body text
10348 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
10349 Remember @i{Rule #1 - Everything is a string.} The key point is this:
10350 Often many of those parameters are in @{curly-braces@} - thus the
10351 variables inside are not expanded or replaced until later.
10353 Remember that every Tcl command looks like the classic ``main( argc,
10354 argv )'' function in C. In JimTCL - they actually look like this:
10358 MyCommand( Jim_Interp *interp,
10360 Jim_Obj * const *argvs );
10363 Real Tcl is nearly identical. Although the newer versions have
10364 introduced a byte-code parser and interpreter, but at the core, it
10365 still operates in the same basic way.
10367 @subsection FOR command implementation
10369 To understand Tcl it is perhaps most helpful to see the FOR
10370 command. Remember, it is a COMMAND not a control flow structure.
10372 In Tcl there are two underlying C helper functions.
10374 Remember Rule #1 - You are a string.
10376 The @b{first} helper parses and executes commands found in an ascii
10377 string. Commands can be separated by semicolons, or newlines. While
10378 parsing, variables are expanded via the quoting rules.
10380 The @b{second} helper evaluates an ascii string as a numerical
10381 expression and returns a value.
10383 Here is an example of how the @b{FOR} command could be
10384 implemented. The pseudo code below does not show error handling.
10386 void Execute_AsciiString( void *interp, const char *string );
10388 int Evaluate_AsciiExpression( void *interp, const char *string );
10391 MyForCommand( void *interp,
10396 SetResult( interp, "WRONG number of parameters");
10400 // argv[0] = the ascii string just like C
10402 // Execute the start statement.
10403 Execute_AsciiString( interp, argv[1] );
10405 // Top of loop test
10407 i = Evaluate_AsciiExpression(interp, argv[2]);
10411 // Execute the body
10412 Execute_AsciiString( interp, argv[3] );
10414 // Execute the LOOP part
10415 Execute_AsciiString( interp, argv[4] );
10419 SetResult( interp, "" );
10424 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
10425 in the same basic way.
10427 @section OpenOCD Tcl Usage
10429 @subsection source and find commands
10430 @b{Where:} In many configuration files
10431 @* Example: @b{ source [find FILENAME] }
10432 @*Remember the parsing rules
10434 @item The @command{find} command is in square brackets,
10435 and is executed with the parameter FILENAME. It should find and return
10436 the full path to a file with that name; it uses an internal search path.
10437 The RESULT is a string, which is substituted into the command line in
10438 place of the bracketed @command{find} command.
10439 (Don't try to use a FILENAME which includes the "#" character.
10440 That character begins Tcl comments.)
10441 @item The @command{source} command is executed with the resulting filename;
10442 it reads a file and executes as a script.
10444 @subsection format command
10445 @b{Where:} Generally occurs in numerous places.
10446 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
10452 puts [format "The answer: %d" [expr $x * $y]]
10455 @item The SET command creates 2 variables, X and Y.
10456 @item The double [nested] EXPR command performs math
10457 @* The EXPR command produces numerical result as a string.
10458 @* Refer to Rule #1
10459 @item The format command is executed, producing a single string
10460 @* Refer to Rule #1.
10461 @item The PUTS command outputs the text.
10463 @subsection Body or Inlined Text
10464 @b{Where:} Various TARGET scripts.
10467 proc someproc @{@} @{
10468 ... multiple lines of stuff ...
10470 $_TARGETNAME configure -event FOO someproc
10471 #2 Good - no variables
10472 $_TARGETNAME configure -event foo "this ; that;"
10473 #3 Good Curly Braces
10474 $_TARGETNAME configure -event FOO @{
10475 puts "Time: [date]"
10477 #4 DANGER DANGER DANGER
10478 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
10481 @item The $_TARGETNAME is an OpenOCD variable convention.
10482 @*@b{$_TARGETNAME} represents the last target created, the value changes
10483 each time a new target is created. Remember the parsing rules. When
10484 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
10485 the name of the target which happens to be a TARGET (object)
10487 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
10488 @*There are 4 examples:
10490 @item The TCLBODY is a simple string that happens to be a proc name
10491 @item The TCLBODY is several simple commands separated by semicolons
10492 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
10493 @item The TCLBODY is a string with variables that get expanded.
10496 In the end, when the target event FOO occurs the TCLBODY is
10497 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
10498 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
10500 Remember the parsing rules. In case #3, @{curly-braces@} mean the
10501 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
10502 and the text is evaluated. In case #4, they are replaced before the
10503 ``Target Object Command'' is executed. This occurs at the same time
10504 $_TARGETNAME is replaced. In case #4 the date will never
10505 change. @{BTW: [date] is a bad example; at this writing,
10506 Jim/OpenOCD does not have a date command@}
10508 @subsection Global Variables
10509 @b{Where:} You might discover this when writing your own procs @* In
10510 simple terms: Inside a PROC, if you need to access a global variable
10511 you must say so. See also ``upvar''. Example:
10513 proc myproc @{ @} @{
10514 set y 0 #Local variable Y
10515 global x #Global variable X
10516 puts [format "X=%d, Y=%d" $x $y]
10519 @section Other Tcl Hacks
10520 @b{Dynamic variable creation}
10522 # Dynamically create a bunch of variables.
10523 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
10525 set vn [format "BIT%d" $x]
10529 set $vn [expr (1 << $x)]
10532 @b{Dynamic proc/command creation}
10534 # One "X" function - 5 uart functions.
10535 foreach who @{A B C D E@}
10536 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
10542 @node OpenOCD Concept Index
10543 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
10544 @comment case issue with ``Index.html'' and ``index.html''
10545 @comment Occurs when creating ``--html --no-split'' output
10546 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
10547 @unnumbered OpenOCD Concept Index
10551 @node Command and Driver Index
10552 @unnumbered Command and Driver Index