1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD Subversion Repository
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
179 @uref{svn://svn.berlios.de/openocd/trunk}
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
191 If you prefer GIT based tools, the @command{git-svn} package works too:
193 git svn clone -s svn://svn.berlios.de/openocd
195 The ``README'' file contains the instructions for building the project
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
203 @section Doxygen Developer Manual
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
216 @section OpenOCD Developer Mailing List
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
251 @section Choosing a Dongle
253 There are several things you should keep in mind when choosing a dongle.
256 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
257 Does your dongle support it? You might need a level converter.
258 @item @b{Pinout} What pinout does your target board use?
259 Does your dongle support it? You may be able to use jumper
260 wires, or an "octopus" connector, to convert pinouts.
261 @item @b{Connection} Does your computer have the USB, printer, or
262 Ethernet port needed?
263 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
266 @section Stand alone Systems
268 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
269 dongle, but a standalone box. The ZY1000 has the advantage that it does
270 not require any drivers installed on the developer PC. It also has
271 a built in web interface. It supports RTCK/RCLK or adaptive clocking
272 and has a built in relay to power cycle targets remotely.
274 @section USB FT2232 Based
276 There are many USB JTAG dongles on the market, many of them are based
277 on a chip from ``Future Technology Devices International'' (FTDI)
278 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
279 See: @url{http://www.ftdichip.com} for more information.
280 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
281 chips are starting to become available in JTAG adapters.
285 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
287 @* See: @url{http://www.amontec.com/jtagkey.shtml}
289 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
291 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
293 @* See: @url{http://www.signalyzer.com}
294 @item @b{evb_lm3s811}
295 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
296 @item @b{luminary_icdi}
297 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
298 @item @b{olimex-jtag}
299 @* See: @url{http://www.olimex.com}
301 @* See: @url{http://www.tincantools.com}
302 @item @b{turtelizer2}
304 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
305 @url{http://www.ethernut.de}
307 @* Link: @url{http://www.hitex.com/index.php?id=383}
309 @* Link @url{http://www.hitex.com/stm32-stick}
310 @item @b{axm0432_jtag}
311 @* Axiom AXM-0432 Link @url{http://www.axman.com}
313 @* Link @url{http://www.hitex.com/index.php?id=cortino}
316 @section USB JLINK based
317 There are several OEM versions of the Segger @b{JLINK} adapter. It is
318 an example of a micro controller based JTAG adapter, it uses an
319 AT91SAM764 internally.
322 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
323 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
324 @item @b{SEGGER JLINK}
325 @* Link: @url{http://www.segger.com/jlink.html}
327 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
330 @section USB RLINK based
331 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
334 @item @b{Raisonance RLink}
335 @* Link: @url{http://www.raisonance.com/products/RLink.php}
336 @item @b{STM32 Primer}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
338 @item @b{STM32 Primer2}
339 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
345 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
347 @item @b{USB - Presto}
348 @* Link: @url{http://tools.asix.net/prg_presto.htm}
350 @item @b{Versaloon-Link}
351 @* Link: @url{http://www.simonqian.com/en/Versaloon}
353 @item @b{ARM-JTAG-EW}
354 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
357 @section IBM PC Parallel Printer Port Based
359 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
360 and the MacGraigor Wiggler. There are many clones and variations of
363 Note that parallel ports are becoming much less common, so if you
364 have the choice you should probably avoid these adapters in favor
369 @item @b{Wiggler} - There are many clones of this.
370 @* Link: @url{http://www.macraigor.com/wiggler.htm}
372 @item @b{DLC5} - From XILINX - There are many clones of this
373 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
374 produced, PDF schematics are easily found and it is easy to make.
376 @item @b{Amontec - JTAG Accelerator}
377 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
380 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
383 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
384 Improved parallel-port wiggler-style JTAG adapter}
386 @item @b{Wiggler_ntrst_inverted}
387 @* Yet another variation - See the source code, src/jtag/parport.c
389 @item @b{old_amt_wiggler}
390 @* Unknown - probably not on the market today
393 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
396 @* Link: @url{http://www.amontec.com/chameleon.shtml}
402 @* ispDownload from Lattice Semiconductor
403 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
406 @* From ST Microsystems;
407 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
408 FlashLINK JTAG programing cable for PSD and uPSD}
416 @* An EP93xx based Linux machine using the GPIO pins directly.
419 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
424 @chapter About JIM-Tcl
428 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
429 This programming language provides a simple and extensible
432 All commands presented in this Guide are extensions to JIM-Tcl.
433 You can use them as simple commands, without needing to learn
434 much of anything about Tcl.
435 Alternatively, can write Tcl programs with them.
437 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
440 @item @b{JIM vs. Tcl}
441 @* JIM-TCL is a stripped down version of the well known Tcl language,
442 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
443 fewer features. JIM-Tcl is a single .C file and a single .H file and
444 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
445 4.2 MB .zip file containing 1540 files.
447 @item @b{Missing Features}
448 @* Our practice has been: Add/clone the real Tcl feature if/when
449 needed. We welcome JIM Tcl improvements, not bloat.
452 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
453 command interpreter today is a mixture of (newer)
454 JIM-Tcl commands, and (older) the orginal command interpreter.
457 @* At the OpenOCD telnet command line (or via the GDB mon command) one
458 can type a Tcl for() loop, set variables, etc.
459 Some of the commands documented in this guide are implemented
460 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
462 @item @b{Historical Note}
463 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
465 @item @b{Need a crash course in Tcl?}
466 @*@xref{Tcl Crash Course}.
471 @cindex command line options
473 @cindex directory search
475 The @option{--help} option shows:
479 --help | -h display this help
480 --version | -v display OpenOCD version
481 --file | -f use configuration file <name>
482 --search | -s dir to search for config files and scripts
483 --debug | -d set debug level <0-3>
484 --log_output | -l redirect log output to file <name>
485 --command | -c run <command>
486 --pipe | -p use pipes when talking to gdb
489 By default OpenOCD reads the file configuration file @file{openocd.cfg}
490 in the current directory. To specify a different (or multiple)
491 configuration file, you can use the ``-f'' option. For example:
494 openocd -f config1.cfg -f config2.cfg -f config3.cfg
497 OpenOCD starts by processing the configuration commands provided
498 on the command line or in @file{openocd.cfg}.
499 @xref{Configuration Stage}.
500 At the end of the configuration stage it verifies the JTAG scan
501 chain defined using those commands; your configuration should
502 ensure that this always succeeds.
503 Normally, OpenOCD then starts running as a daemon.
504 Alternatively, commands may be used to terminate the configuration
505 stage early, perform work (such as updating some flash memory),
506 and then shut down without acting as a daemon.
508 Once OpenOCD starts running as a daemon, it waits for connections from
509 clients (Telnet, GDB, Other) and processes the commands issued through
512 If you are having problems, you can enable internal debug messages via
515 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
516 @option{-c} command line switch.
518 To enable debug output (when reporting problems or working on OpenOCD
519 itself), use the @option{-d} command line switch. This sets the
520 @option{debug_level} to "3", outputting the most information,
521 including debug messages. The default setting is "2", outputting only
522 informational messages, warnings and errors. You can also change this
523 setting from within a telnet or gdb session using @command{debug_level
524 <n>} (@pxref{debug_level}).
526 You can redirect all output from the daemon to a file using the
527 @option{-l <logfile>} switch.
529 Search paths for config/script files can be added to OpenOCD by using
530 the @option{-s <search>} switch. The current directory and the OpenOCD
531 target library is in the search path by default.
533 For details on the @option{-p} option. @xref{Connecting to GDB}.
535 Note! OpenOCD will launch the GDB & telnet server even if it can not
536 establish a connection with the target. In general, it is possible for
537 the JTAG controller to be unresponsive until the target is set up
538 correctly via e.g. GDB monitor commands in a GDB init script.
540 @node OpenOCD Project Setup
541 @chapter OpenOCD Project Setup
543 To use OpenOCD with your development projects, you need to do more than
544 just connecting the JTAG adapter hardware (dongle) to your development board
545 and then starting the OpenOCD server.
546 You also need to configure that server so that it knows
547 about that adapter and board, and helps your work.
549 @section Hooking up the JTAG Adapter
551 Today's most common case is a dongle with a JTAG cable on one side
552 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
553 and a USB cable on the other.
554 Instead of USB, some cables use Ethernet;
555 older ones may use a PC parallel port, or even a serial port.
558 @item @emph{Start with power to your target board turned off},
559 and nothing connected to your JTAG adapter.
560 If you're particularly paranoid, unplug power to the board.
561 It's important to have the ground signal properly set up,
562 unless you are using a JTAG adapter which provides
563 galvanic isolation between the target board and the
566 @item @emph{Be sure it's the right kind of JTAG connector.}
567 If your dongle has a 20-pin ARM connector, you need some kind
568 of adapter (or octopus, see below) to hook it up to
569 boards using 14-pin or 10-pin connectors ... or to 20-pin
570 connectors which don't use ARM's pinout.
572 In the same vein, make sure the voltage levels are compatible.
573 Not all JTAG adapters have the level shifters needed to work
574 with 1.2 Volt boards.
576 @item @emph{Be certain the cable is properly oriented} or you might
577 damage your board. In most cases there are only two possible
578 ways to connect the cable.
579 Connect the JTAG cable from your adapter to the board.
580 Be sure it's firmly connected.
582 In the best case, the connector is keyed to physically
583 prevent you from inserting it wrong.
584 This is most often done using a slot on the board's male connector
585 housing, which must match a key on the JTAG cable's female connector.
586 If there's no housing, then you must look carefully and
587 make sure pin 1 on the cable hooks up to pin 1 on the board.
588 Ribbon cables are frequently all grey except for a wire on one
589 edge, which is red. The red wire is pin 1.
591 Sometimes dongles provide cables where one end is an ``octopus'' of
592 color coded single-wire connectors, instead of a connector block.
593 These are great when converting from one JTAG pinout to another,
594 but are tedious to set up.
595 Use these with connector pinout diagrams to help you match up the
596 adapter signals to the right board pins.
598 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
599 A USB, parallel, or serial port connector will go to the host which
600 you are using to run OpenOCD.
601 For Ethernet, consult the documentation and your network administrator.
603 For USB based JTAG adapters you have an easy sanity check at this point:
604 does the host operating system see the JTAG adapter?
606 @item @emph{Connect the adapter's power supply, if needed.}
607 This step is primarily for non-USB adapters,
608 but sometimes USB adapters need extra power.
610 @item @emph{Power up the target board.}
611 Unless you just let the magic smoke escape,
612 you're now ready to set up the OpenOCD server
613 so you can use JTAG to work with that board.
617 Talk with the OpenOCD server using
618 telnet (@code{telnet localhost 4444} on many systems) or GDB.
619 @xref{GDB and OpenOCD}.
621 @section Project Directory
623 There are many ways you can configure OpenOCD and start it up.
625 A simple way to organize them all involves keeping a
626 single directory for your work with a given board.
627 When you start OpenOCD from that directory,
628 it searches there first for configuration files, scripts,
629 and for code you upload to the target board.
630 It is also the natural place to write files,
631 such as log files and data you download from the board.
633 @section Configuration Basics
635 There are two basic ways of configuring OpenOCD, and
636 a variety of ways you can mix them.
637 Think of the difference as just being how you start the server:
640 @item Many @option{-f file} or @option{-c command} options on the command line
641 @item No options, but a @dfn{user config file}
642 in the current directory named @file{openocd.cfg}
645 Here is an example @file{openocd.cfg} file for a setup
646 using a Signalyzer FT2232-based JTAG adapter to talk to
647 a board with an Atmel AT91SAM7X256 microcontroller:
650 source [find interface/signalyzer.cfg]
652 # GDB can also flash my flash!
653 gdb_memory_map enable
654 gdb_flash_program enable
656 source [find target/sam7x256.cfg]
659 Here is the command line equivalent of that configuration:
662 openocd -f interface/signalyzer.cfg \
663 -c "gdb_memory_map enable" \
664 -c "gdb_flash_program enable" \
665 -f target/sam7x256.cfg
668 You could wrap such long command lines in shell scripts,
669 each supporting a different development task.
670 One might re-flash the board with a specific firmware version.
671 Another might set up a particular debugging or run-time environment.
674 At this writing (October 2009) the command line method has
675 problems with how it treats variables.
676 For example, after @option{-c "set VAR value"}, or doing the
677 same in a script, the variable @var{VAR} will have no value
678 that can be tested in a later script.
681 Here we will focus on the simpler solution: one user config
682 file, including basic configuration plus any TCL procedures
683 to simplify your work.
685 @section User Config Files
686 @cindex config file, user
687 @cindex user config file
688 @cindex config file, overview
690 A user configuration file ties together all the parts of a project
692 One of the following will match your situation best:
695 @item Ideally almost everything comes from configuration files
696 provided by someone else.
697 For example, OpenOCD distributes a @file{scripts} directory
698 (probably in @file{/usr/share/openocd/scripts} on Linux).
699 Board and tool vendors can provide these too, as can individual
700 user sites; the @option{-s} command line option lets you say
701 where to find these files. (@xref{Running}.)
702 The AT91SAM7X256 example above works this way.
704 Three main types of non-user configuration file each have their
705 own subdirectory in the @file{scripts} directory:
708 @item @b{interface} -- one for each kind of JTAG adapter/dongle
709 @item @b{board} -- one for each different board
710 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
713 Best case: include just two files, and they handle everything else.
714 The first is an interface config file.
715 The second is board-specific, and it sets up the JTAG TAPs and
716 their GDB targets (by deferring to some @file{target.cfg} file),
717 declares all flash memory, and leaves you nothing to do except
721 source [find interface/olimex-jtag-tiny.cfg]
722 source [find board/csb337.cfg]
725 Boards with a single microcontroller often won't need more
726 than the target config file, as in the AT91SAM7X256 example.
727 That's because there is no external memory (flash, DDR RAM), and
728 the board differences are encapsulated by application code.
730 @item You can often reuse some standard config files but
731 need to write a few new ones, probably a @file{board.cfg} file.
732 You will be using commands described later in this User's Guide,
733 and working with the guidelines in the next chapter.
735 For example, there may be configuration files for your JTAG adapter
736 and target chip, but you need a new board-specific config file
737 giving access to your particular flash chips.
738 Or you might need to write another target chip configuration file
739 for a new chip built around the Cortex M3 core.
742 When you write new configuration files, please submit
743 them for inclusion in the next OpenOCD release.
744 For example, a @file{board/newboard.cfg} file will help the
745 next users of that board, and a @file{target/newcpu.cfg}
746 will help support users of any board using that chip.
750 You may may need to write some C code.
751 It may be as simple as a supporting a new ft2232 or parport
752 based dongle; a bit more involved, like a NAND or NOR flash
753 controller driver; or a big piece of work like supporting
754 a new chip architecture.
757 Reuse the existing config files when you can.
758 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
759 You may find a board configuration that's a good example to follow.
761 When you write config files, separate the reusable parts
762 (things every user of that interface, chip, or board needs)
763 from ones specific to your environment and debugging approach.
767 For example, a @code{gdb-attach} event handler that invokes
768 the @command{reset init} command will interfere with debugging
769 early boot code, which performs some of the same actions
770 that the @code{reset-init} event handler does.
773 Likewise, the @command{arm9tdmi vector_catch} command (or
775 its siblings @command{xscale vector_catch}
776 and @command{cortex_m3 vector_catch}) can be a timesaver
777 during some debug sessions, but don't make everyone use that either.
778 Keep those kinds of debugging aids in your user config file,
779 along with messaging and tracing setup.
780 (@xref{Software Debug Messages and Tracing}.)
783 You might need to override some defaults.
784 For example, you might need to move, shrink, or back up the target's
785 work area if your application needs much SRAM.
788 TCP/IP port configuration is another example of something which
789 is environment-specific, and should only appear in
790 a user config file. @xref{TCP/IP Ports}.
793 @section Project-Specific Utilities
795 A few project-specific utility
796 routines may well speed up your work.
797 Write them, and keep them in your project's user config file.
799 For example, if you are making a boot loader work on a
800 board, it's nice to be able to debug the ``after it's
801 loaded to RAM'' parts separately from the finicky early
802 code which sets up the DDR RAM controller and clocks.
803 A script like this one, or a more GDB-aware sibling,
807 proc ramboot @{ @} @{
808 # Reset, running the target's "reset-init" scripts
809 # to initialize clocks and the DDR RAM controller.
810 # Leave the CPU halted.
813 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
814 load_image u-boot.bin 0x20000000
821 Then once that code is working you will need to make it
822 boot from NOR flash; a different utility would help.
823 Alternatively, some developers write to flash using GDB.
824 (You might use a similar script if you're working with a flash
825 based microcontroller application instead of a boot loader.)
828 proc newboot @{ @} @{
829 # Reset, leaving the CPU halted. The "reset-init" event
830 # proc gives faster access to the CPU and to NOR flash;
831 # "reset halt" would be slower.
834 # Write standard version of U-Boot into the first two
835 # sectors of NOR flash ... the standard version should
836 # do the same lowlevel init as "reset-init".
837 flash protect 0 0 1 off
838 flash erase_sector 0 0 1
839 flash write_bank 0 u-boot.bin 0x0
840 flash protect 0 0 1 on
842 # Reboot from scratch using that new boot loader.
847 You may need more complicated utility procedures when booting
849 That often involves an extra bootloader stage,
850 running from on-chip SRAM to perform DDR RAM setup so it can load
851 the main bootloader code (which won't fit into that SRAM).
853 Other helper scripts might be used to write production system images,
854 involving considerably more than just a three stage bootloader.
856 @section Target Software Changes
858 Sometimes you may want to make some small changes to the software
859 you're developing, to help make JTAG debugging work better.
860 For example, in C or assembly language code you might
861 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
862 handling issues like:
866 @item @b{ARM Wait-For-Interrupt}...
867 Many ARM chips synchronize the JTAG clock using the core clock.
868 Low power states which stop that core clock thus prevent JTAG access.
869 Idle loops in tasking environments often enter those low power states
870 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
872 You may want to @emph{disable that instruction} in source code,
873 or otherwise prevent using that state,
874 to ensure you can get JTAG access at any time.
875 For example, the OpenOCD @command{halt} command may not
876 work for an idle processor otherwise.
878 @item @b{Delay after reset}...
879 Not all chips have good support for debugger access
880 right after reset; many LPC2xxx chips have issues here.
881 Similarly, applications that reconfigure pins used for
882 JTAG access as they start will also block debugger access.
884 To work with boards like this, @emph{enable a short delay loop}
885 the first thing after reset, before "real" startup activities.
886 For example, one second's delay is usually more than enough
887 time for a JTAG debugger to attach, so that
888 early code execution can be debugged
889 or firmware can be replaced.
891 @item @b{Debug Communications Channel (DCC)}...
892 Some processors include mechanisms to send messages over JTAG.
893 Many ARM cores support these, as do some cores from other vendors.
894 (OpenOCD may be able to use this DCC internally, speeding up some
895 operations like writing to memory.)
897 Your application may want to deliver various debugging messages
898 over JTAG, by @emph{linking with a small library of code}
899 provided with OpenOCD and using the utilities there to send
900 various kinds of message.
901 @xref{Software Debug Messages and Tracing}.
905 @node Config File Guidelines
906 @chapter Config File Guidelines
908 This chapter is aimed at any user who needs to write a config file,
909 including developers and integrators of OpenOCD and any user who
910 needs to get a new board working smoothly.
911 It provides guidelines for creating those files.
913 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
916 @item @file{interface} ...
917 think JTAG Dongle. Files that configure JTAG adapters go here.
918 @item @file{board} ...
919 think Circuit Board, PWA, PCB, they go by many names. Board files
920 contain initialization items that are specific to a board. For
921 example, the SDRAM initialization sequence for the board, or the type
922 of external flash and what address it uses. Any initialization
923 sequence to enable that external flash or SDRAM should be found in the
924 board file. Boards may also contain multiple targets: two CPUs; or
925 a CPU and an FPGA or CPLD.
926 @item @file{target} ...
927 think chip. The ``target'' directory represents the JTAG TAPs
929 which OpenOCD should control, not a board. Two common types of targets
930 are ARM chips and FPGA or CPLD chips.
931 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
932 the target config file defines all of them.
935 The @file{openocd.cfg} user config
936 file may override features in any of the above files by
937 setting variables before sourcing the target file, or by adding
938 commands specific to their situation.
940 @section Interface Config Files
943 should be able to source one of these files with a command like this:
946 source [find interface/FOOBAR.cfg]
949 A preconfigured interface file should exist for every interface in use
950 today, that said, perhaps some interfaces have only been used by the
951 sole developer who created it.
953 A separate chapter gives information about how to set these up.
954 @xref{Interface - Dongle Configuration}.
955 Read the OpenOCD source code if you have a new kind of hardware interface
956 and need to provide a driver for it.
958 @section Board Config Files
959 @cindex config file, board
960 @cindex board config file
963 should be able to source one of these files with a command like this:
966 source [find board/FOOBAR.cfg]
969 The point of a board config file is to package everything
970 about a given board that user config files need to know.
971 In summary the board files should contain (if present)
974 @item One or more @command{source [target/...cfg]} statements
975 @item NOR flash configuration (@pxref{NOR Configuration})
976 @item NAND flash configuration (@pxref{NAND Configuration})
977 @item Target @code{reset} handlers for SDRAM and I/O configuration
978 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
979 @item All things that are not ``inside a chip''
982 Generic things inside target chips belong in target config files,
983 not board config files. So for example a @code{reset-init} event
984 handler should know board-specific oscillator and PLL parameters,
985 which it passes to target-specific utility code.
987 The most complex task of a board config file is creating such a
988 @code{reset-init} event handler.
989 Define those handlers last, after you verify the rest of the board
992 @subsection Communication Between Config files
994 In addition to target-specific utility code, another way that
995 board and target config files communicate is by following a
996 convention on how to use certain variables.
998 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
999 Thus the rule we follow in OpenOCD is this: Variables that begin with
1000 a leading underscore are temporary in nature, and can be modified and
1001 used at will within a target configuration file.
1003 Complex board config files can do the things like this,
1004 for a board with three chips:
1007 # Chip #1: PXA270 for network side, big endian
1008 set CHIPNAME network
1010 source [find target/pxa270.cfg]
1011 # on return: _TARGETNAME = network.cpu
1012 # other commands can refer to the "network.cpu" target.
1013 $_TARGETNAME configure .... events for this CPU..
1015 # Chip #2: PXA270 for video side, little endian
1018 source [find target/pxa270.cfg]
1019 # on return: _TARGETNAME = video.cpu
1020 # other commands can refer to the "video.cpu" target.
1021 $_TARGETNAME configure .... events for this CPU..
1023 # Chip #3: Xilinx FPGA for glue logic
1026 source [find target/spartan3.cfg]
1029 That example is oversimplified because it doesn't show any flash memory,
1030 or the @code{reset-init} event handlers to initialize external DRAM
1031 or (assuming it needs it) load a configuration into the FPGA.
1032 Such features are usually needed for low-level work with many boards,
1033 where ``low level'' implies that the board initialization software may
1034 not be working. (That's a common reason to need JTAG tools. Another
1035 is to enable working with microcontroller-based systems, which often
1036 have no debugging support except a JTAG connector.)
1038 Target config files may also export utility functions to board and user
1039 config files. Such functions should use name prefixes, to help avoid
1042 Board files could also accept input variables from user config files.
1043 For example, there might be a @code{J4_JUMPER} setting used to identify
1044 what kind of flash memory a development board is using, or how to set
1045 up other clocks and peripherals.
1047 @subsection Variable Naming Convention
1048 @cindex variable names
1050 Most boards have only one instance of a chip.
1051 However, it should be easy to create a board with more than
1052 one such chip (as shown above).
1053 Accordingly, we encourage these conventions for naming
1054 variables associated with different @file{target.cfg} files,
1055 to promote consistency and
1056 so that board files can override target defaults.
1058 Inputs to target config files include:
1061 @item @code{CHIPNAME} ...
1062 This gives a name to the overall chip, and is used as part of
1063 tap identifier dotted names.
1064 While the default is normally provided by the chip manufacturer,
1065 board files may need to distinguish between instances of a chip.
1066 @item @code{ENDIAN} ...
1067 By default @option{little} - although chips may hard-wire @option{big}.
1068 Chips that can't change endianness don't need to use this variable.
1069 @item @code{CPUTAPID} ...
1070 When OpenOCD examines the JTAG chain, it can be told verify the
1071 chips against the JTAG IDCODE register.
1072 The target file will hold one or more defaults, but sometimes the
1073 chip in a board will use a different ID (perhaps a newer revision).
1076 Outputs from target config files include:
1079 @item @code{_TARGETNAME} ...
1080 By convention, this variable is created by the target configuration
1081 script. The board configuration file may make use of this variable to
1082 configure things like a ``reset init'' script, or other things
1083 specific to that board and that target.
1084 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1085 @code{_TARGETNAME1}, ... etc.
1088 @subsection The reset-init Event Handler
1089 @cindex event, reset-init
1090 @cindex reset-init handler
1092 Board config files run in the OpenOCD configuration stage;
1093 they can't use TAPs or targets, since they haven't been
1095 This means you can't write memory or access chip registers;
1096 you can't even verify that a flash chip is present.
1097 That's done later in event handlers, of which the target @code{reset-init}
1098 handler is one of the most important.
1100 Except on microcontrollers, the basic job of @code{reset-init} event
1101 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1102 Microcontrollers rarely use boot loaders; they run right out of their
1103 on-chip flash and SRAM memory. But they may want to use one of these
1104 handlers too, if just for developer convenience.
1107 Because this is so very board-specific, and chip-specific, no examples
1109 Instead, look at the board config files distributed with OpenOCD.
1110 If you have a boot loader, its source code may also be useful.
1113 Some of this code could probably be shared between different boards.
1114 For example, setting up a DRAM controller often doesn't differ by
1115 much except the bus width (16 bits or 32?) and memory timings, so a
1116 reusable TCL procedure loaded by the @file{target.cfg} file might take
1117 those as parameters.
1118 Similarly with oscillator, PLL, and clock setup;
1119 and disabling the watchdog.
1120 Structure the code cleanly, and provide comments to help
1121 the next developer doing such work.
1122 (@emph{You might be that next person} trying to reuse init code!)
1124 The last thing normally done in a @code{reset-init} handler is probing
1125 whatever flash memory was configured. For most chips that needs to be
1126 done while the associated target is halted, either because JTAG memory
1127 access uses the CPU or to prevent conflicting CPU access.
1129 @subsection JTAG Clock Rate
1131 Before your @code{reset-init} handler has set up
1132 the PLLs and clocking, you may need to run with
1133 a low JTAG clock rate.
1135 Then you'd increase that rate after your handler has
1136 made it possible to use the faster JTAG clock.
1137 When the initial low speed is board-specific, for example
1138 because it depends on a board-specific oscillator speed, then
1139 you should probably set it up in the board config file;
1140 if it's target-specific, it belongs in the target config file.
1142 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1143 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1144 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1145 Consult chip documentation to determine the peak JTAG clock rate,
1146 which might be less than that.
1149 On most ARMs, JTAG clock detection is coupled to the core clock, so
1150 software using a @option{wait for interrupt} operation blocks JTAG access.
1151 Adaptive clocking provides a partial workaround, but a more complete
1152 solution just avoids using that instruction with JTAG debuggers.
1155 If the board supports adaptive clocking, use the @command{jtag_rclk}
1156 command, in case your board is used with JTAG adapter which
1157 also supports it. Otherwise use @command{jtag_khz}.
1158 Set the slow rate at the beginning of the reset sequence,
1159 and the faster rate as soon as the clocks are at full speed.
1161 @section Target Config Files
1162 @cindex config file, target
1163 @cindex target config file
1165 Board config files communicate with target config files using
1166 naming conventions as described above, and may source one or
1167 more target config files like this:
1170 source [find target/FOOBAR.cfg]
1173 The point of a target config file is to package everything
1174 about a given chip that board config files need to know.
1175 In summary the target files should contain
1179 @item Add TAPs to the scan chain
1180 @item Add CPU targets (includes GDB support)
1181 @item CPU/Chip/CPU-Core specific features
1185 As a rule of thumb, a target file sets up only one chip.
1186 For a microcontroller, that will often include a single TAP,
1187 which is a CPU needing a GDB target, and its on-chip flash.
1189 More complex chips may include multiple TAPs, and the target
1190 config file may need to define them all before OpenOCD
1191 can talk to the chip.
1192 For example, some phone chips have JTAG scan chains that include
1193 an ARM core for operating system use, a DSP,
1194 another ARM core embedded in an image processing engine,
1195 and other processing engines.
1197 @subsection Default Value Boiler Plate Code
1199 All target configuration files should start with code like this,
1200 letting board config files express environment-specific
1201 differences in how things should be set up.
1204 # Boards may override chip names, perhaps based on role,
1205 # but the default should match what the vendor uses
1206 if @{ [info exists CHIPNAME] @} @{
1207 set _CHIPNAME $CHIPNAME
1209 set _CHIPNAME sam7x256
1212 # ONLY use ENDIAN with targets that can change it.
1213 if @{ [info exists ENDIAN] @} @{
1219 # TAP identifiers may change as chips mature, for example with
1220 # new revision fields (the "3" here). Pick a good default; you
1221 # can pass several such identifiers to the "jtag newtap" command.
1222 if @{ [info exists CPUTAPID ] @} @{
1223 set _CPUTAPID $CPUTAPID
1225 set _CPUTAPID 0x3f0f0f0f
1228 @c but 0x3f0f0f0f is for an str73x part ...
1230 @emph{Remember:} Board config files may include multiple target
1231 config files, or the same target file multiple times
1232 (changing at least @code{CHIPNAME}).
1234 Likewise, the target configuration file should define
1235 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1236 use it later on when defining debug targets:
1239 set _TARGETNAME $_CHIPNAME.cpu
1240 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1243 @subsection Adding TAPs to the Scan Chain
1244 After the ``defaults'' are set up,
1245 add the TAPs on each chip to the JTAG scan chain.
1246 @xref{TAP Declaration}, and the naming convention
1249 In the simplest case the chip has only one TAP,
1250 probably for a CPU or FPGA.
1251 The config file for the Atmel AT91SAM7X256
1252 looks (in part) like this:
1255 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1256 -expected-id $_CPUTAPID
1259 A board with two such at91sam7 chips would be able
1260 to source such a config file twice, with different
1261 values for @code{CHIPNAME}, so
1262 it adds a different TAP each time.
1264 If there are nonzero @option{-expected-id} values,
1265 OpenOCD attempts to verify the actual tap id against those values.
1266 It will issue error messages if there is mismatch, which
1267 can help to pinpoint problems in OpenOCD configurations.
1270 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1271 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1272 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1273 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1274 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1277 There are more complex examples too, with chips that have
1278 multiple TAPs. Ones worth looking at include:
1281 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1282 plus a JRC to enable them
1283 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1284 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1285 is not currently used)
1288 @subsection Add CPU targets
1290 After adding a TAP for a CPU, you should set it up so that
1291 GDB and other commands can use it.
1292 @xref{CPU Configuration}.
1293 For the at91sam7 example above, the command can look like this;
1294 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1295 to little endian, and this chip doesn't support changing that.
1298 set _TARGETNAME $_CHIPNAME.cpu
1299 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1302 Work areas are small RAM areas associated with CPU targets.
1303 They are used by OpenOCD to speed up downloads,
1304 and to download small snippets of code to program flash chips.
1305 If the chip includes a form of ``on-chip-ram'' - and many do - define
1306 a work area if you can.
1307 Again using the at91sam7 as an example, this can look like:
1310 $_TARGETNAME configure -work-area-phys 0x00200000 \
1311 -work-area-size 0x4000 -work-area-backup 0
1314 @subsection Chip Reset Setup
1316 As a rule, you should put the @command{reset_config} command
1317 into the board file. Most things you think you know about a
1318 chip can be tweaked by the board.
1320 Some chips have specific ways the TRST and SRST signals are
1321 managed. In the unusual case that these are @emph{chip specific}
1322 and can never be changed by board wiring, they could go here.
1324 Some chips need special attention during reset handling if
1325 they're going to be used with JTAG.
1326 An example might be needing to send some commands right
1327 after the target's TAP has been reset, providing a
1328 @code{reset-deassert-post} event handler that writes a chip
1329 register to report that JTAG debugging is being done.
1331 JTAG clocking constraints often change during reset, and in
1332 some cases target config files (rather than board config files)
1333 are the right places to handle some of those issues.
1334 For example, immediately after reset most chips run using a
1335 slower clock than they will use later.
1336 That means that after reset (and potentially, as OpenOCD
1337 first starts up) they must use a slower JTAG clock rate
1338 than they will use later.
1341 @quotation Important
1342 When you are debugging code that runs right after chip
1343 reset, getting these issues right is critical.
1344 In particular, if you see intermittent failures when
1345 OpenOCD verifies the scan chain after reset,
1346 look at how you are setting up JTAG clocking.
1349 @subsection ARM Core Specific Hacks
1351 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1352 special high speed download features - enable it.
1354 If present, the MMU, the MPU and the CACHE should be disabled.
1356 Some ARM cores are equipped with trace support, which permits
1357 examination of the instruction and data bus activity. Trace
1358 activity is controlled through an ``Embedded Trace Module'' (ETM)
1359 on one of the core's scan chains. The ETM emits voluminous data
1360 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1361 If you are using an external trace port,
1362 configure it in your board config file.
1363 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1364 configure it in your target config file.
1367 etm config $_TARGETNAME 16 normal full etb
1368 etb config $_TARGETNAME $_CHIPNAME.etb
1371 @subsection Internal Flash Configuration
1373 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1375 @b{Never ever} in the ``target configuration file'' define any type of
1376 flash that is external to the chip. (For example a BOOT flash on
1377 Chip Select 0.) Such flash information goes in a board file - not
1378 the TARGET (chip) file.
1382 @item at91sam7x256 - has 256K flash YES enable it.
1383 @item str912 - has flash internal YES enable it.
1384 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1385 @item pxa270 - again - CS0 flash - it goes in the board file.
1388 @node Daemon Configuration
1389 @chapter Daemon Configuration
1390 @cindex initialization
1391 The commands here are commonly found in the openocd.cfg file and are
1392 used to specify what TCP/IP ports are used, and how GDB should be
1395 @anchor{Configuration Stage}
1396 @section Configuration Stage
1397 @cindex configuration stage
1398 @cindex config command
1400 When the OpenOCD server process starts up, it enters a
1401 @emph{configuration stage} which is the only time that
1402 certain commands, @emph{configuration commands}, may be issued.
1403 In this manual, the definition of a configuration command is
1404 presented as a @emph{Config Command}, not as a @emph{Command}
1405 which may be issued interactively.
1407 Those configuration commands include declaration of TAPs,
1409 the interface used for JTAG communication,
1410 and other basic setup.
1411 The server must leave the configuration stage before it
1412 may access or activate TAPs.
1413 After it leaves this stage, configuration commands may no
1416 The first thing OpenOCD does after leaving the configuration
1417 stage is to verify that it can talk to the scan chain
1418 (list of TAPs) which has been configured.
1419 It will warn if it doesn't find TAPs it expects to find,
1420 or finds TAPs that aren't supposed to be there.
1421 You should see no errors at this point.
1422 If you see errors, resolve them by correcting the
1423 commands you used to configure the server.
1424 Common errors include using an initial JTAG speed that's too
1425 fast, and not providing the right IDCODE values for the TAPs
1428 @deffn {Config Command} init
1429 This command terminates the configuration stage and
1430 enters the normal command mode. This can be useful to add commands to
1431 the startup scripts and commands such as resetting the target,
1432 programming flash, etc. To reset the CPU upon startup, add "init" and
1433 "reset" at the end of the config script or at the end of the OpenOCD
1434 command line using the @option{-c} command line switch.
1436 If this command does not appear in any startup/configuration file
1437 OpenOCD executes the command for you after processing all
1438 configuration files and/or command line options.
1440 @b{NOTE:} This command normally occurs at or near the end of your
1441 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1442 targets ready. For example: If your openocd.cfg file needs to
1443 read/write memory on your target, @command{init} must occur before
1444 the memory read/write commands. This includes @command{nand probe}.
1447 @anchor{TCP/IP Ports}
1448 @section TCP/IP Ports
1453 The OpenOCD server accepts remote commands in several syntaxes.
1454 Each syntax uses a different TCP/IP port, which you may specify
1455 only during configuration (before those ports are opened).
1457 For reasons including security, you may wish to prevent remote
1458 access using one or more of these ports.
1459 In such cases, just specify the relevant port number as zero.
1460 If you disable all access through TCP/IP, you will need to
1461 use the command line @option{-pipe} option.
1463 @deffn {Command} gdb_port (number)
1465 Specify or query the first port used for incoming GDB connections.
1466 The GDB port for the
1467 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1468 When not specified during the configuration stage,
1469 the port @var{number} defaults to 3333.
1470 When specified as zero, this port is not activated.
1473 @deffn {Command} tcl_port (number)
1474 Specify or query the port used for a simplified RPC
1475 connection that can be used by clients to issue TCL commands and get the
1476 output from the Tcl engine.
1477 Intended as a machine interface.
1478 When not specified during the configuration stage,
1479 the port @var{number} defaults to 6666.
1480 When specified as zero, this port is not activated.
1483 @deffn {Command} telnet_port (number)
1484 Specify or query the
1485 port on which to listen for incoming telnet connections.
1486 This port is intended for interaction with one human through TCL commands.
1487 When not specified during the configuration stage,
1488 the port @var{number} defaults to 4444.
1489 When specified as zero, this port is not activated.
1492 @anchor{GDB Configuration}
1493 @section GDB Configuration
1495 @cindex GDB configuration
1496 You can reconfigure some GDB behaviors if needed.
1497 The ones listed here are static and global.
1498 @xref{Target Configuration}, about configuring individual targets.
1499 @xref{Target Events}, about configuring target-specific event handling.
1501 @anchor{gdb_breakpoint_override}
1502 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1503 Force breakpoint type for gdb @command{break} commands.
1504 This option supports GDB GUIs which don't
1505 distinguish hard versus soft breakpoints, if the default OpenOCD and
1506 GDB behaviour is not sufficient. GDB normally uses hardware
1507 breakpoints if the memory map has been set up for flash regions.
1510 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1511 Configures what OpenOCD will do when GDB detaches from the daemon.
1512 Default behaviour is @option{resume}.
1515 @anchor{gdb_flash_program}
1516 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1517 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1518 vFlash packet is received.
1519 The default behaviour is @option{enable}.
1522 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1523 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1524 requested. GDB will then know when to set hardware breakpoints, and program flash
1525 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1526 for flash programming to work.
1527 Default behaviour is @option{enable}.
1528 @xref{gdb_flash_program}.
1531 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1532 Specifies whether data aborts cause an error to be reported
1533 by GDB memory read packets.
1534 The default behaviour is @option{disable};
1535 use @option{enable} see these errors reported.
1538 @anchor{Event Polling}
1539 @section Event Polling
1541 Hardware debuggers are parts of asynchronous systems,
1542 where significant events can happen at any time.
1543 The OpenOCD server needs to detect some of these events,
1544 so it can report them to through TCL command line
1547 Examples of such events include:
1550 @item One of the targets can stop running ... maybe it triggers
1551 a code breakpoint or data watchpoint, or halts itself.
1552 @item Messages may be sent over ``debug message'' channels ... many
1553 targets support such messages sent over JTAG,
1554 for receipt by the person debugging or tools.
1555 @item Loss of power ... some adapters can detect these events.
1556 @item Resets not issued through JTAG ... such reset sources
1557 can include button presses or other system hardware, sometimes
1558 including the target itself (perhaps through a watchdog).
1559 @item Debug instrumentation sometimes supports event triggering
1560 such as ``trace buffer full'' (so it can quickly be emptied)
1561 or other signals (to correlate with code behavior).
1564 None of those events are signaled through standard JTAG signals.
1565 However, most conventions for JTAG connectors include voltage
1566 level and system reset (SRST) signal detection.
1567 Some connectors also include instrumentation signals, which
1568 can imply events when those signals are inputs.
1570 In general, OpenOCD needs to periodically check for those events,
1571 either by looking at the status of signals on the JTAG connector
1572 or by sending synchronous ``tell me your status'' JTAG requests
1573 to the various active targets.
1574 There is a command to manage and monitor that polling,
1575 which is normally done in the background.
1577 @deffn Command poll [@option{on}|@option{off}]
1578 Poll the current target for its current state.
1579 (Also, @pxref{target curstate}.)
1580 If that target is in debug mode, architecture
1581 specific information about the current state is printed.
1582 An optional parameter
1583 allows background polling to be enabled and disabled.
1585 You could use this from the TCL command shell, or
1586 from GDB using @command{monitor poll} command.
1589 background polling: on
1590 target state: halted
1591 target halted in ARM state due to debug-request, \
1592 current mode: Supervisor
1593 cpsr: 0x800000d3 pc: 0x11081bfc
1594 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1599 @node Interface - Dongle Configuration
1600 @chapter Interface - Dongle Configuration
1601 @cindex config file, interface
1602 @cindex interface config file
1604 JTAG Adapters/Interfaces/Dongles are normally configured
1605 through commands in an interface configuration
1606 file which is sourced by your @file{openocd.cfg} file, or
1607 through a command line @option{-f interface/....cfg} option.
1610 source [find interface/olimex-jtag-tiny.cfg]
1614 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1615 A few cases are so simple that you only need to say what driver to use:
1622 Most adapters need a bit more configuration than that.
1625 @section Interface Configuration
1627 The interface command tells OpenOCD what type of JTAG dongle you are
1628 using. Depending on the type of dongle, you may need to have one or
1629 more additional commands.
1631 @deffn {Config Command} {interface} name
1632 Use the interface driver @var{name} to connect to the
1636 @deffn Command {interface_list}
1637 List the interface drivers that have been built into
1638 the running copy of OpenOCD.
1641 @deffn Command {jtag interface}
1642 Returns the name of the interface driver being used.
1645 @section Interface Drivers
1647 Each of the interface drivers listed here must be explicitly
1648 enabled when OpenOCD is configured, in order to be made
1649 available at run time.
1651 @deffn {Interface Driver} {amt_jtagaccel}
1652 Amontec Chameleon in its JTAG Accelerator configuration,
1653 connected to a PC's EPP mode parallel port.
1654 This defines some driver-specific commands:
1656 @deffn {Config Command} {parport_port} number
1657 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1658 the number of the @file{/dev/parport} device.
1661 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1662 Displays status of RTCK option.
1663 Optionally sets that option first.
1667 @deffn {Interface Driver} {arm-jtag-ew}
1668 Olimex ARM-JTAG-EW USB adapter
1669 This has one driver-specific command:
1671 @deffn Command {armjtagew_info}
1676 @deffn {Interface Driver} {at91rm9200}
1677 Supports bitbanged JTAG from the local system,
1678 presuming that system is an Atmel AT91rm9200
1679 and a specific set of GPIOs is used.
1680 @c command: at91rm9200_device NAME
1681 @c chooses among list of bit configs ... only one option
1684 @deffn {Interface Driver} {dummy}
1685 A dummy software-only driver for debugging.
1688 @deffn {Interface Driver} {ep93xx}
1689 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1692 @deffn {Interface Driver} {ft2232}
1693 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1694 These interfaces have several commands, used to configure the driver
1695 before initializing the JTAG scan chain:
1697 @deffn {Config Command} {ft2232_device_desc} description
1698 Provides the USB device description (the @emph{iProduct string})
1699 of the FTDI FT2232 device. If not
1700 specified, the FTDI default value is used. This setting is only valid
1701 if compiled with FTD2XX support.
1704 @deffn {Config Command} {ft2232_serial} serial-number
1705 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1706 in case the vendor provides unique IDs and more than one FT2232 device
1707 is connected to the host.
1708 If not specified, serial numbers are not considered.
1709 (Note that USB serial numbers can be arbitrary Unicode strings,
1710 and are not restricted to containing only decimal digits.)
1713 @deffn {Config Command} {ft2232_layout} name
1714 Each vendor's FT2232 device can use different GPIO signals
1715 to control output-enables, reset signals, and LEDs.
1716 Currently valid layout @var{name} values include:
1718 @item @b{axm0432_jtag} Axiom AXM-0432
1719 @item @b{comstick} Hitex STR9 comstick
1720 @item @b{cortino} Hitex Cortino JTAG interface
1721 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1722 either for the local Cortex-M3 (SRST only)
1723 or in a passthrough mode (neither SRST nor TRST)
1724 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1725 @item @b{flyswatter} Tin Can Tools Flyswatter
1726 @item @b{icebear} ICEbear JTAG adapter from Section 5
1727 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1728 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1729 @item @b{m5960} American Microsystems M5960
1730 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1731 @item @b{oocdlink} OOCDLink
1732 @c oocdlink ~= jtagkey_prototype_v1
1733 @item @b{sheevaplug} Marvell Sheevaplug development kit
1734 @item @b{signalyzer} Xverve Signalyzer
1735 @item @b{stm32stick} Hitex STM32 Performance Stick
1736 @item @b{turtelizer2} egnite Software turtelizer2
1737 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1741 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1742 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1743 default values are used.
1744 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1746 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1750 @deffn {Config Command} {ft2232_latency} ms
1751 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1752 ft2232_read() fails to return the expected number of bytes. This can be caused by
1753 USB communication delays and has proved hard to reproduce and debug. Setting the
1754 FT2232 latency timer to a larger value increases delays for short USB packets but it
1755 also reduces the risk of timeouts before receiving the expected number of bytes.
1756 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1759 For example, the interface config file for a
1760 Turtelizer JTAG Adapter looks something like this:
1764 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1765 ft2232_layout turtelizer2
1766 ft2232_vid_pid 0x0403 0xbdc8
1770 @deffn {Interface Driver} {gw16012}
1771 Gateworks GW16012 JTAG programmer.
1772 This has one driver-specific command:
1774 @deffn {Config Command} {parport_port} number
1775 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1776 the number of the @file{/dev/parport} device.
1780 @deffn {Interface Driver} {jlink}
1781 Segger jlink USB adapter
1782 @c command: jlink_info
1784 @c command: jlink_hw_jtag (2|3)
1785 @c sets version 2 or 3
1788 @deffn {Interface Driver} {parport}
1789 Supports PC parallel port bit-banging cables:
1790 Wigglers, PLD download cable, and more.
1791 These interfaces have several commands, used to configure the driver
1792 before initializing the JTAG scan chain:
1794 @deffn {Config Command} {parport_cable} name
1795 The layout of the parallel port cable used to connect to the target.
1796 Currently valid cable @var{name} values include:
1799 @item @b{altium} Altium Universal JTAG cable.
1800 @item @b{arm-jtag} Same as original wiggler except SRST and
1801 TRST connections reversed and TRST is also inverted.
1802 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1803 in configuration mode. This is only used to
1804 program the Chameleon itself, not a connected target.
1805 @item @b{dlc5} The Xilinx Parallel cable III.
1806 @item @b{flashlink} The ST Parallel cable.
1807 @item @b{lattice} Lattice ispDOWNLOAD Cable
1808 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1810 Amontec's Chameleon Programmer. The new version available from
1811 the website uses the original Wiggler layout ('@var{wiggler}')
1812 @item @b{triton} The parallel port adapter found on the
1813 ``Karo Triton 1 Development Board''.
1814 This is also the layout used by the HollyGates design
1815 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1816 @item @b{wiggler} The original Wiggler layout, also supported by
1817 several clones, such as the Olimex ARM-JTAG
1818 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1819 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1823 @deffn {Config Command} {parport_port} number
1824 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1825 the @file{/dev/parport} device
1827 When using PPDEV to access the parallel port, use the number of the parallel port:
1828 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1829 you may encounter a problem.
1832 @deffn {Config Command} {parport_write_on_exit} (on|off)
1833 This will configure the parallel driver to write a known
1834 cable-specific value to the parallel interface on exiting OpenOCD
1837 For example, the interface configuration file for a
1838 classic ``Wiggler'' cable might look something like this:
1843 parport_cable wiggler
1847 @deffn {Interface Driver} {presto}
1848 ASIX PRESTO USB JTAG programmer.
1849 @c command: presto_serial str
1850 @c sets serial number
1853 @deffn {Interface Driver} {rlink}
1854 Raisonance RLink USB adapter
1857 @deffn {Interface Driver} {usbprog}
1858 usbprog is a freely programmable USB adapter.
1861 @deffn {Interface Driver} {vsllink}
1862 vsllink is part of Versaloon which is a versatile USB programmer.
1865 This defines quite a few driver-specific commands,
1866 which are not currently documented here.
1870 @deffn {Interface Driver} {ZY1000}
1871 This is the Zylin ZY1000 JTAG debugger.
1874 This defines some driver-specific commands,
1875 which are not currently documented here.
1878 @deffn Command power [@option{on}|@option{off}]
1879 Turn power switch to target on/off.
1880 No arguments: print status.
1887 JTAG clock setup is part of system setup.
1888 It @emph{does not belong with interface setup} since any interface
1889 only knows a few of the constraints for the JTAG clock speed.
1890 Sometimes the JTAG speed is
1891 changed during the target initialization process: (1) slow at
1892 reset, (2) program the CPU clocks, (3) run fast.
1893 Both the "slow" and "fast" clock rates are functions of the
1894 oscillators used, the chip, the board design, and sometimes
1895 power management software that may be active.
1897 The speed used during reset, and the scan chain verification which
1898 follows reset, can be adjusted using a @code{reset-start}
1899 target event handler.
1900 It can then be reconfigured to a faster speed by a
1901 @code{reset-init} target event handler after it reprograms those
1902 CPU clocks, or manually (if something else, such as a boot loader,
1903 sets up those clocks).
1904 @xref{Target Events}.
1905 When the initial low JTAG speed is a chip characteristic, perhaps
1906 because of a required oscillator speed, provide such a handler
1907 in the target config file.
1908 When that speed is a function of a board-specific characteristic
1909 such as which speed oscillator is used, it belongs in the board
1910 config file instead.
1911 In both cases it's safest to also set the initial JTAG clock rate
1912 to that same slow speed, so that OpenOCD never starts up using a
1913 clock speed that's faster than the scan chain can support.
1917 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
1920 If your system supports adaptive clocking (RTCK), configuring
1921 JTAG to use that is probably the most robust approach.
1922 However, it introduces delays to synchronize clocks; so it
1923 may not be the fastest solution.
1925 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1926 instead of @command{jtag_khz}.
1928 @deffn {Command} jtag_khz max_speed_kHz
1929 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1930 JTAG interfaces usually support a limited number of
1931 speeds. The speed actually used won't be faster
1932 than the speed specified.
1934 Chip data sheets generally include a top JTAG clock rate.
1935 The actual rate is often a function of a CPU core clock,
1936 and is normally less than that peak rate.
1937 For example, most ARM cores accept at most one sixth of the CPU clock.
1939 Speed 0 (khz) selects RTCK method.
1941 If your system uses RTCK, you won't need to change the
1942 JTAG clocking after setup.
1943 Not all interfaces, boards, or targets support ``rtck''.
1944 If the interface device can not
1945 support it, an error is returned when you try to use RTCK.
1948 @defun jtag_rclk fallback_speed_kHz
1949 @cindex adaptive clocking
1951 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1952 If that fails (maybe the interface, board, or target doesn't
1953 support it), falls back to the specified frequency.
1955 # Fall back to 3mhz if RTCK is not supported
1960 @node Reset Configuration
1961 @chapter Reset Configuration
1962 @cindex Reset Configuration
1964 Every system configuration may require a different reset
1965 configuration. This can also be quite confusing.
1966 Resets also interact with @var{reset-init} event handlers,
1967 which do things like setting up clocks and DRAM, and
1968 JTAG clock rates. (@xref{JTAG Speed}.)
1969 They can also interact with JTAG routers.
1970 Please see the various board files for examples.
1973 To maintainers and integrators:
1974 Reset configuration touches several things at once.
1975 Normally the board configuration file
1976 should define it and assume that the JTAG adapter supports
1977 everything that's wired up to the board's JTAG connector.
1979 However, the target configuration file could also make note
1980 of something the silicon vendor has done inside the chip,
1981 which will be true for most (or all) boards using that chip.
1982 And when the JTAG adapter doesn't support everything, the
1983 user configuration file will need to override parts of
1984 the reset configuration provided by other files.
1987 @section Types of Reset
1989 There are many kinds of reset possible through JTAG, but
1990 they may not all work with a given board and adapter.
1991 That's part of why reset configuration can be error prone.
1995 @emph{System Reset} ... the @emph{SRST} hardware signal
1996 resets all chips connected to the JTAG adapter, such as processors,
1997 power management chips, and I/O controllers. Normally resets triggered
1998 with this signal behave exactly like pressing a RESET button.
2000 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2001 just the TAP controllers connected to the JTAG adapter.
2002 Such resets should not be visible to the rest of the system; resetting a
2003 device's the TAP controller just puts that controller into a known state.
2005 @emph{Emulation Reset} ... many devices can be reset through JTAG
2006 commands. These resets are often distinguishable from system
2007 resets, either explicitly (a "reset reason" register says so)
2008 or implicitly (not all parts of the chip get reset).
2010 @emph{Other Resets} ... system-on-chip devices often support
2011 several other types of reset.
2012 You may need to arrange that a watchdog timer stops
2013 while debugging, preventing a watchdog reset.
2014 There may be individual module resets.
2017 In the best case, OpenOCD can hold SRST, then reset
2018 the TAPs via TRST and send commands through JTAG to halt the
2019 CPU at the reset vector before the 1st instruction is executed.
2020 Then when it finally releases the SRST signal, the system is
2021 halted under debugger control before any code has executed.
2022 This is the behavior required to support the @command{reset halt}
2023 and @command{reset init} commands; after @command{reset init} a
2024 board-specific script might do things like setting up DRAM.
2025 (@xref{Reset Command}.)
2027 @anchor{SRST and TRST Issues}
2028 @section SRST and TRST Issues
2030 Because SRST and TRST are hardware signals, they can have a
2031 variety of system-specific constraints. Some of the most
2036 @item @emph{Signal not available} ... Some boards don't wire
2037 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2038 support such signals even if they are wired up.
2039 Use the @command{reset_config} @var{signals} options to say
2040 when either of those signals is not connected.
2041 When SRST is not available, your code might not be able to rely
2042 on controllers having been fully reset during code startup.
2043 Missing TRST is not a problem, since JTAG level resets can
2044 be triggered using with TMS signaling.
2046 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2047 adapter will connect SRST to TRST, instead of keeping them separate.
2048 Use the @command{reset_config} @var{combination} options to say
2049 when those signals aren't properly independent.
2051 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2052 delay circuit, reset supervisor, or on-chip features can extend
2053 the effect of a JTAG adapter's reset for some time after the adapter
2054 stops issuing the reset. For example, there may be chip or board
2055 requirements that all reset pulses last for at least a
2056 certain amount of time; and reset buttons commonly have
2057 hardware debouncing.
2058 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2059 commands to say when extra delays are needed.
2061 @item @emph{Drive type} ... Reset lines often have a pullup
2062 resistor, letting the JTAG interface treat them as open-drain
2063 signals. But that's not a requirement, so the adapter may need
2064 to use push/pull output drivers.
2065 Also, with weak pullups it may be advisable to drive
2066 signals to both levels (push/pull) to minimize rise times.
2067 Use the @command{reset_config} @var{trst_type} and
2068 @var{srst_type} parameters to say how to drive reset signals.
2070 @item @emph{Special initialization} ... Targets sometimes need
2071 special JTAG initialization sequences to handle chip-specific
2072 issues (not limited to errata).
2073 For example, certain JTAG commands might need to be issued while
2074 the system as a whole is in a reset state (SRST active)
2075 but the JTAG scan chain is usable (TRST inactive).
2076 (@xref{JTAG Commands}, where the @command{jtag_reset}
2077 command is presented.)
2080 There can also be other issues.
2081 Some devices don't fully conform to the JTAG specifications.
2082 Trivial system-specific differences are common, such as
2083 SRST and TRST using slightly different names.
2084 There are also vendors who distribute key JTAG documentation for
2085 their chips only to developers who have signed a Non-Disclosure
2088 Sometimes there are chip-specific extensions like a requirement to use
2089 the normally-optional TRST signal (precluding use of JTAG adapters which
2090 don't pass TRST through), or needing extra steps to complete a TAP reset.
2092 In short, SRST and especially TRST handling may be very finicky,
2093 needing to cope with both architecture and board specific constraints.
2095 @section Commands for Handling Resets
2097 @deffn {Command} jtag_nsrst_delay milliseconds
2098 How long (in milliseconds) OpenOCD should wait after deasserting
2099 nSRST (active-low system reset) before starting new JTAG operations.
2100 When a board has a reset button connected to SRST line it will
2101 probably have hardware debouncing, implying you should use this.
2104 @deffn {Command} jtag_ntrst_delay milliseconds
2105 How long (in milliseconds) OpenOCD should wait after deasserting
2106 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2109 @deffn {Command} reset_config mode_flag ...
2110 This command displays or modifies the reset configuration
2111 of your combination of JTAG board and target in target
2112 configuration scripts.
2114 Information earlier in this section describes the kind of problems
2115 the command is intended to address (@pxref{SRST and TRST Issues}).
2116 As a rule this command belongs only in board config files,
2117 describing issues like @emph{board doesn't connect TRST};
2118 or in user config files, addressing limitations derived
2119 from a particular combination of interface and board.
2120 (An unlikely example would be using a TRST-only adapter
2121 with a board that only wires up SRST.)
2123 The @var{mode_flag} options can be specified in any order, but only one
2124 of each type -- @var{signals}, @var{combination},
2127 and @var{srst_type} -- may be specified at a time.
2128 If you don't provide a new value for a given type, its previous
2129 value (perhaps the default) is unchanged.
2130 For example, this means that you don't need to say anything at all about
2131 TRST just to declare that if the JTAG adapter should want to drive SRST,
2132 it must explicitly be driven high (@option{srst_push_pull}).
2136 @var{signals} can specify which of the reset signals are connected.
2137 For example, If the JTAG interface provides SRST, but the board doesn't
2138 connect that signal properly, then OpenOCD can't use it.
2139 Possible values are @option{none} (the default), @option{trst_only},
2140 @option{srst_only} and @option{trst_and_srst}.
2143 If your board provides SRST and/or TRST through the JTAG connector,
2144 you must declare that or else those signals will not be used.
2148 The @var{combination} is an optional value specifying broken reset
2149 signal implementations.
2150 The default behaviour if no option given is @option{separate},
2151 indicating everything behaves normally.
2152 @option{srst_pulls_trst} states that the
2153 test logic is reset together with the reset of the system (e.g. Philips
2154 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2155 the system is reset together with the test logic (only hypothetical, I
2156 haven't seen hardware with such a bug, and can be worked around).
2157 @option{combined} implies both @option{srst_pulls_trst} and
2158 @option{trst_pulls_srst}.
2161 The @var{gates} tokens control flags that describe some cases where
2162 JTAG may be unvailable during reset.
2163 @option{srst_gates_jtag} (default)
2164 indicates that asserting SRST gates the
2165 JTAG clock. This means that no communication can happen on JTAG
2166 while SRST is asserted.
2167 Its converse is @option{srst_nogate}, indicating that JTAG commands
2168 can safely be issued while SRST is active.
2171 The optional @var{trst_type} and @var{srst_type} parameters allow the
2172 driver mode of each reset line to be specified. These values only affect
2173 JTAG interfaces with support for different driver modes, like the Amontec
2174 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2175 relevant signal (TRST or SRST) is not connected.
2179 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2180 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2181 Most boards connect this signal to a pulldown, so the JTAG TAPs
2182 never leave reset unless they are hooked up to a JTAG adapter.
2185 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2186 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2187 Most boards connect this signal to a pullup, and allow the
2188 signal to be pulled low by various events including system
2189 powerup and pressing a reset button.
2194 @node TAP Declaration
2195 @chapter TAP Declaration
2196 @cindex TAP declaration
2197 @cindex TAP configuration
2199 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2200 TAPs serve many roles, including:
2203 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2204 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2205 Others do it indirectly, making a CPU do it.
2206 @item @b{Program Download} Using the same CPU support GDB uses,
2207 you can initialize a DRAM controller, download code to DRAM, and then
2208 start running that code.
2209 @item @b{Boundary Scan} Most chips support boundary scan, which
2210 helps test for board assembly problems like solder bridges
2211 and missing connections
2214 OpenOCD must know about the active TAPs on your board(s).
2215 Setting up the TAPs is the core task of your configuration files.
2216 Once those TAPs are set up, you can pass their names to code
2217 which sets up CPUs and exports them as GDB targets,
2218 probes flash memory, performs low-level JTAG operations, and more.
2220 @section Scan Chains
2223 TAPs are part of a hardware @dfn{scan chain},
2224 which is daisy chain of TAPs.
2225 They also need to be added to
2226 OpenOCD's software mirror of that hardware list,
2227 giving each member a name and associating other data with it.
2228 Simple scan chains, with a single TAP, are common in
2229 systems with a single microcontroller or microprocessor.
2230 More complex chips may have several TAPs internally.
2231 Very complex scan chains might have a dozen or more TAPs:
2232 several in one chip, more in the next, and connecting
2233 to other boards with their own chips and TAPs.
2235 You can display the list with the @command{scan_chain} command.
2236 (Don't confuse this with the list displayed by the @command{targets}
2237 command, presented in the next chapter.
2238 That only displays TAPs for CPUs which are configured as
2240 Here's what the scan chain might look like for a chip more than one TAP:
2243 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2244 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2245 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2246 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2247 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2250 Unfortunately those TAPs can't always be autoconfigured,
2251 because not all devices provide good support for that.
2252 JTAG doesn't require supporting IDCODE instructions, and
2253 chips with JTAG routers may not link TAPs into the chain
2254 until they are told to do so.
2256 The configuration mechanism currently supported by OpenOCD
2257 requires explicit configuration of all TAP devices using
2258 @command{jtag newtap} commands, as detailed later in this chapter.
2259 A command like this would declare one tap and name it @code{chip1.cpu}:
2262 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2265 Each target configuration file lists the TAPs provided
2267 Board configuration files combine all the targets on a board,
2269 Note that @emph{the order in which TAPs are declared is very important.}
2270 It must match the order in the JTAG scan chain, both inside
2271 a single chip and between them.
2272 @xref{FAQ TAP Order}.
2274 For example, the ST Microsystems STR912 chip has
2275 three separate TAPs@footnote{See the ST
2276 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2277 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2278 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2279 To configure those taps, @file{target/str912.cfg}
2280 includes commands something like this:
2283 jtag newtap str912 flash ... params ...
2284 jtag newtap str912 cpu ... params ...
2285 jtag newtap str912 bs ... params ...
2288 Actual config files use a variable instead of literals like
2289 @option{str912}, to support more than one chip of each type.
2290 @xref{Config File Guidelines}.
2292 @deffn Command {jtag names}
2293 Returns the names of all current TAPs in the scan chain.
2294 Use @command{jtag cget} or @command{jtag tapisenabled}
2295 to examine attributes and state of each TAP.
2297 foreach t [jtag names] @{
2298 puts [format "TAP: %s\n" $t]
2303 @deffn Command {scan_chain}
2304 Displays the TAPs in the scan chain configuration,
2306 The set of TAPs listed by this command is fixed by
2307 exiting the OpenOCD configuration stage,
2308 but systems with a JTAG router can
2309 enable or disable TAPs dynamically.
2310 In addition to the enable/disable status, the contents of
2311 each TAP's instruction register can also change.
2314 @c FIXME! "jtag cget" should be able to return all TAP
2315 @c attributes, like "$target_name cget" does for targets.
2317 @c Probably want "jtag eventlist", and a "tap-reset" event
2318 @c (on entry to RESET state).
2323 When TAP objects are declared with @command{jtag newtap},
2324 a @dfn{dotted.name} is created for the TAP, combining the
2325 name of a module (usually a chip) and a label for the TAP.
2326 For example: @code{xilinx.tap}, @code{str912.flash},
2327 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2328 Many other commands use that dotted.name to manipulate or
2329 refer to the TAP. For example, CPU configuration uses the
2330 name, as does declaration of NAND or NOR flash banks.
2332 The components of a dotted name should follow ``C'' symbol
2333 name rules: start with an alphabetic character, then numbers
2334 and underscores are OK; while others (including dots!) are not.
2337 In older code, JTAG TAPs were numbered from 0..N.
2338 This feature is still present.
2339 However its use is highly discouraged, and
2340 should not be relied on; it will be removed by mid-2010.
2341 Update all of your scripts to use TAP names rather than numbers,
2342 by paying attention to the runtime warnings they trigger.
2343 Using TAP numbers in target configuration scripts prevents
2344 reusing those scripts on boards with multiple targets.
2347 @section TAP Declaration Commands
2349 @c shouldn't this be(come) a {Config Command}?
2350 @anchor{jtag newtap}
2351 @deffn Command {jtag newtap} chipname tapname configparams...
2352 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2353 and configured according to the various @var{configparams}.
2355 The @var{chipname} is a symbolic name for the chip.
2356 Conventionally target config files use @code{$_CHIPNAME},
2357 defaulting to the model name given by the chip vendor but
2360 @cindex TAP naming convention
2361 The @var{tapname} reflects the role of that TAP,
2362 and should follow this convention:
2365 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2366 @item @code{cpu} -- The main CPU of the chip, alternatively
2367 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2368 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2369 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2370 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2371 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2372 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2373 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2375 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2376 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2377 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2378 a JTAG TAP; that TAP should be named @code{sdma}.
2381 Every TAP requires at least the following @var{configparams}:
2384 @item @code{-irlen} @var{NUMBER}
2385 @*The length in bits of the
2386 instruction register, such as 4 or 5 bits.
2389 A TAP may also provide optional @var{configparams}:
2392 @item @code{-disable} (or @code{-enable})
2393 @*Use the @code{-disable} parameter to flag a TAP which is not
2394 linked in to the scan chain after a reset using either TRST
2395 or the JTAG state machine's @sc{reset} state.
2396 You may use @code{-enable} to highlight the default state
2397 (the TAP is linked in).
2398 @xref{Enabling and Disabling TAPs}.
2399 @item @code{-expected-id} @var{number}
2400 @*A non-zero @var{number} represents a 32-bit IDCODE
2401 which you expect to find when the scan chain is examined.
2402 These codes are not required by all JTAG devices.
2403 @emph{Repeat the option} as many times as required if more than one
2404 ID code could appear (for example, multiple versions).
2405 Specify @var{number} as zero to suppress warnings about IDCODE
2406 values that were found but not included in the list.
2407 @item @code{-ircapture} @var{NUMBER}
2408 @*The bit pattern loaded by the TAP into the JTAG shift register
2409 on entry to the @sc{ircapture} state, such as 0x01.
2410 JTAG requires the two LSBs of this value to be 01.
2411 By default, @code{-ircapture} and @code{-irmask} are set
2412 up to verify that two-bit value; but you may provide
2413 additional bits, if you know them.
2414 @item @code{-irmask} @var{NUMBER}
2415 @*A mask used with @code{-ircapture}
2416 to verify that instruction scans work correctly.
2417 Such scans are not used by OpenOCD except to verify that
2418 there seems to be no problems with JTAG scan chain operations.
2422 @section Other TAP commands
2424 @c @deffn Command {jtag arp_init-reset}
2425 @c ... more or less "toggle TRST ... and SRST too, what the heck"
2427 @deffn Command {jtag cget} dotted.name @option{-event} name
2428 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2429 At this writing this TAP attribute
2430 mechanism is used only for event handling.
2431 (It is not a direct analogue of the @code{cget}/@code{configure}
2432 mechanism for debugger targets.)
2433 See the next section for information about the available events.
2435 The @code{configure} subcommand assigns an event handler,
2436 a TCL string which is evaluated when the event is triggered.
2437 The @code{cget} subcommand returns that handler.
2445 OpenOCD includes two event mechanisms.
2446 The one presented here applies to all JTAG TAPs.
2447 The other applies to debugger targets,
2448 which are associated with certain TAPs.
2450 The TAP events currently defined are:
2453 @item @b{post-reset}
2454 @* The TAP has just completed a JTAG reset.
2455 The tap may still be in the JTAG @sc{reset} state.
2456 Handlers for these events might perform initialization sequences
2457 such as issuing TCK cycles, TMS sequences to ensure
2458 exit from the ARM SWD mode, and more.
2460 Because the scan chain has not yet been verified, handlers for these events
2461 @emph{should not issue commands which scan the JTAG IR or DR registers}
2462 of any particular target.
2463 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2465 @* The scan chain has been reset and verified.
2466 This handler may enable TAPs as needed.
2467 @item @b{tap-disable}
2468 @* The TAP needs to be disabled. This handler should
2469 implement @command{jtag tapdisable}
2470 by issuing the relevant JTAG commands.
2471 @item @b{tap-enable}
2472 @* The TAP needs to be enabled. This handler should
2473 implement @command{jtag tapenable}
2474 by issuing the relevant JTAG commands.
2477 If you need some action after each JTAG reset, which isn't actually
2478 specific to any TAP (since you can't yet trust the scan chain's
2479 contents to be accurate), you might:
2482 jtag configure CHIP.jrc -event post-reset @{
2483 echo "JTAG Reset done"
2484 ... non-scan jtag operations to be done after reset
2489 @anchor{Enabling and Disabling TAPs}
2490 @section Enabling and Disabling TAPs
2491 @cindex JTAG Route Controller
2494 In some systems, a @dfn{JTAG Route Controller} (JRC)
2495 is used to enable and/or disable specific JTAG TAPs.
2496 Many ARM based chips from Texas Instruments include
2497 an ``ICEpick'' module, which is a JRC.
2498 Such chips include DaVinci and OMAP3 processors.
2500 A given TAP may not be visible until the JRC has been
2501 told to link it into the scan chain; and if the JRC
2502 has been told to unlink that TAP, it will no longer
2504 Such routers address problems that JTAG ``bypass mode''
2508 @item The scan chain can only go as fast as its slowest TAP.
2509 @item Having many TAPs slows instruction scans, since all
2510 TAPs receive new instructions.
2511 @item TAPs in the scan chain must be powered up, which wastes
2512 power and prevents debugging some power management mechanisms.
2515 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2516 as implied by the existence of JTAG routers.
2517 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2518 does include a kind of JTAG router functionality.
2520 @c (a) currently the event handlers don't seem to be able to
2521 @c fail in a way that could lead to no-change-of-state.
2523 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2524 shown below, and is implemented using TAP event handlers.
2525 So for example, when defining a TAP for a CPU connected to
2526 a JTAG router, your @file{target.cfg} file
2527 should define TAP event handlers using
2528 code that looks something like this:
2531 jtag configure CHIP.cpu -event tap-enable @{
2532 ... jtag operations using CHIP.jrc
2534 jtag configure CHIP.cpu -event tap-disable @{
2535 ... jtag operations using CHIP.jrc
2539 Then you might want that CPU's TAP enabled almost all the time:
2542 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2545 Note how that particular setup event handler declaration
2546 uses quotes to evaluate @code{$CHIP} when the event is configured.
2547 Using brackets @{ @} would cause it to be evaluated later,
2548 at runtime, when it might have a different value.
2550 @deffn Command {jtag tapdisable} dotted.name
2551 If necessary, disables the tap
2552 by sending it a @option{tap-disable} event.
2553 Returns the string "1" if the tap
2554 specified by @var{dotted.name} is enabled,
2555 and "0" if it is disabled.
2558 @deffn Command {jtag tapenable} dotted.name
2559 If necessary, enables the tap
2560 by sending it a @option{tap-enable} event.
2561 Returns the string "1" if the tap
2562 specified by @var{dotted.name} is enabled,
2563 and "0" if it is disabled.
2566 @deffn Command {jtag tapisenabled} dotted.name
2567 Returns the string "1" if the tap
2568 specified by @var{dotted.name} is enabled,
2569 and "0" if it is disabled.
2572 Humans will find the @command{scan_chain} command more helpful
2573 for querying the state of the JTAG taps.
2577 @node CPU Configuration
2578 @chapter CPU Configuration
2581 This chapter discusses how to set up GDB debug targets for CPUs.
2582 You can also access these targets without GDB
2583 (@pxref{Architecture and Core Commands},
2584 and @ref{Target State handling}) and
2585 through various kinds of NAND and NOR flash commands.
2586 If you have multiple CPUs you can have multiple such targets.
2588 We'll start by looking at how to examine the targets you have,
2589 then look at how to add one more target and how to configure it.
2591 @section Target List
2592 @cindex target, current
2593 @cindex target, list
2595 All targets that have been set up are part of a list,
2596 where each member has a name.
2597 That name should normally be the same as the TAP name.
2598 You can display the list with the @command{targets}
2600 This display often has only one CPU; here's what it might
2601 look like with more than one:
2603 TargetName Type Endian TapName State
2604 -- ------------------ ---------- ------ ------------------ ------------
2605 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2606 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2609 One member of that list is the @dfn{current target}, which
2610 is implicitly referenced by many commands.
2611 It's the one marked with a @code{*} near the target name.
2612 In particular, memory addresses often refer to the address
2613 space seen by that current target.
2614 Commands like @command{mdw} (memory display words)
2615 and @command{flash erase_address} (erase NOR flash blocks)
2616 are examples; and there are many more.
2618 Several commands let you examine the list of targets:
2620 @deffn Command {target count}
2621 @emph{Note: target numbers are deprecated; don't use them.
2622 They will be removed shortly after August 2010, including this command.
2623 Iterate target using @command{target names}, not by counting.}
2625 Returns the number of targets, @math{N}.
2626 The highest numbered target is @math{N - 1}.
2628 set c [target count]
2629 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2630 # Assuming you have created this function
2631 print_target_details $x
2636 @deffn Command {target current}
2637 Returns the name of the current target.
2640 @deffn Command {target names}
2641 Lists the names of all current targets in the list.
2643 foreach t [target names] @{
2644 puts [format "Target: %s\n" $t]
2649 @deffn Command {target number} number
2650 @emph{Note: target numbers are deprecated; don't use them.
2651 They will be removed shortly after August 2010, including this command.}
2653 The list of targets is numbered starting at zero.
2654 This command returns the name of the target at index @var{number}.
2656 set thename [target number $x]
2657 puts [format "Target %d is: %s\n" $x $thename]
2661 @c yep, "target list" would have been better.
2662 @c plus maybe "target setdefault".
2664 @deffn Command targets [name]
2665 @emph{Note: the name of this command is plural. Other target
2666 command names are singular.}
2668 With no parameter, this command displays a table of all known
2669 targets in a user friendly form.
2671 With a parameter, this command sets the current target to
2672 the given target with the given @var{name}; this is
2673 only relevant on boards which have more than one target.
2676 @section Target CPU Types and Variants
2681 Each target has a @dfn{CPU type}, as shown in the output of
2682 the @command{targets} command. You need to specify that type
2683 when calling @command{target create}.
2684 The CPU type indicates more than just the instruction set.
2685 It also indicates how that instruction set is implemented,
2686 what kind of debug support it integrates,
2687 whether it has an MMU (and if so, what kind),
2688 what core-specific commands may be available
2689 (@pxref{Architecture and Core Commands}),
2692 For some CPU types, OpenOCD also defines @dfn{variants} which
2693 indicate differences that affect their handling.
2694 For example, a particular implementation bug might need to be
2695 worked around in some chip versions.
2697 It's easy to see what target types are supported,
2698 since there's a command to list them.
2699 However, there is currently no way to list what target variants
2700 are supported (other than by reading the OpenOCD source code).
2702 @anchor{target types}
2703 @deffn Command {target types}
2704 Lists all supported target types.
2705 At this writing, the supported CPU types and variants are:
2708 @item @code{arm11} -- this is a generation of ARMv6 cores
2709 @item @code{arm720t} -- this is an ARMv4 core
2710 @item @code{arm7tdmi} -- this is an ARMv4 core
2711 @item @code{arm920t} -- this is an ARMv5 core
2712 @item @code{arm926ejs} -- this is an ARMv5 core
2713 @item @code{arm966e} -- this is an ARMv5 core
2714 @item @code{arm9tdmi} -- this is an ARMv4 core
2715 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2716 (Support for this is preliminary and incomplete.)
2717 @item @code{cortex_a8} -- this is an ARMv7 core
2718 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2719 compact Thumb2 instruction set. It supports one variant:
2721 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2722 This will cause OpenOCD to use a software reset rather than asserting
2723 SRST, to avoid a issue with clearing the debug registers.
2724 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2725 be detected and the normal reset behaviour used.
2727 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2728 @item @code{feroceon} -- resembles arm926
2729 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2731 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2732 provide a functional SRST line on the EJTAG connector. This causes
2733 OpenOCD to instead use an EJTAG software reset command to reset the
2735 You still need to enable @option{srst} on the @command{reset_config}
2736 command to enable OpenOCD hardware reset functionality.
2738 @item @code{xscale} -- this is actually an architecture,
2739 not a CPU type. It is based on the ARMv5 architecture.
2740 There are several variants defined:
2742 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2743 @code{pxa27x} ... instruction register length is 7 bits
2744 @item @code{pxa250}, @code{pxa255},
2745 @code{pxa26x} ... instruction register length is 5 bits
2750 To avoid being confused by the variety of ARM based cores, remember
2751 this key point: @emph{ARM is a technology licencing company}.
2752 (See: @url{http://www.arm.com}.)
2753 The CPU name used by OpenOCD will reflect the CPU design that was
2754 licenced, not a vendor brand which incorporates that design.
2755 Name prefixes like arm7, arm9, arm11, and cortex
2756 reflect design generations;
2757 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2758 reflect an architecture version implemented by a CPU design.
2760 @anchor{Target Configuration}
2761 @section Target Configuration
2763 Before creating a ``target'', you must have added its TAP to the scan chain.
2764 When you've added that TAP, you will have a @code{dotted.name}
2765 which is used to set up the CPU support.
2766 The chip-specific configuration file will normally configure its CPU(s)
2767 right after it adds all of the chip's TAPs to the scan chain.
2769 Although you can set up a target in one step, it's often clearer if you
2770 use shorter commands and do it in two steps: create it, then configure
2772 All operations on the target after it's created will use a new
2773 command, created as part of target creation.
2775 The two main things to configure after target creation are
2776 a work area, which usually has target-specific defaults even
2777 if the board setup code overrides them later;
2778 and event handlers (@pxref{Target Events}), which tend
2779 to be much more board-specific.
2780 The key steps you use might look something like this
2783 target create MyTarget cortex_m3 -chain-position mychip.cpu
2784 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2785 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2786 $MyTarget configure -event reset-init @{ myboard_reinit @}
2789 You should specify a working area if you can; typically it uses some
2791 Such a working area can speed up many things, including bulk
2792 writes to target memory;
2793 flash operations like checking to see if memory needs to be erased;
2794 GDB memory checksumming;
2798 On more complex chips, the work area can become
2799 inaccessible when application code
2800 (such as an operating system)
2801 enables or disables the MMU.
2802 For example, the particular MMU context used to acess the virtual
2803 address will probably matter ... and that context might not have
2804 easy access to other addresses needed.
2805 At this writing, OpenOCD doesn't have much MMU intelligence.
2808 It's often very useful to define a @code{reset-init} event handler.
2809 For systems that are normally used with a boot loader,
2810 common tasks include updating clocks and initializing memory
2812 That may be needed to let you write the boot loader into flash,
2813 in order to ``de-brick'' your board; or to load programs into
2814 external DDR memory without having run the boot loader.
2816 @deffn Command {target create} target_name type configparams...
2817 This command creates a GDB debug target that refers to a specific JTAG tap.
2818 It enters that target into a list, and creates a new
2819 command (@command{@var{target_name}}) which is used for various
2820 purposes including additional configuration.
2823 @item @var{target_name} ... is the name of the debug target.
2824 By convention this should be the same as the @emph{dotted.name}
2825 of the TAP associated with this target, which must be specified here
2826 using the @code{-chain-position @var{dotted.name}} configparam.
2828 This name is also used to create the target object command,
2829 referred to here as @command{$target_name},
2830 and in other places the target needs to be identified.
2831 @item @var{type} ... specifies the target type. @xref{target types}.
2832 @item @var{configparams} ... all parameters accepted by
2833 @command{$target_name configure} are permitted.
2834 If the target is big-endian, set it here with @code{-endian big}.
2835 If the variant matters, set it here with @code{-variant}.
2837 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2841 @deffn Command {$target_name configure} configparams...
2842 The options accepted by this command may also be
2843 specified as parameters to @command{target create}.
2844 Their values can later be queried one at a time by
2845 using the @command{$target_name cget} command.
2847 @emph{Warning:} changing some of these after setup is dangerous.
2848 For example, moving a target from one TAP to another;
2849 and changing its endianness or variant.
2853 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2854 used to access this target.
2856 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2857 whether the CPU uses big or little endian conventions
2859 @item @code{-event} @var{event_name} @var{event_body} --
2860 @xref{Target Events}.
2861 Note that this updates a list of named event handlers.
2862 Calling this twice with two different event names assigns
2863 two different handlers, but calling it twice with the
2864 same event name assigns only one handler.
2866 @item @code{-variant} @var{name} -- specifies a variant of the target,
2867 which OpenOCD needs to know about.
2869 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2870 whether the work area gets backed up; by default,
2871 @emph{it is not backed up.}
2872 When possible, use a working_area that doesn't need to be backed up,
2873 since performing a backup slows down operations.
2874 For example, the beginning of an SRAM block is likely to
2875 be used by most build systems, but the end is often unused.
2877 @item @code{-work-area-size} @var{size} -- specify/set the work area
2879 @item @code{-work-area-phys} @var{address} -- set the work area
2880 base @var{address} to be used when no MMU is active.
2882 @item @code{-work-area-virt} @var{address} -- set the work area
2883 base @var{address} to be used when an MMU is active.
2888 @section Other $target_name Commands
2889 @cindex object command
2891 The Tcl/Tk language has the concept of object commands,
2892 and OpenOCD adopts that same model for targets.
2894 A good Tk example is a on screen button.
2895 Once a button is created a button
2896 has a name (a path in Tk terms) and that name is useable as a first
2897 class command. For example in Tk, one can create a button and later
2898 configure it like this:
2902 button .foobar -background red -command @{ foo @}
2904 .foobar configure -foreground blue
2906 set x [.foobar cget -background]
2908 puts [format "The button is %s" $x]
2911 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2912 button, and its object commands are invoked the same way.
2915 str912.cpu mww 0x1234 0x42
2916 omap3530.cpu mww 0x5555 123
2919 The commands supported by OpenOCD target objects are:
2921 @deffn Command {$target_name arp_examine}
2922 @deffnx Command {$target_name arp_halt}
2923 @deffnx Command {$target_name arp_poll}
2924 @deffnx Command {$target_name arp_reset}
2925 @deffnx Command {$target_name arp_waitstate}
2926 Internal OpenOCD scripts (most notably @file{startup.tcl})
2927 use these to deal with specific reset cases.
2928 They are not otherwise documented here.
2931 @deffn Command {$target_name array2mem} arrayname width address count
2932 @deffnx Command {$target_name mem2array} arrayname width address count
2933 These provide an efficient script-oriented interface to memory.
2934 The @code{array2mem} primitive writes bytes, halfwords, or words;
2935 while @code{mem2array} reads them.
2936 In both cases, the TCL side uses an array, and
2937 the target side uses raw memory.
2939 The efficiency comes from enabling the use of
2940 bulk JTAG data transfer operations.
2941 The script orientation comes from working with data
2942 values that are packaged for use by TCL scripts;
2943 @command{mdw} type primitives only print data they retrieve,
2944 and neither store nor return those values.
2947 @item @var{arrayname} ... is the name of an array variable
2948 @item @var{width} ... is 8/16/32 - indicating the memory access size
2949 @item @var{address} ... is the target memory address
2950 @item @var{count} ... is the number of elements to process
2954 @deffn Command {$target_name cget} queryparm
2955 Each configuration parameter accepted by
2956 @command{$target_name configure}
2957 can be individually queried, to return its current value.
2958 The @var{queryparm} is a parameter name
2959 accepted by that command, such as @code{-work-area-phys}.
2960 There are a few special cases:
2963 @item @code{-event} @var{event_name} -- returns the handler for the
2964 event named @var{event_name}.
2965 This is a special case because setting a handler requires
2967 @item @code{-type} -- returns the target type.
2968 This is a special case because this is set using
2969 @command{target create} and can't be changed
2970 using @command{$target_name configure}.
2973 For example, if you wanted to summarize information about
2974 all the targets you might use something like this:
2977 foreach name [target names] @{
2978 set y [$name cget -endian]
2979 set z [$name cget -type]
2980 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2986 @anchor{target curstate}
2987 @deffn Command {$target_name curstate}
2988 Displays the current target state:
2989 @code{debug-running},
2992 @code{running}, or @code{unknown}.
2993 (Also, @pxref{Event Polling}.)
2996 @deffn Command {$target_name eventlist}
2997 Displays a table listing all event handlers
2998 currently associated with this target.
2999 @xref{Target Events}.
3002 @deffn Command {$target_name invoke-event} event_name
3003 Invokes the handler for the event named @var{event_name}.
3004 (This is primarily intended for use by OpenOCD framework
3005 code, for example by the reset code in @file{startup.tcl}.)
3008 @deffn Command {$target_name mdw} addr [count]
3009 @deffnx Command {$target_name mdh} addr [count]
3010 @deffnx Command {$target_name mdb} addr [count]
3011 Display contents of address @var{addr}, as
3012 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3013 or 8-bit bytes (@command{mdb}).
3014 If @var{count} is specified, displays that many units.
3015 (If you want to manipulate the data instead of displaying it,
3016 see the @code{mem2array} primitives.)
3019 @deffn Command {$target_name mww} addr word
3020 @deffnx Command {$target_name mwh} addr halfword
3021 @deffnx Command {$target_name mwb} addr byte
3022 Writes the specified @var{word} (32 bits),
3023 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3024 at the specified address @var{addr}.
3027 @anchor{Target Events}
3028 @section Target Events
3029 @cindex target events
3031 At various times, certain things can happen, or you want them to happen.
3034 @item What should happen when GDB connects? Should your target reset?
3035 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3036 @item During reset, do you need to write to certain memory locations
3037 to set up system clocks or
3038 to reconfigure the SDRAM?
3041 All of the above items can be addressed by target event handlers.
3042 These are set up by @command{$target_name configure -event} or
3043 @command{target create ... -event}.
3045 The programmer's model matches the @code{-command} option used in Tcl/Tk
3046 buttons and events. The two examples below act the same, but one creates
3047 and invokes a small procedure while the other inlines it.
3050 proc my_attach_proc @{ @} @{
3054 mychip.cpu configure -event gdb-attach my_attach_proc
3055 mychip.cpu configure -event gdb-attach @{
3061 The following target events are defined:
3064 @item @b{debug-halted}
3065 @* The target has halted for debug reasons (i.e.: breakpoint)
3066 @item @b{debug-resumed}
3067 @* The target has resumed (i.e.: gdb said run)
3068 @item @b{early-halted}
3069 @* Occurs early in the halt process
3071 @item @b{examine-end}
3072 @* Currently not used (goal: when JTAG examine completes)
3073 @item @b{examine-start}
3074 @* Currently not used (goal: when JTAG examine starts)
3076 @item @b{gdb-attach}
3077 @* When GDB connects
3078 @item @b{gdb-detach}
3079 @* When GDB disconnects
3081 @* When the target has halted and GDB is not doing anything (see early halt)
3082 @item @b{gdb-flash-erase-start}
3083 @* Before the GDB flash process tries to erase the flash
3084 @item @b{gdb-flash-erase-end}
3085 @* After the GDB flash process has finished erasing the flash
3086 @item @b{gdb-flash-write-start}
3087 @* Before GDB writes to the flash
3088 @item @b{gdb-flash-write-end}
3089 @* After GDB writes to the flash
3091 @* Before the target steps, gdb is trying to start/resume the target
3093 @* The target has halted
3095 @item @b{old-gdb_program_config}
3096 @* DO NOT USE THIS: Used internally
3097 @item @b{old-pre_resume}
3098 @* DO NOT USE THIS: Used internally
3100 @item @b{reset-assert-pre}
3101 @* Issued as part of @command{reset} processing
3102 after SRST and/or TRST were activated and deactivated,
3103 but before SRST alone is re-asserted on the tap.
3104 @item @b{reset-assert-post}
3105 @* Issued as part of @command{reset} processing
3106 when SRST is asserted on the tap.
3107 @item @b{reset-deassert-pre}
3108 @* Issued as part of @command{reset} processing
3109 when SRST is about to be released on the tap.
3110 @item @b{reset-deassert-post}
3111 @* Issued as part of @command{reset} processing
3112 when SRST has been released on the tap.
3114 @* Issued as the final step in @command{reset} processing.
3116 @item @b{reset-halt-post}
3117 @* Currently not used
3118 @item @b{reset-halt-pre}
3119 @* Currently not used
3121 @item @b{reset-init}
3122 @* Used by @b{reset init} command for board-specific initialization.
3123 This event fires after @emph{reset-deassert-post}.
3125 This is where you would configure PLLs and clocking, set up DRAM so
3126 you can download programs that don't fit in on-chip SRAM, set up pin
3127 multiplexing, and so on.
3128 (You may be able to switch to a fast JTAG clock rate here, after
3129 the target clocks are fully set up.)
3130 @item @b{reset-start}
3131 @* Issued as part of @command{reset} processing
3132 before either SRST or TRST are activated.
3134 This is the most robust place to switch to a low JTAG clock rate, if
3135 SRST disables PLLs needed to use a fast clock.
3137 @item @b{reset-wait-pos}
3138 @* Currently not used
3139 @item @b{reset-wait-pre}
3140 @* Currently not used
3142 @item @b{resume-start}
3143 @* Before any target is resumed
3144 @item @b{resume-end}
3145 @* After all targets have resumed
3149 @* Target has resumed
3153 @node Flash Commands
3154 @chapter Flash Commands
3156 OpenOCD has different commands for NOR and NAND flash;
3157 the ``flash'' command works with NOR flash, while
3158 the ``nand'' command works with NAND flash.
3159 This partially reflects different hardware technologies:
3160 NOR flash usually supports direct CPU instruction and data bus access,
3161 while data from a NAND flash must be copied to memory before it can be
3162 used. (SPI flash must also be copied to memory before use.)
3163 However, the documentation also uses ``flash'' as a generic term;
3164 for example, ``Put flash configuration in board-specific files''.
3168 @item Configure via the command @command{flash bank}
3169 @* Do this in a board-specific configuration file,
3170 passing parameters as needed by the driver.
3171 @item Operate on the flash via @command{flash subcommand}
3172 @* Often commands to manipulate the flash are typed by a human, or run
3173 via a script in some automated way. Common tasks include writing a
3174 boot loader, operating system, or other data.
3176 @* Flashing via GDB requires the flash be configured via ``flash
3177 bank'', and the GDB flash features be enabled.
3178 @xref{GDB Configuration}.
3181 Many CPUs have the ablity to ``boot'' from the first flash bank.
3182 This means that misprogramming that bank can ``brick'' a system,
3183 so that it can't boot.
3184 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3185 board by (re)installing working boot firmware.
3187 @anchor{NOR Configuration}
3188 @section Flash Configuration Commands
3189 @cindex flash configuration
3191 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3192 Configures a flash bank which provides persistent storage
3193 for addresses from @math{base} to @math{base + size - 1}.
3194 These banks will often be visible to GDB through the target's memory map.
3195 In some cases, configuring a flash bank will activate extra commands;
3196 see the driver-specific documentation.
3199 @item @var{driver} ... identifies the controller driver
3200 associated with the flash bank being declared.
3201 This is usually @code{cfi} for external flash, or else
3202 the name of a microcontroller with embedded flash memory.
3203 @xref{Flash Driver List}.
3204 @item @var{base} ... Base address of the flash chip.
3205 @item @var{size} ... Size of the chip, in bytes.
3206 For some drivers, this value is detected from the hardware.
3207 @item @var{chip_width} ... Width of the flash chip, in bytes;
3208 ignored for most microcontroller drivers.
3209 @item @var{bus_width} ... Width of the data bus used to access the
3210 chip, in bytes; ignored for most microcontroller drivers.
3211 @item @var{target} ... Names the target used to issue
3212 commands to the flash controller.
3213 @comment Actually, it's currently a controller-specific parameter...
3214 @item @var{driver_options} ... drivers may support, or require,
3215 additional parameters. See the driver-specific documentation
3216 for more information.
3219 This command is not available after OpenOCD initialization has completed.
3220 Use it in board specific configuration files, not interactively.
3224 @comment the REAL name for this command is "ocd_flash_banks"
3225 @comment less confusing would be: "flash list" (like "nand list")
3226 @deffn Command {flash banks}
3227 Prints a one-line summary of each device declared
3228 using @command{flash bank}, numbered from zero.
3229 Note that this is the @emph{plural} form;
3230 the @emph{singular} form is a very different command.
3233 @deffn Command {flash probe} num
3234 Identify the flash, or validate the parameters of the configured flash. Operation
3235 depends on the flash type.
3236 The @var{num} parameter is a value shown by @command{flash banks}.
3237 Most flash commands will implicitly @emph{autoprobe} the bank;
3238 flash drivers can distinguish between probing and autoprobing,
3239 but most don't bother.
3242 @section Erasing, Reading, Writing to Flash
3243 @cindex flash erasing
3244 @cindex flash reading
3245 @cindex flash writing
3246 @cindex flash programming
3248 One feature distinguishing NOR flash from NAND or serial flash technologies
3249 is that for read access, it acts exactly like any other addressible memory.
3250 This means you can use normal memory read commands like @command{mdw} or
3251 @command{dump_image} with it, with no special @command{flash} subcommands.
3252 @xref{Memory access}, and @ref{Image access}.
3254 Write access works differently. Flash memory normally needs to be erased
3255 before it's written. Erasing a sector turns all of its bits to ones, and
3256 writing can turn ones into zeroes. This is why there are special commands
3257 for interactive erasing and writing, and why GDB needs to know which parts
3258 of the address space hold NOR flash memory.
3261 Most of these erase and write commands leverage the fact that NOR flash
3262 chips consume target address space. They implicitly refer to the current
3263 JTAG target, and map from an address in that target's address space
3264 back to a flash bank.
3265 @comment In May 2009, those mappings may fail if any bank associated
3266 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3267 A few commands use abstract addressing based on bank and sector numbers,
3268 and don't depend on searching the current target and its address space.
3269 Avoid confusing the two command models.
3272 Some flash chips implement software protection against accidental writes,
3273 since such buggy writes could in some cases ``brick'' a system.
3274 For such systems, erasing and writing may require sector protection to be
3276 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3277 and AT91SAM7 on-chip flash.
3278 @xref{flash protect}.
3280 @anchor{flash erase_sector}
3281 @deffn Command {flash erase_sector} num first last
3282 Erase sectors in bank @var{num}, starting at sector @var{first}
3283 up to and including @var{last}.
3284 Sector numbering starts at 0.
3285 Providing a @var{last} sector of @option{last}
3286 specifies "to the end of the flash bank".
3287 The @var{num} parameter is a value shown by @command{flash banks}.
3290 @deffn Command {flash erase_address} address length
3291 Erase sectors starting at @var{address} for @var{length} bytes.
3292 The flash bank to use is inferred from the @var{address}, and
3293 the specified length must stay within that bank.
3294 As a special case, when @var{length} is zero and @var{address} is
3295 the start of the bank, the whole flash is erased.
3298 @deffn Command {flash fillw} address word length
3299 @deffnx Command {flash fillh} address halfword length
3300 @deffnx Command {flash fillb} address byte length
3301 Fills flash memory with the specified @var{word} (32 bits),
3302 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3303 starting at @var{address} and continuing
3304 for @var{length} units (word/halfword/byte).
3305 No erasure is done before writing; when needed, that must be done
3306 before issuing this command.
3307 Writes are done in blocks of up to 1024 bytes, and each write is
3308 verified by reading back the data and comparing it to what was written.
3309 The flash bank to use is inferred from the @var{address} of
3310 each block, and the specified length must stay within that bank.
3312 @comment no current checks for errors if fill blocks touch multiple banks!
3314 @anchor{flash write_bank}
3315 @deffn Command {flash write_bank} num filename offset
3316 Write the binary @file{filename} to flash bank @var{num},
3317 starting at @var{offset} bytes from the beginning of the bank.
3318 The @var{num} parameter is a value shown by @command{flash banks}.
3321 @anchor{flash write_image}
3322 @deffn Command {flash write_image} [erase] filename [offset] [type]
3323 Write the image @file{filename} to the current target's flash bank(s).
3324 A relocation @var{offset} may be specified, in which case it is added
3325 to the base address for each section in the image.
3326 The file [@var{type}] can be specified
3327 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3328 @option{elf} (ELF file), @option{s19} (Motorola s19).
3329 @option{mem}, or @option{builder}.
3330 The relevant flash sectors will be erased prior to programming
3331 if the @option{erase} parameter is given.
3332 The flash bank to use is inferred from the @var{address} of
3336 @section Other Flash commands
3337 @cindex flash protection
3339 @deffn Command {flash erase_check} num
3340 Check erase state of sectors in flash bank @var{num},
3341 and display that status.
3342 The @var{num} parameter is a value shown by @command{flash banks}.
3343 This is the only operation that
3344 updates the erase state information displayed by @option{flash info}. That means you have
3345 to issue a @command{flash erase_check} command after erasing or programming the device
3346 to get updated information.
3347 (Code execution may have invalidated any state records kept by OpenOCD.)
3350 @deffn Command {flash info} num
3351 Print info about flash bank @var{num}
3352 The @var{num} parameter is a value shown by @command{flash banks}.
3353 The information includes per-sector protect status.
3356 @anchor{flash protect}
3357 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3358 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3359 in flash bank @var{num}, starting at sector @var{first}
3360 and continuing up to and including @var{last}.
3361 Providing a @var{last} sector of @option{last}
3362 specifies "to the end of the flash bank".
3363 The @var{num} parameter is a value shown by @command{flash banks}.
3366 @deffn Command {flash protect_check} num
3367 Check protection state of sectors in flash bank @var{num}.
3368 The @var{num} parameter is a value shown by @command{flash banks}.
3369 @comment @option{flash erase_sector} using the same syntax.
3372 @anchor{Flash Driver List}
3373 @section Flash Drivers, Options, and Commands
3374 As noted above, the @command{flash bank} command requires a driver name,
3375 and allows driver-specific options and behaviors.
3376 Some drivers also activate driver-specific commands.
3378 @subsection External Flash
3380 @deffn {Flash Driver} cfi
3381 @cindex Common Flash Interface
3383 The ``Common Flash Interface'' (CFI) is the main standard for
3384 external NOR flash chips, each of which connects to a
3385 specific external chip select on the CPU.
3386 Frequently the first such chip is used to boot the system.
3387 Your board's @code{reset-init} handler might need to
3388 configure additional chip selects using other commands (like: @command{mww} to
3389 configure a bus and its timings) , or
3390 perhaps configure a GPIO pin that controls the ``write protect'' pin
3392 The CFI driver can use a target-specific working area to significantly
3395 The CFI driver can accept the following optional parameters, in any order:
3398 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3399 like AM29LV010 and similar types.
3400 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3403 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3404 wide on a sixteen bit bus:
3407 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3408 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3410 @c "cfi part_id" disabled
3413 @subsection Internal Flash (Microcontrollers)
3415 @deffn {Flash Driver} aduc702x
3416 The ADUC702x analog microcontrollers from Analog Devices
3417 include internal flash and use ARM7TDMI cores.
3418 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3419 The setup command only requires the @var{target} argument
3420 since all devices in this family have the same memory layout.
3423 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3427 @deffn {Flash Driver} at91sam3
3429 All members of the AT91SAM3 microcontroller family from
3430 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3431 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3432 that the driver was orginaly developed and tested using the
3433 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3434 the family was cribbed from the data sheet. @emph{Note to future
3435 readers/updaters: Please remove this worrysome comment after other
3436 chips are confirmed.}
3438 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3439 have one flash bank. In all cases the flash banks are at
3440 the following fixed locations:
3443 # Flash bank 0 - all chips
3444 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3445 # Flash bank 1 - only 256K chips
3446 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3449 Internally, the AT91SAM3 flash memory is organized as follows.
3450 Unlike the AT91SAM7 chips, these are not used as parameters
3451 to the @command{flash bank} command:
3454 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3455 @item @emph{Bank Size:} 128K/64K Per flash bank
3456 @item @emph{Sectors:} 16 or 8 per bank
3457 @item @emph{SectorSize:} 8K Per Sector
3458 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3461 The AT91SAM3 driver adds some additional commands:
3463 @deffn Command {at91sam3 gpnvm}
3464 @deffnx Command {at91sam3 gpnvm clear} number
3465 @deffnx Command {at91sam3 gpnvm set} number
3466 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3467 With no parameters, @command{show} or @command{show all},
3468 shows the status of all GPNVM bits.
3469 With @command{show} @var{number}, displays that bit.
3471 With @command{set} @var{number} or @command{clear} @var{number},
3472 modifies that GPNVM bit.
3475 @deffn Command {at91sam3 info}
3476 This command attempts to display information about the AT91SAM3
3477 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3478 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3479 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3480 various clock configuration registers and attempts to display how it
3481 believes the chip is configured. By default, the SLOWCLK is assumed to
3482 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3485 @deffn Command {at91sam3 slowclk} [value]
3486 This command shows/sets the slow clock frequency used in the
3487 @command{at91sam3 info} command calculations above.
3491 @deffn {Flash Driver} at91sam7
3492 All members of the AT91SAM7 microcontroller family from Atmel include
3493 internal flash and use ARM7TDMI cores. The driver automatically
3494 recognizes a number of these chips using the chip identification
3495 register, and autoconfigures itself.
3498 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3501 For chips which are not recognized by the controller driver, you must
3502 provide additional parameters in the following order:
3505 @item @var{chip_model} ... label used with @command{flash info}
3507 @item @var{sectors_per_bank}
3508 @item @var{pages_per_sector}
3509 @item @var{pages_size}
3510 @item @var{num_nvm_bits}
3511 @item @var{freq_khz} ... required if an external clock is provided,
3512 optional (but recommended) when the oscillator frequency is known
3515 It is recommended that you provide zeroes for all of those values
3516 except the clock frequency, so that everything except that frequency
3517 will be autoconfigured.
3518 Knowing the frequency helps ensure correct timings for flash access.
3520 The flash controller handles erases automatically on a page (128/256 byte)
3521 basis, so explicit erase commands are not necessary for flash programming.
3522 However, there is an ``EraseAll`` command that can erase an entire flash
3523 plane (of up to 256KB), and it will be used automatically when you issue
3524 @command{flash erase_sector} or @command{flash erase_address} commands.
3526 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3527 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3528 bit for the processor. Each processor has a number of such bits,
3529 used for controlling features such as brownout detection (so they
3530 are not truly general purpose).
3532 This assumes that the first flash bank (number 0) is associated with
3533 the appropriate at91sam7 target.
3538 @deffn {Flash Driver} avr
3539 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3540 @emph{The current implementation is incomplete.}
3541 @comment - defines mass_erase ... pointless given flash_erase_address
3544 @deffn {Flash Driver} ecosflash
3545 @emph{No idea what this is...}
3546 The @var{ecosflash} driver defines one mandatory parameter,
3547 the name of a modules of target code which is downloaded
3551 @deffn {Flash Driver} lpc2000
3552 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3553 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3556 There are LPC2000 devices which are not supported by the @var{lpc2000}
3558 The LPC2888 is supported by the @var{lpc288x} driver.
3559 The LPC29xx family is supported by the @var{lpc2900} driver.
3562 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3563 which must appear in the following order:
3566 @item @var{variant} ... required, may be
3567 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3568 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3569 or @var{lpc1700} (LPC175x and LPC176x)
3570 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3571 at which the core is running
3572 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3573 telling the driver to calculate a valid checksum for the exception vector table.
3576 LPC flashes don't require the chip and bus width to be specified.
3579 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3580 lpc2000_v2 14765 calc_checksum
3583 @deffn {Command} {lpc2000 part_id} bank
3584 Displays the four byte part identifier associated with
3585 the specified flash @var{bank}.
3589 @deffn {Flash Driver} lpc288x
3590 The LPC2888 microcontroller from NXP needs slightly different flash
3591 support from its lpc2000 siblings.
3592 The @var{lpc288x} driver defines one mandatory parameter,
3593 the programming clock rate in Hz.
3594 LPC flashes don't require the chip and bus width to be specified.
3597 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3601 @deffn {Flash Driver} lpc2900
3602 This driver supports the LPC29xx ARM968E based microcontroller family
3605 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3606 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3607 sector layout are auto-configured by the driver.
3608 The driver has one additional mandatory parameter: The CPU clock rate
3609 (in kHz) at the time the flash operations will take place. Most of the time this
3610 will not be the crystal frequency, but a higher PLL frequency. The
3611 @code{reset-init} event handler in the board script is usually the place where
3614 The driver rejects flashless devices (currently the LPC2930).
3616 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3617 It must be handled much more like NAND flash memory, and will therefore be
3618 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3620 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3621 sector needs to be erased or programmed, it is automatically unprotected.
3622 What is shown as protection status in the @code{flash info} command, is
3623 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3624 sector from ever being erased or programmed again. As this is an irreversible
3625 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3626 and not by the standard @code{flash protect} command.
3628 Example for a 125 MHz clock frequency:
3630 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3633 Some @code{lpc2900}-specific commands are defined. In the following command list,
3634 the @var{bank} parameter is the bank number as obtained by the
3635 @code{flash banks} command.
3637 @deffn Command {lpc2900 signature} bank
3638 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3639 content. This is a hardware feature of the flash block, hence the calculation is
3640 very fast. You may use this to verify the content of a programmed device against
3645 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3649 @deffn Command {lpc2900 read_custom} bank filename
3650 Reads the 912 bytes of customer information from the flash index sector, and
3651 saves it to a file in binary format.
3654 lpc2900 read_custom 0 /path_to/customer_info.bin
3658 The index sector of the flash is a @emph{write-only} sector. It cannot be
3659 erased! In order to guard against unintentional write access, all following
3660 commands need to be preceeded by a successful call to the @code{password}
3663 @deffn Command {lpc2900 password} bank password
3664 You need to use this command right before each of the following commands:
3665 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3666 @code{lpc2900 secure_jtag}.
3668 The password string is fixed to "I_know_what_I_am_doing".
3671 lpc2900 password 0 I_know_what_I_am_doing
3672 Potentially dangerous operation allowed in next command!
3676 @deffn Command {lpc2900 write_custom} bank filename type
3677 Writes the content of the file into the customer info space of the flash index
3678 sector. The filetype can be specified with the @var{type} field. Possible values
3679 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3680 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3681 contain a single section, and the contained data length must be exactly
3683 @quotation Attention
3684 This cannot be reverted! Be careful!
3688 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3692 @deffn Command {lpc2900 secure_sector} bank first last
3693 Secures the sector range from @var{first} to @var{last} (including) against
3694 further program and erase operations. The sector security will be effective
3695 after the next power cycle.
3696 @quotation Attention
3697 This cannot be reverted! Be careful!
3699 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3702 lpc2900 secure_sector 0 1 1
3704 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3705 # 0: 0x00000000 (0x2000 8kB) not protected
3706 # 1: 0x00002000 (0x2000 8kB) protected
3707 # 2: 0x00004000 (0x2000 8kB) not protected
3711 @deffn Command {lpc2900 secure_jtag} bank
3712 Irreversibly disable the JTAG port. The new JTAG security setting will be
3713 effective after the next power cycle.
3714 @quotation Attention
3715 This cannot be reverted! Be careful!
3719 lpc2900 secure_jtag 0
3724 @deffn {Flash Driver} ocl
3725 @emph{No idea what this is, other than using some arm7/arm9 core.}
3728 flash bank ocl 0 0 0 0 $_TARGETNAME
3732 @deffn {Flash Driver} pic32mx
3733 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3734 and integrate flash memory.
3735 @emph{The current implementation is incomplete.}
3738 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3741 @comment numerous *disabled* commands are defined:
3742 @comment - chip_erase ... pointless given flash_erase_address
3743 @comment - lock, unlock ... pointless given protect on/off (yes?)
3744 @comment - pgm_word ... shouldn't bank be deduced from address??
3745 Some pic32mx-specific commands are defined:
3746 @deffn Command {pic32mx pgm_word} address value bank
3747 Programs the specified 32-bit @var{value} at the given @var{address}
3748 in the specified chip @var{bank}.
3752 @deffn {Flash Driver} stellaris
3753 All members of the Stellaris LM3Sxxx microcontroller family from
3755 include internal flash and use ARM Cortex M3 cores.
3756 The driver automatically recognizes a number of these chips using
3757 the chip identification register, and autoconfigures itself.
3758 @footnote{Currently there is a @command{stellaris mass_erase} command.
3759 That seems pointless since the same effect can be had using the
3760 standard @command{flash erase_address} command.}
3763 flash bank stellaris 0 0 0 0 $_TARGETNAME
3767 @deffn {Flash Driver} stm32x
3768 All members of the STM32 microcontroller family from ST Microelectronics
3769 include internal flash and use ARM Cortex M3 cores.
3770 The driver automatically recognizes a number of these chips using
3771 the chip identification register, and autoconfigures itself.
3774 flash bank stm32x 0 0 0 0 $_TARGETNAME
3777 Some stm32x-specific commands
3778 @footnote{Currently there is a @command{stm32x mass_erase} command.
3779 That seems pointless since the same effect can be had using the
3780 standard @command{flash erase_address} command.}
3783 @deffn Command {stm32x lock} num
3784 Locks the entire stm32 device.
3785 The @var{num} parameter is a value shown by @command{flash banks}.
3788 @deffn Command {stm32x unlock} num
3789 Unlocks the entire stm32 device.
3790 The @var{num} parameter is a value shown by @command{flash banks}.
3793 @deffn Command {stm32x options_read} num
3794 Read and display the stm32 option bytes written by
3795 the @command{stm32x options_write} command.
3796 The @var{num} parameter is a value shown by @command{flash banks}.
3799 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3800 Writes the stm32 option byte with the specified values.
3801 The @var{num} parameter is a value shown by @command{flash banks}.
3805 @deffn {Flash Driver} str7x
3806 All members of the STR7 microcontroller family from ST Microelectronics
3807 include internal flash and use ARM7TDMI cores.
3808 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3809 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3812 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3815 @deffn Command {str7x disable_jtag} bank
3816 Activate the Debug/Readout protection mechanism
3817 for the specified flash bank.
3821 @deffn {Flash Driver} str9x
3822 Most members of the STR9 microcontroller family from ST Microelectronics
3823 include internal flash and use ARM966E cores.
3824 The str9 needs the flash controller to be configured using
3825 the @command{str9x flash_config} command prior to Flash programming.
3828 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3829 str9x flash_config 0 4 2 0 0x80000
3832 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3833 Configures the str9 flash controller.
3834 The @var{num} parameter is a value shown by @command{flash banks}.
3837 @item @var{bbsr} - Boot Bank Size register
3838 @item @var{nbbsr} - Non Boot Bank Size register
3839 @item @var{bbadr} - Boot Bank Start Address register
3840 @item @var{nbbadr} - Boot Bank Start Address register
3846 @deffn {Flash Driver} tms470
3847 Most members of the TMS470 microcontroller family from Texas Instruments
3848 include internal flash and use ARM7TDMI cores.
3849 This driver doesn't require the chip and bus width to be specified.
3851 Some tms470-specific commands are defined:
3853 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3854 Saves programming keys in a register, to enable flash erase and write commands.
3857 @deffn Command {tms470 osc_mhz} clock_mhz
3858 Reports the clock speed, which is used to calculate timings.
3861 @deffn Command {tms470 plldis} (0|1)
3862 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3867 @subsection str9xpec driver
3870 Here is some background info to help
3871 you better understand how this driver works. OpenOCD has two flash drivers for
3875 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3876 flash programming as it is faster than the @option{str9xpec} driver.
3878 Direct programming @option{str9xpec} using the flash controller. This is an
3879 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3880 core does not need to be running to program using this flash driver. Typical use
3881 for this driver is locking/unlocking the target and programming the option bytes.
3884 Before we run any commands using the @option{str9xpec} driver we must first disable
3885 the str9 core. This example assumes the @option{str9xpec} driver has been
3886 configured for flash bank 0.
3888 # assert srst, we do not want core running
3889 # while accessing str9xpec flash driver
3891 # turn off target polling
3894 str9xpec enable_turbo 0
3896 str9xpec options_read 0
3897 # re-enable str9 core
3898 str9xpec disable_turbo 0
3902 The above example will read the str9 option bytes.
3903 When performing a unlock remember that you will not be able to halt the str9 - it
3904 has been locked. Halting the core is not required for the @option{str9xpec} driver
3905 as mentioned above, just issue the commands above manually or from a telnet prompt.
3907 @deffn {Flash Driver} str9xpec
3908 Only use this driver for locking/unlocking the device or configuring the option bytes.
3909 Use the standard str9 driver for programming.
3910 Before using the flash commands the turbo mode must be enabled using the
3911 @command{str9xpec enable_turbo} command.
3913 Several str9xpec-specific commands are defined:
3915 @deffn Command {str9xpec disable_turbo} num
3916 Restore the str9 into JTAG chain.
3919 @deffn Command {str9xpec enable_turbo} num
3920 Enable turbo mode, will simply remove the str9 from the chain and talk
3921 directly to the embedded flash controller.
3924 @deffn Command {str9xpec lock} num
3925 Lock str9 device. The str9 will only respond to an unlock command that will
3929 @deffn Command {str9xpec part_id} num
3930 Prints the part identifier for bank @var{num}.
3933 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3934 Configure str9 boot bank.
3937 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3938 Configure str9 lvd source.
3941 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3942 Configure str9 lvd threshold.
3945 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3946 Configure str9 lvd reset warning source.
3949 @deffn Command {str9xpec options_read} num
3950 Read str9 option bytes.
3953 @deffn Command {str9xpec options_write} num
3954 Write str9 option bytes.
3957 @deffn Command {str9xpec unlock} num
3966 @subsection mFlash Configuration
3967 @cindex mFlash Configuration
3969 @deffn {Config Command} {mflash bank} soc base RST_pin target
3970 Configures a mflash for @var{soc} host bank at
3972 The pin number format depends on the host GPIO naming convention.
3973 Currently, the mflash driver supports s3c2440 and pxa270.
3975 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3978 mflash bank s3c2440 0x10000000 1b 0
3981 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3984 mflash bank pxa270 0x08000000 43 0
3988 @subsection mFlash commands
3989 @cindex mFlash commands
3991 @deffn Command {mflash config pll} frequency
3992 Configure mflash PLL.
3993 The @var{frequency} is the mflash input frequency, in Hz.
3994 Issuing this command will erase mflash's whole internal nand and write new pll.
3995 After this command, mflash needs power-on-reset for normal operation.
3996 If pll was newly configured, storage and boot(optional) info also need to be update.
3999 @deffn Command {mflash config boot}
4000 Configure bootable option.
4001 If bootable option is set, mflash offer the first 8 sectors
4005 @deffn Command {mflash config storage}
4006 Configure storage information.
4007 For the normal storage operation, this information must be
4011 @deffn Command {mflash dump} num filename offset size
4012 Dump @var{size} bytes, starting at @var{offset} bytes from the
4013 beginning of the bank @var{num}, to the file named @var{filename}.
4016 @deffn Command {mflash probe}
4020 @deffn Command {mflash write} num filename offset
4021 Write the binary file @var{filename} to mflash bank @var{num}, starting at
4022 @var{offset} bytes from the beginning of the bank.
4025 @node NAND Flash Commands
4026 @chapter NAND Flash Commands
4029 Compared to NOR or SPI flash, NAND devices are inexpensive
4030 and high density. Today's NAND chips, and multi-chip modules,
4031 commonly hold multiple GigaBytes of data.
4033 NAND chips consist of a number of ``erase blocks'' of a given
4034 size (such as 128 KBytes), each of which is divided into a
4035 number of pages (of perhaps 512 or 2048 bytes each). Each
4036 page of a NAND flash has an ``out of band'' (OOB) area to hold
4037 Error Correcting Code (ECC) and other metadata, usually 16 bytes
4038 of OOB for every 512 bytes of page data.
4040 One key characteristic of NAND flash is that its error rate
4041 is higher than that of NOR flash. In normal operation, that
4042 ECC is used to correct and detect errors. However, NAND
4043 blocks can also wear out and become unusable; those blocks
4044 are then marked "bad". NAND chips are even shipped from the
4045 manufacturer with a few bad blocks. The highest density chips
4046 use a technology (MLC) that wears out more quickly, so ECC
4047 support is increasingly important as a way to detect blocks
4048 that have begun to fail, and help to preserve data integrity
4049 with techniques such as wear leveling.
4051 Software is used to manage the ECC. Some controllers don't
4052 support ECC directly; in those cases, software ECC is used.
4053 Other controllers speed up the ECC calculations with hardware.
4054 Single-bit error correction hardware is routine. Controllers
4055 geared for newer MLC chips may correct 4 or more errors for
4056 every 512 bytes of data.
4058 You will need to make sure that any data you write using
4059 OpenOCD includes the apppropriate kind of ECC. For example,
4060 that may mean passing the @code{oob_softecc} flag when
4061 writing NAND data, or ensuring that the correct hardware
4064 The basic steps for using NAND devices include:
4066 @item Declare via the command @command{nand device}
4067 @* Do this in a board-specific configuration file,
4068 passing parameters as needed by the controller.
4069 @item Configure each device using @command{nand probe}.
4070 @* Do this only after the associated target is set up,
4071 such as in its reset-init script or in procures defined
4072 to access that device.
4073 @item Operate on the flash via @command{nand subcommand}
4074 @* Often commands to manipulate the flash are typed by a human, or run
4075 via a script in some automated way. Common task include writing a
4076 boot loader, operating system, or other data needed to initialize or
4080 @b{NOTE:} At the time this text was written, the largest NAND
4081 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4082 This is because the variables used to hold offsets and lengths
4083 are only 32 bits wide.
4084 (Larger chips may work in some cases, unless an offset or length
4085 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4086 Some larger devices will work, since they are actually multi-chip
4087 modules with two smaller chips and individual chipselect lines.
4089 @anchor{NAND Configuration}
4090 @section NAND Configuration Commands
4091 @cindex NAND configuration
4093 NAND chips must be declared in configuration scripts,
4094 plus some additional configuration that's done after
4095 OpenOCD has initialized.
4097 @deffn {Config Command} {nand device} controller target [configparams...]
4098 Declares a NAND device, which can be read and written to
4099 after it has been configured through @command{nand probe}.
4100 In OpenOCD, devices are single chips; this is unlike some
4101 operating systems, which may manage multiple chips as if
4102 they were a single (larger) device.
4103 In some cases, configuring a device will activate extra
4104 commands; see the controller-specific documentation.
4106 @b{NOTE:} This command is not available after OpenOCD
4107 initialization has completed. Use it in board specific
4108 configuration files, not interactively.
4111 @item @var{controller} ... identifies the controller driver
4112 associated with the NAND device being declared.
4113 @xref{NAND Driver List}.
4114 @item @var{target} ... names the target used when issuing
4115 commands to the NAND controller.
4116 @comment Actually, it's currently a controller-specific parameter...
4117 @item @var{configparams} ... controllers may support, or require,
4118 additional parameters. See the controller-specific documentation
4119 for more information.
4123 @deffn Command {nand list}
4124 Prints a summary of each device declared
4125 using @command{nand device}, numbered from zero.
4126 Note that un-probed devices show no details.
4129 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4130 blocksize: 131072, blocks: 8192
4131 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4132 blocksize: 131072, blocks: 8192
4137 @deffn Command {nand probe} num
4138 Probes the specified device to determine key characteristics
4139 like its page and block sizes, and how many blocks it has.
4140 The @var{num} parameter is the value shown by @command{nand list}.
4141 You must (successfully) probe a device before you can use
4142 it with most other NAND commands.
4145 @section Erasing, Reading, Writing to NAND Flash
4147 @deffn Command {nand dump} num filename offset length [oob_option]
4148 @cindex NAND reading
4149 Reads binary data from the NAND device and writes it to the file,
4150 starting at the specified offset.
4151 The @var{num} parameter is the value shown by @command{nand list}.
4153 Use a complete path name for @var{filename}, so you don't depend
4154 on the directory used to start the OpenOCD server.
4156 The @var{offset} and @var{length} must be exact multiples of the
4157 device's page size. They describe a data region; the OOB data
4158 associated with each such page may also be accessed.
4160 @b{NOTE:} At the time this text was written, no error correction
4161 was done on the data that's read, unless raw access was disabled
4162 and the underlying NAND controller driver had a @code{read_page}
4163 method which handled that error correction.
4165 By default, only page data is saved to the specified file.
4166 Use an @var{oob_option} parameter to save OOB data:
4168 @item no oob_* parameter
4169 @*Output file holds only page data; OOB is discarded.
4170 @item @code{oob_raw}
4171 @*Output file interleaves page data and OOB data;
4172 the file will be longer than "length" by the size of the
4173 spare areas associated with each data page.
4174 Note that this kind of "raw" access is different from
4175 what's implied by @command{nand raw_access}, which just
4176 controls whether a hardware-aware access method is used.
4177 @item @code{oob_only}
4178 @*Output file has only raw OOB data, and will
4179 be smaller than "length" since it will contain only the
4180 spare areas associated with each data page.
4184 @deffn Command {nand erase} num [offset length]
4185 @cindex NAND erasing
4186 @cindex NAND programming
4187 Erases blocks on the specified NAND device, starting at the
4188 specified @var{offset} and continuing for @var{length} bytes.
4189 Both of those values must be exact multiples of the device's
4190 block size, and the region they specify must fit entirely in the chip.
4191 If those parameters are not specified,
4192 the whole NAND chip will be erased.
4193 The @var{num} parameter is the value shown by @command{nand list}.
4195 @b{NOTE:} This command will try to erase bad blocks, when told
4196 to do so, which will probably invalidate the manufacturer's bad
4198 For the remainder of the current server session, @command{nand info}
4199 will still report that the block ``is'' bad.
4202 @deffn Command {nand write} num filename offset [option...]
4203 @cindex NAND writing
4204 @cindex NAND programming
4205 Writes binary data from the file into the specified NAND device,
4206 starting at the specified offset. Those pages should already
4207 have been erased; you can't change zero bits to one bits.
4208 The @var{num} parameter is the value shown by @command{nand list}.
4210 Use a complete path name for @var{filename}, so you don't depend
4211 on the directory used to start the OpenOCD server.
4213 The @var{offset} must be an exact multiple of the device's page size.
4214 All data in the file will be written, assuming it doesn't run
4215 past the end of the device.
4216 Only full pages are written, and any extra space in the last
4217 page will be filled with 0xff bytes. (That includes OOB data,
4218 if that's being written.)
4220 @b{NOTE:} At the time this text was written, bad blocks are
4221 ignored. That is, this routine will not skip bad blocks,
4222 but will instead try to write them. This can cause problems.
4224 Provide at most one @var{option} parameter. With some
4225 NAND drivers, the meanings of these parameters may change
4226 if @command{nand raw_access} was used to disable hardware ECC.
4228 @item no oob_* parameter
4229 @*File has only page data, which is written.
4230 If raw acccess is in use, the OOB area will not be written.
4231 Otherwise, if the underlying NAND controller driver has
4232 a @code{write_page} routine, that routine may write the OOB
4233 with hardware-computed ECC data.
4234 @item @code{oob_only}
4235 @*File has only raw OOB data, which is written to the OOB area.
4236 Each page's data area stays untouched. @i{This can be a dangerous
4237 option}, since it can invalidate the ECC data.
4238 You may need to force raw access to use this mode.
4239 @item @code{oob_raw}
4240 @*File interleaves data and OOB data, both of which are written
4241 If raw access is enabled, the data is written first, then the
4243 Otherwise, if the underlying NAND controller driver has
4244 a @code{write_page} routine, that routine may modify the OOB
4245 before it's written, to include hardware-computed ECC data.
4246 @item @code{oob_softecc}
4247 @*File has only page data, which is written.
4248 The OOB area is filled with 0xff, except for a standard 1-bit
4249 software ECC code stored in conventional locations.
4250 You might need to force raw access to use this mode, to prevent
4251 the underlying driver from applying hardware ECC.
4252 @item @code{oob_softecc_kw}
4253 @*File has only page data, which is written.
4254 The OOB area is filled with 0xff, except for a 4-bit software ECC
4255 specific to the boot ROM in Marvell Kirkwood SoCs.
4256 You might need to force raw access to use this mode, to prevent
4257 the underlying driver from applying hardware ECC.
4261 @section Other NAND commands
4262 @cindex NAND other commands
4264 @deffn Command {nand check_bad_blocks} [offset length]
4265 Checks for manufacturer bad block markers on the specified NAND
4266 device. If no parameters are provided, checks the whole
4267 device; otherwise, starts at the specified @var{offset} and
4268 continues for @var{length} bytes.
4269 Both of those values must be exact multiples of the device's
4270 block size, and the region they specify must fit entirely in the chip.
4271 The @var{num} parameter is the value shown by @command{nand list}.
4273 @b{NOTE:} Before using this command you should force raw access
4274 with @command{nand raw_access enable} to ensure that the underlying
4275 driver will not try to apply hardware ECC.
4278 @deffn Command {nand info} num
4279 The @var{num} parameter is the value shown by @command{nand list}.
4280 This prints the one-line summary from "nand list", plus for
4281 devices which have been probed this also prints any known
4282 status for each block.
4285 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4286 Sets or clears an flag affecting how page I/O is done.
4287 The @var{num} parameter is the value shown by @command{nand list}.
4289 This flag is cleared (disabled) by default, but changing that
4290 value won't affect all NAND devices. The key factor is whether
4291 the underlying driver provides @code{read_page} or @code{write_page}
4292 methods. If it doesn't provide those methods, the setting of
4293 this flag is irrelevant; all access is effectively ``raw''.
4295 When those methods exist, they are normally used when reading
4296 data (@command{nand dump} or reading bad block markers) or
4297 writing it (@command{nand write}). However, enabling
4298 raw access (setting the flag) prevents use of those methods,
4299 bypassing hardware ECC logic.
4300 @i{This can be a dangerous option}, since writing blocks
4301 with the wrong ECC data can cause them to be marked as bad.
4304 @anchor{NAND Driver List}
4305 @section NAND Drivers, Options, and Commands
4306 As noted above, the @command{nand device} command allows
4307 driver-specific options and behaviors.
4308 Some controllers also activate controller-specific commands.
4310 @deffn {NAND Driver} davinci
4311 This driver handles the NAND controllers found on DaVinci family
4312 chips from Texas Instruments.
4313 It takes three extra parameters:
4314 address of the NAND chip;
4315 hardware ECC mode to use (@option{hwecc1},
4316 @option{hwecc4}, @option{hwecc4_infix});
4317 address of the AEMIF controller on this processor.
4319 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4321 All DaVinci processors support the single-bit ECC hardware,
4322 and newer ones also support the four-bit ECC hardware.
4323 The @code{write_page} and @code{read_page} methods are used
4324 to implement those ECC modes, unless they are disabled using
4325 the @command{nand raw_access} command.
4328 @deffn {NAND Driver} lpc3180
4329 These controllers require an extra @command{nand device}
4330 parameter: the clock rate used by the controller.
4331 @deffn Command {lpc3180 select} num [mlc|slc]
4332 Configures use of the MLC or SLC controller mode.
4333 MLC implies use of hardware ECC.
4334 The @var{num} parameter is the value shown by @command{nand list}.
4337 At this writing, this driver includes @code{write_page}
4338 and @code{read_page} methods. Using @command{nand raw_access}
4339 to disable those methods will prevent use of hardware ECC
4340 in the MLC controller mode, but won't change SLC behavior.
4342 @comment current lpc3180 code won't issue 5-byte address cycles
4344 @deffn {NAND Driver} orion
4345 These controllers require an extra @command{nand device}
4346 parameter: the address of the controller.
4348 nand device orion 0xd8000000
4350 These controllers don't define any specialized commands.
4351 At this writing, their drivers don't include @code{write_page}
4352 or @code{read_page} methods, so @command{nand raw_access} won't
4353 change any behavior.
4356 @deffn {NAND Driver} s3c2410
4357 @deffnx {NAND Driver} s3c2412
4358 @deffnx {NAND Driver} s3c2440
4359 @deffnx {NAND Driver} s3c2443
4360 These S3C24xx family controllers don't have any special
4361 @command{nand device} options, and don't define any
4362 specialized commands.
4363 At this writing, their drivers don't include @code{write_page}
4364 or @code{read_page} methods, so @command{nand raw_access} won't
4365 change any behavior.
4368 @node PLD/FPGA Commands
4369 @chapter PLD/FPGA Commands
4373 Programmable Logic Devices (PLDs) and the more flexible
4374 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4375 OpenOCD can support programming them.
4376 Although PLDs are generally restrictive (cells are less functional, and
4377 there are no special purpose cells for memory or computational tasks),
4378 they share the same OpenOCD infrastructure.
4379 Accordingly, both are called PLDs here.
4381 @section PLD/FPGA Configuration and Commands
4383 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4384 OpenOCD maintains a list of PLDs available for use in various commands.
4385 Also, each such PLD requires a driver.
4387 They are referenced by the number shown by the @command{pld devices} command,
4388 and new PLDs are defined by @command{pld device driver_name}.
4390 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4391 Defines a new PLD device, supported by driver @var{driver_name},
4392 using the TAP named @var{tap_name}.
4393 The driver may make use of any @var{driver_options} to configure its
4397 @deffn {Command} {pld devices}
4398 Lists the PLDs and their numbers.
4401 @deffn {Command} {pld load} num filename
4402 Loads the file @file{filename} into the PLD identified by @var{num}.
4403 The file format must be inferred by the driver.
4406 @section PLD/FPGA Drivers, Options, and Commands
4408 Drivers may support PLD-specific options to the @command{pld device}
4409 definition command, and may also define commands usable only with
4410 that particular type of PLD.
4412 @deffn {FPGA Driver} virtex2
4413 Virtex-II is a family of FPGAs sold by Xilinx.
4414 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4415 No driver-specific PLD definition options are used,
4416 and one driver-specific command is defined.
4418 @deffn {Command} {virtex2 read_stat} num
4419 Reads and displays the Virtex-II status register (STAT)
4424 @node General Commands
4425 @chapter General Commands
4428 The commands documented in this chapter here are common commands that
4429 you, as a human, may want to type and see the output of. Configuration type
4430 commands are documented elsewhere.
4434 @item @b{Source Of Commands}
4435 @* OpenOCD commands can occur in a configuration script (discussed
4436 elsewhere) or typed manually by a human or supplied programatically,
4437 or via one of several TCP/IP Ports.
4439 @item @b{From the human}
4440 @* A human should interact with the telnet interface (default port: 4444)
4441 or via GDB (default port 3333).
4443 To issue commands from within a GDB session, use the @option{monitor}
4444 command, e.g. use @option{monitor poll} to issue the @option{poll}
4445 command. All output is relayed through the GDB session.
4447 @item @b{Machine Interface}
4448 The Tcl interface's intent is to be a machine interface. The default Tcl
4453 @section Daemon Commands
4455 @deffn {Command} exit
4456 Exits the current telnet session.
4459 @c note EXTREMELY ANNOYING word wrap at column 75
4460 @c even when lines are e.g. 100+ columns ...
4461 @c coded in startup.tcl
4462 @deffn {Command} help [string]
4463 With no parameters, prints help text for all commands.
4464 Otherwise, prints each helptext containing @var{string}.
4465 Not every command provides helptext.
4468 @deffn Command sleep msec [@option{busy}]
4469 Wait for at least @var{msec} milliseconds before resuming.
4470 If @option{busy} is passed, busy-wait instead of sleeping.
4471 (This option is strongly discouraged.)
4472 Useful in connection with script files
4473 (@command{script} command and @command{target_name} configuration).
4476 @deffn Command shutdown
4477 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4480 @anchor{debug_level}
4481 @deffn Command debug_level [n]
4482 @cindex message level
4483 Display debug level.
4484 If @var{n} (from 0..3) is provided, then set it to that level.
4485 This affects the kind of messages sent to the server log.
4486 Level 0 is error messages only;
4487 level 1 adds warnings;
4488 level 2 adds informational messages;
4489 and level 3 adds debugging messages.
4490 The default is level 2, but that can be overridden on
4491 the command line along with the location of that log
4492 file (which is normally the server's standard output).
4496 @deffn Command fast (@option{enable}|@option{disable})
4498 Set default behaviour of OpenOCD to be "fast and dangerous".
4500 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4501 fast memory access, and DCC downloads. Those parameters may still be
4502 individually overridden.
4504 The target specific "dangerous" optimisation tweaking options may come and go
4505 as more robust and user friendly ways are found to ensure maximum throughput
4506 and robustness with a minimum of configuration.
4508 Typically the "fast enable" is specified first on the command line:
4511 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4515 @deffn Command echo message
4516 Logs a message at "user" priority.
4517 Output @var{message} to stdout.
4519 echo "Downloading kernel -- please wait"
4523 @deffn Command log_output [filename]
4524 Redirect logging to @var{filename};
4525 the initial log output channel is stderr.
4528 @anchor{Target State handling}
4529 @section Target State handling
4532 @cindex target initialization
4534 In this section ``target'' refers to a CPU configured as
4535 shown earlier (@pxref{CPU Configuration}).
4536 These commands, like many, implicitly refer to
4537 a current target which is used to perform the
4538 various operations. The current target may be changed
4539 by using @command{targets} command with the name of the
4540 target which should become current.
4542 @deffn Command reg [(number|name) [value]]
4543 Access a single register by @var{number} or by its @var{name}.
4545 @emph{With no arguments}:
4546 list all available registers for the current target,
4547 showing number, name, size, value, and cache status.
4549 @emph{With number/name}: display that register's value.
4551 @emph{With both number/name and value}: set register's value.
4553 Cores may have surprisingly many registers in their
4554 Debug and trace infrastructure:
4558 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4559 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4560 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4562 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4563 0x00000000 (dirty: 0, valid: 0)
4568 @deffn Command halt [ms]
4569 @deffnx Command wait_halt [ms]
4570 The @command{halt} command first sends a halt request to the target,
4571 which @command{wait_halt} doesn't.
4572 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4573 or 5 seconds if there is no parameter, for the target to halt
4574 (and enter debug mode).
4575 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4578 On ARM cores, software using the @emph{wait for interrupt} operation
4579 often blocks the JTAG access needed by a @command{halt} command.
4580 This is because that operation also puts the core into a low
4581 power mode by gating the core clock;
4582 but the core clock is needed to detect JTAG clock transitions.
4584 One partial workaround uses adaptive clocking: when the core is
4585 interrupted the operation completes, then JTAG clocks are accepted
4586 at least until the interrupt handler completes.
4587 However, this workaround is often unusable since the processor, board,
4588 and JTAG adapter must all support adaptive JTAG clocking.
4589 Also, it can't work until an interrupt is issued.
4591 A more complete workaround is to not use that operation while you
4592 work with a JTAG debugger.
4593 Tasking environments generaly have idle loops where the body is the
4594 @emph{wait for interrupt} operation.
4595 (On older cores, it is a coprocessor action;
4596 newer cores have a @option{wfi} instruction.)
4597 Such loops can just remove that operation, at the cost of higher
4598 power consumption (because the CPU is needlessly clocked).
4603 @deffn Command resume [address]
4604 Resume the target at its current code position,
4605 or the optional @var{address} if it is provided.
4606 OpenOCD will wait 5 seconds for the target to resume.
4609 @deffn Command step [address]
4610 Single-step the target at its current code position,
4611 or the optional @var{address} if it is provided.
4614 @anchor{Reset Command}
4615 @deffn Command reset
4616 @deffnx Command {reset run}
4617 @deffnx Command {reset halt}
4618 @deffnx Command {reset init}
4619 Perform as hard a reset as possible, using SRST if possible.
4620 @emph{All defined targets will be reset, and target
4621 events will fire during the reset sequence.}
4623 The optional parameter specifies what should
4624 happen after the reset.
4625 If there is no parameter, a @command{reset run} is executed.
4626 The other options will not work on all systems.
4627 @xref{Reset Configuration}.
4630 @item @b{run} Let the target run
4631 @item @b{halt} Immediately halt the target
4632 @item @b{init} Immediately halt the target, and execute the reset-init script
4636 @deffn Command soft_reset_halt
4637 Requesting target halt and executing a soft reset. This is often used
4638 when a target cannot be reset and halted. The target, after reset is
4639 released begins to execute code. OpenOCD attempts to stop the CPU and
4640 then sets the program counter back to the reset vector. Unfortunately
4641 the code that was executed may have left the hardware in an unknown
4645 @section I/O Utilities
4647 These commands are available when
4648 OpenOCD is built with @option{--enable-ioutil}.
4649 They are mainly useful on embedded targets,
4651 Hosts with operating systems have complementary tools.
4653 @emph{Note:} there are several more such commands.
4655 @deffn Command append_file filename [string]*
4656 Appends the @var{string} parameters to
4657 the text file @file{filename}.
4658 Each string except the last one is followed by one space.
4659 The last string is followed by a newline.
4662 @deffn Command cat filename
4663 Reads and displays the text file @file{filename}.
4666 @deffn Command cp src_filename dest_filename
4667 Copies contents from the file @file{src_filename}
4668 into @file{dest_filename}.
4672 @emph{No description provided.}
4676 @emph{No description provided.}
4680 @emph{No description provided.}
4683 @deffn Command meminfo
4684 Display available RAM memory on OpenOCD host.
4685 Used in OpenOCD regression testing scripts.
4689 @emph{No description provided.}
4693 @emph{No description provided.}
4696 @deffn Command rm filename
4697 @c "rm" has both normal and Jim-level versions??
4698 Unlinks the file @file{filename}.
4701 @deffn Command trunc filename
4702 Removes all data in the file @file{filename}.
4705 @anchor{Memory access}
4706 @section Memory access commands
4707 @cindex memory access
4709 These commands allow accesses of a specific size to the memory
4710 system. Often these are used to configure the current target in some
4711 special way. For example - one may need to write certain values to the
4712 SDRAM controller to enable SDRAM.
4715 @item Use the @command{targets} (plural) command
4716 to change the current target.
4717 @item In system level scripts these commands are deprecated.
4718 Please use their TARGET object siblings to avoid making assumptions
4719 about what TAP is the current target, or about MMU configuration.
4722 @deffn Command mdw addr [count]
4723 @deffnx Command mdh addr [count]
4724 @deffnx Command mdb addr [count]
4725 Display contents of address @var{addr}, as
4726 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4727 or 8-bit bytes (@command{mdb}).
4728 If @var{count} is specified, displays that many units.
4729 (If you want to manipulate the data instead of displaying it,
4730 see the @code{mem2array} primitives.)
4733 @deffn Command mww addr word
4734 @deffnx Command mwh addr halfword
4735 @deffnx Command mwb addr byte
4736 Writes the specified @var{word} (32 bits),
4737 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4738 at the specified address @var{addr}.
4742 @anchor{Image access}
4743 @section Image loading commands
4744 @cindex image loading
4745 @cindex image dumping
4748 @deffn Command {dump_image} filename address size
4749 Dump @var{size} bytes of target memory starting at @var{address} to the
4750 binary file named @var{filename}.
4753 @deffn Command {fast_load}
4754 Loads an image stored in memory by @command{fast_load_image} to the
4755 current target. Must be preceeded by fast_load_image.
4758 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4759 Normally you should be using @command{load_image} or GDB load. However, for
4760 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4761 host), storing the image in memory and uploading the image to the target
4762 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4763 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4764 memory, i.e. does not affect target. This approach is also useful when profiling
4765 target programming performance as I/O and target programming can easily be profiled
4770 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4771 Load image from file @var{filename} to target memory at @var{address}.
4772 The file format may optionally be specified
4773 (@option{bin}, @option{ihex}, or @option{elf})
4776 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4777 Displays image section sizes and addresses
4778 as if @var{filename} were loaded into target memory
4779 starting at @var{address} (defaults to zero).
4780 The file format may optionally be specified
4781 (@option{bin}, @option{ihex}, or @option{elf})
4784 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4785 Verify @var{filename} against target memory starting at @var{address}.
4786 The file format may optionally be specified
4787 (@option{bin}, @option{ihex}, or @option{elf})
4788 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4792 @section Breakpoint and Watchpoint commands
4796 CPUs often make debug modules accessible through JTAG, with
4797 hardware support for a handful of code breakpoints and data
4799 In addition, CPUs almost always support software breakpoints.
4801 @deffn Command {bp} [address len [@option{hw}]]
4802 With no parameters, lists all active breakpoints.
4803 Else sets a breakpoint on code execution starting
4804 at @var{address} for @var{length} bytes.
4805 This is a software breakpoint, unless @option{hw} is specified
4806 in which case it will be a hardware breakpoint.
4808 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4809 for similar mechanisms that do not consume hardware breakpoints.)
4812 @deffn Command {rbp} address
4813 Remove the breakpoint at @var{address}.
4816 @deffn Command {rwp} address
4817 Remove data watchpoint on @var{address}
4820 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4821 With no parameters, lists all active watchpoints.
4822 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4823 The watch point is an "access" watchpoint unless
4824 the @option{r} or @option{w} parameter is provided,
4825 defining it as respectively a read or write watchpoint.
4826 If a @var{value} is provided, that value is used when determining if
4827 the watchpoint should trigger. The value may be first be masked
4828 using @var{mask} to mark ``don't care'' fields.
4831 @section Misc Commands
4834 @deffn Command {profile} seconds filename
4835 Profiling samples the CPU's program counter as quickly as possible,
4836 which is useful for non-intrusive stochastic profiling.
4837 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4840 @deffn Command {version}
4841 Displays a string identifying the version of this OpenOCD server.
4844 @deffn Command {virt2phys} virtual_address
4845 Requests the current target to map the specified @var{virtual_address}
4846 to its corresponding physical address, and displays the result.
4849 @node Architecture and Core Commands
4850 @chapter Architecture and Core Commands
4851 @cindex Architecture Specific Commands
4852 @cindex Core Specific Commands
4854 Most CPUs have specialized JTAG operations to support debugging.
4855 OpenOCD packages most such operations in its standard command framework.
4856 Some of those operations don't fit well in that framework, so they are
4857 exposed here as architecture or implementation (core) specific commands.
4859 @anchor{ARM Hardware Tracing}
4860 @section ARM Hardware Tracing
4865 CPUs based on ARM cores may include standard tracing interfaces,
4866 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4867 address and data bus trace records to a ``Trace Port''.
4871 Development-oriented boards will sometimes provide a high speed
4872 trace connector for collecting that data, when the particular CPU
4873 supports such an interface.
4874 (The standard connector is a 38-pin Mictor, with both JTAG
4875 and trace port support.)
4876 Those trace connectors are supported by higher end JTAG adapters
4877 and some logic analyzer modules; frequently those modules can
4878 buffer several megabytes of trace data.
4879 Configuring an ETM coupled to such an external trace port belongs
4880 in the board-specific configuration file.
4882 If the CPU doesn't provide an external interface, it probably
4883 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4884 dedicated SRAM. 4KBytes is one common ETB size.
4885 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4886 (target) configuration file, since it works the same on all boards.
4889 ETM support in OpenOCD doesn't seem to be widely used yet.
4892 ETM support may be buggy, and at least some @command{etm config}
4893 parameters should be detected by asking the ETM for them.
4894 It seems like a GDB hookup should be possible,
4895 as well as triggering trace on specific events
4896 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4897 There should be GUI tools to manipulate saved trace data and help
4898 analyse it in conjunction with the source code.
4899 It's unclear how much of a common interface is shared
4900 with the current XScale trace support, or should be
4901 shared with eventual Nexus-style trace module support.
4902 At this writing (September 2009) only ARM7 and ARM9 support
4903 for ETM modules is available. The code should be able to
4904 work with some newer cores; but not all of them support
4905 this original style of JTAG access.
4908 @subsection ETM Configuration
4909 ETM setup is coupled with the trace port driver configuration.
4911 @deffn {Config Command} {etm config} target width mode clocking driver
4912 Declares the ETM associated with @var{target}, and associates it
4913 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4915 Several of the parameters must reflect the trace port configuration.
4916 The @var{width} must be either 4, 8, or 16.
4917 The @var{mode} must be @option{normal}, @option{multiplexted},
4918 or @option{demultiplexted}.
4919 The @var{clocking} must be @option{half} or @option{full}.
4922 You can see the ETM registers using the @command{reg} command.
4923 Not all possible registers are present in every ETM.
4924 Most of the registers are write-only, and are used to configure
4925 what CPU activities are traced.
4929 @deffn Command {etm info}
4930 Displays information about the current target's ETM.
4933 @deffn Command {etm status}
4934 Displays status of the current target's ETM and trace port driver:
4935 is the ETM idle, or is it collecting data?
4936 Did trace data overflow?
4940 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4941 Displays what data that ETM will collect.
4942 If arguments are provided, first configures that data.
4943 When the configuration changes, tracing is stopped
4944 and any buffered trace data is invalidated.
4947 @item @var{type} ... describing how data accesses are traced,
4948 when they pass any ViewData filtering that that was set up.
4950 @option{none} (save nothing),
4951 @option{data} (save data),
4952 @option{address} (save addresses),
4953 @option{all} (save data and addresses)
4954 @item @var{context_id_bits} ... 0, 8, 16, or 32
4955 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4956 cycle-accurate instruction tracing.
4957 Before ETMv3, enabling this causes much extra data to be recorded.
4958 @item @var{branch_output} ... @option{enable} or @option{disable}.
4959 Disable this unless you need to try reconstructing the instruction
4960 trace stream without an image of the code.
4964 @deffn Command {etm trigger_percent} [percent]
4965 This displays, or optionally changes, the trace port driver's
4966 behavior after the ETM's configured @emph{trigger} event fires.
4967 It controls how much more trace data is saved after the (single)
4968 trace trigger becomes active.
4971 @item The default corresponds to @emph{trace around} usage,
4972 recording 50 percent data before the event and the rest
4974 @item The minimum value of @var{percent} is 2 percent,
4975 recording almost exclusively data before the trigger.
4976 Such extreme @emph{trace before} usage can help figure out
4977 what caused that event to happen.
4978 @item The maximum value of @var{percent} is 100 percent,
4979 recording data almost exclusively after the event.
4980 This extreme @emph{trace after} usage might help sort out
4981 how the event caused trouble.
4983 @c REVISIT allow "break" too -- enter debug mode.
4986 @subsection ETM Trace Operation
4988 After setting up the ETM, you can use it to collect data.
4989 That data can be exported to files for later analysis.
4990 It can also be parsed with OpenOCD, for basic sanity checking.
4992 To configure what is being traced, you will need to write
4993 various trace registers using @command{reg ETM_*} commands.
4994 For the definitions of these registers, read ARM publication
4995 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
4996 Be aware that most of the relevant registers are write-only,
4997 and that ETM resources are limited. There are only a handful
4998 of address comparators, data comparators, counters, and so on.
5000 Examples of scenarios you might arrange to trace include:
5003 @item Code flow within a function, @emph{excluding} subroutines
5004 it calls. Use address range comparators to enable tracing
5005 for instruction access within that function's body.
5006 @item Code flow within a function, @emph{including} subroutines
5007 it calls. Use the sequencer and address comparators to activate
5008 tracing on an ``entered function'' state, then deactivate it by
5009 exiting that state when the function's exit code is invoked.
5010 @item Code flow starting at the fifth invocation of a function,
5011 combining one of the above models with a counter.
5012 @item CPU data accesses to the registers for a particular device,
5013 using address range comparators and the ViewData logic.
5014 @item Such data accesses only during IRQ handling, combining the above
5015 model with sequencer triggers which on entry and exit to the IRQ handler.
5016 @item @emph{... more}
5019 At this writing, September 2009, there are no Tcl utility
5020 procedures to help set up any common tracing scenarios.
5022 @deffn Command {etm analyze}
5023 Reads trace data into memory, if it wasn't already present.
5024 Decodes and prints the data that was collected.
5027 @deffn Command {etm dump} filename
5028 Stores the captured trace data in @file{filename}.
5031 @deffn Command {etm image} filename [base_address] [type]
5032 Opens an image file.
5035 @deffn Command {etm load} filename
5036 Loads captured trace data from @file{filename}.
5039 @deffn Command {etm start}
5040 Starts trace data collection.
5043 @deffn Command {etm stop}
5044 Stops trace data collection.
5047 @anchor{Trace Port Drivers}
5048 @subsection Trace Port Drivers
5050 To use an ETM trace port it must be associated with a driver.
5052 @deffn {Trace Port Driver} dummy
5053 Use the @option{dummy} driver if you are configuring an ETM that's
5054 not connected to anything (on-chip ETB or off-chip trace connector).
5055 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
5056 any trace data collection.}
5057 @deffn {Config Command} {etm_dummy config} target
5058 Associates the ETM for @var{target} with a dummy driver.
5062 @deffn {Trace Port Driver} etb
5063 Use the @option{etb} driver if you are configuring an ETM
5064 to use on-chip ETB memory.
5065 @deffn {Config Command} {etb config} target etb_tap
5066 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
5067 You can see the ETB registers using the @command{reg} command.
5071 @deffn {Trace Port Driver} oocd_trace
5072 This driver isn't available unless OpenOCD was explicitly configured
5073 with the @option{--enable-oocd_trace} option. You probably don't want
5074 to configure it unless you've built the appropriate prototype hardware;
5075 it's @emph{proof-of-concept} software.
5077 Use the @option{oocd_trace} driver if you are configuring an ETM that's
5078 connected to an off-chip trace connector.
5080 @deffn {Config Command} {oocd_trace config} target tty
5081 Associates the ETM for @var{target} with a trace driver which
5082 collects data through the serial port @var{tty}.
5085 @deffn Command {oocd_trace resync}
5086 Re-synchronizes with the capture clock.
5089 @deffn Command {oocd_trace status}
5090 Reports whether the capture clock is locked or not.
5095 @section ARMv4 and ARMv5 Architecture
5099 These commands are specific to ARM architecture v4 and v5,
5100 including all ARM7 or ARM9 systems and Intel XScale.
5101 They are available in addition to other core-specific
5102 commands that may be available.
5104 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
5105 Displays the core_state, optionally changing it to process
5106 either @option{arm} or @option{thumb} instructions.
5107 The target may later be resumed in the currently set core_state.
5108 (Processors may also support the Jazelle state, but
5109 that is not currently supported in OpenOCD.)
5112 @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
5114 Disassembles @var{count} instructions starting at @var{address}.
5115 If @var{count} is not specified, a single instruction is disassembled.
5116 If @option{thumb} is specified, or the low bit of the address is set,
5117 Thumb (16-bit) instructions are used;
5118 else ARM (32-bit) instructions are used.
5119 (Processors may also support the Jazelle state, but
5120 those instructions are not currently understood by OpenOCD.)
5123 @deffn Command {armv4_5 reg}
5124 Display a table of all banked core registers, fetching the current value from every
5125 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
5129 @subsection ARM7 and ARM9 specific commands
5133 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
5134 ARM9TDMI, ARM920T or ARM926EJ-S.
5135 They are available in addition to the ARMv4/5 commands,
5136 and any other core-specific commands that may be available.
5138 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
5139 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
5140 instead of breakpoints. This should be
5141 safe for all but ARM7TDMI--S cores (like Philips LPC).
5142 This feature is enabled by default on most ARM9 cores,
5143 including ARM9TDMI, ARM920T, and ARM926EJ-S.
5146 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
5148 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
5149 amounts of memory. DCC downloads offer a huge speed increase, but might be
5150 unsafe, especially with targets running at very low speeds. This command was introduced
5151 with OpenOCD rev. 60, and requires a few bytes of working area.
5154 @anchor{arm7_9 fast_memory_access}
5155 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
5156 Enable or disable memory writes and reads that don't check completion of
5157 the operation. This provides a huge speed increase, especially with USB JTAG
5158 cables (FT2232), but might be unsafe if used with targets running at very low
5159 speeds, like the 32kHz startup clock of an AT91RM9200.
5162 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
5163 @emph{This is intended for use while debugging OpenOCD; you probably
5166 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
5167 as used in the specified @var{mode}
5168 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
5169 the M4..M0 bits of the PSR).
5170 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
5171 Register 16 is the mode-specific SPSR,
5172 unless the specified mode is 0xffffffff (32-bit all-ones)
5173 in which case register 16 is the CPSR.
5174 The write goes directly to the CPU, bypassing the register cache.
5177 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
5178 @emph{This is intended for use while debugging OpenOCD; you probably
5181 If the second parameter is zero, writes @var{word} to the
5182 Current Program Status register (CPSR).
5183 Else writes @var{word} to the current mode's Saved PSR (SPSR).
5184 In both cases, this bypasses the register cache.
5187 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
5188 @emph{This is intended for use while debugging OpenOCD; you probably
5191 Writes eight bits to the CPSR or SPSR,
5192 first rotating them by @math{2*rotate} bits,
5193 and bypassing the register cache.
5194 This has lower JTAG overhead than writing the entire CPSR or SPSR
5195 with @command{arm7_9 write_xpsr}.
5198 @subsection ARM720T specific commands
5201 These commands are available to ARM720T based CPUs,
5202 which are implementations of the ARMv4T architecture
5203 based on the ARM7TDMI-S integer core.
5204 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
5206 @deffn Command {arm720t cp15} regnum [value]
5207 Display cp15 register @var{regnum};
5208 else if a @var{value} is provided, that value is written to that register.
5211 @deffn Command {arm720t mdw_phys} addr [count]
5212 @deffnx Command {arm720t mdh_phys} addr [count]
5213 @deffnx Command {arm720t mdb_phys} addr [count]
5214 Display contents of physical address @var{addr}, as
5215 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5216 or 8-bit bytes (@command{mdb_phys}).
5217 If @var{count} is specified, displays that many units.
5220 @deffn Command {arm720t mww_phys} addr word
5221 @deffnx Command {arm720t mwh_phys} addr halfword
5222 @deffnx Command {arm720t mwb_phys} addr byte
5223 Writes the specified @var{word} (32 bits),
5224 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5225 at the specified physical address @var{addr}.
5228 @deffn Command {arm720t virt2phys} va
5229 Translate a virtual address @var{va} to a physical address
5230 and display the result.
5233 @subsection ARM9 specific commands
5236 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
5238 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
5240 For historical reasons, one command shared by these cores starts
5241 with the @command{arm9tdmi} prefix.
5242 This is true even for ARM9E based processors, which implement the
5243 ARMv5TE architecture instead of ARMv4T.
5245 @c 9-june-2009: tried this on arm920t, it didn't work.
5246 @c no-params always lists nothing caught, and that's how it acts.
5248 @anchor{arm9tdmi vector_catch}
5249 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
5250 @cindex vector_catch
5251 Vector Catch hardware provides a sort of dedicated breakpoint
5252 for hardware events such as reset, interrupt, and abort.
5253 You can use this to conserve normal breakpoint resources,
5254 so long as you're not concerned with code that branches directly
5255 to those hardware vectors.
5257 This always finishes by listing the current configuration.
5258 If parameters are provided, it first reconfigures the
5259 vector catch hardware to intercept
5260 @option{all} of the hardware vectors,
5261 @option{none} of them,
5262 or a list with one or more of the following:
5263 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
5264 @option{irq} @option{fiq}.
5267 @subsection ARM920T specific commands
5270 These commands are available to ARM920T based CPUs,
5271 which are implementations of the ARMv4T architecture
5272 built using the ARM9TDMI integer core.
5273 They are available in addition to the ARMv4/5, ARM7/ARM9,
5274 and ARM9TDMI commands.
5276 @deffn Command {arm920t cache_info}
5277 Print information about the caches found. This allows to see whether your target
5278 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
5281 @deffn Command {arm920t cp15} regnum [value]
5282 Display cp15 register @var{regnum};
5283 else if a @var{value} is provided, that value is written to that register.
5286 @deffn Command {arm920t cp15i} opcode [value [address]]
5287 Interpreted access using cp15 @var{opcode}.
5288 If no @var{value} is provided, the result is displayed.
5289 Else if that value is written using the specified @var{address},
5290 or using zero if no other address is not provided.
5293 @deffn Command {arm920t mdw_phys} addr [count]
5294 @deffnx Command {arm920t mdh_phys} addr [count]
5295 @deffnx Command {arm920t mdb_phys} addr [count]
5296 Display contents of physical address @var{addr}, as
5297 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5298 or 8-bit bytes (@command{mdb_phys}).
5299 If @var{count} is specified, displays that many units.
5302 @deffn Command {arm920t mww_phys} addr word
5303 @deffnx Command {arm920t mwh_phys} addr halfword
5304 @deffnx Command {arm920t mwb_phys} addr byte
5305 Writes the specified @var{word} (32 bits),
5306 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5307 at the specified physical address @var{addr}.
5310 @deffn Command {arm920t read_cache} filename
5311 Dump the content of ICache and DCache to a file named @file{filename}.
5314 @deffn Command {arm920t read_mmu} filename
5315 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5318 @deffn Command {arm920t virt2phys} va
5319 Translate a virtual address @var{va} to a physical address
5320 and display the result.
5323 @subsection ARM926ej-s specific commands
5326 These commands are available to ARM926ej-s based CPUs,
5327 which are implementations of the ARMv5TEJ architecture
5328 based on the ARM9EJ-S integer core.
5329 They are available in addition to the ARMv4/5, ARM7/ARM9,
5330 and ARM9TDMI commands.
5332 The Feroceon cores also support these commands, although
5333 they are not built from ARM926ej-s designs.
5335 @deffn Command {arm926ejs cache_info}
5336 Print information about the caches found.
5339 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
5340 Accesses cp15 register @var{regnum} using
5341 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
5342 If a @var{value} is provided, that value is written to that register.
5343 Else that register is read and displayed.
5346 @deffn Command {arm926ejs mdw_phys} addr [count]
5347 @deffnx Command {arm926ejs mdh_phys} addr [count]
5348 @deffnx Command {arm926ejs mdb_phys} addr [count]
5349 Display contents of physical address @var{addr}, as
5350 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5351 or 8-bit bytes (@command{mdb_phys}).
5352 If @var{count} is specified, displays that many units.
5355 @deffn Command {arm926ejs mww_phys} addr word
5356 @deffnx Command {arm926ejs mwh_phys} addr halfword
5357 @deffnx Command {arm926ejs mwb_phys} addr byte
5358 Writes the specified @var{word} (32 bits),
5359 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5360 at the specified physical address @var{addr}.
5363 @deffn Command {arm926ejs virt2phys} va
5364 Translate a virtual address @var{va} to a physical address
5365 and display the result.
5368 @subsection ARM966E specific commands
5371 These commands are available to ARM966 based CPUs,
5372 which are implementations of the ARMv5TE architecture.
5373 They are available in addition to the ARMv4/5, ARM7/ARM9,
5374 and ARM9TDMI commands.
5376 @deffn Command {arm966e cp15} regnum [value]
5377 Display cp15 register @var{regnum};
5378 else if a @var{value} is provided, that value is written to that register.
5381 @subsection XScale specific commands
5384 Some notes about the debug implementation on the XScale CPUs:
5386 The XScale CPU provides a special debug-only mini-instruction cache
5387 (mini-IC) in which exception vectors and target-resident debug handler
5388 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5389 must point vector 0 (the reset vector) to the entry of the debug
5390 handler. However, this means that the complete first cacheline in the
5391 mini-IC is marked valid, which makes the CPU fetch all exception
5392 handlers from the mini-IC, ignoring the code in RAM.
5394 OpenOCD currently does not sync the mini-IC entries with the RAM
5395 contents (which would fail anyway while the target is running), so
5396 the user must provide appropriate values using the @code{xscale
5397 vector_table} command.
5399 It is recommended to place a pc-relative indirect branch in the vector
5400 table, and put the branch destination somewhere in memory. Doing so
5401 makes sure the code in the vector table stays constant regardless of
5402 code layout in memory:
5405 ldr pc,[pc,#0x100-8]
5406 ldr pc,[pc,#0x100-8]
5407 ldr pc,[pc,#0x100-8]
5408 ldr pc,[pc,#0x100-8]
5409 ldr pc,[pc,#0x100-8]
5410 ldr pc,[pc,#0x100-8]
5411 ldr pc,[pc,#0x100-8]
5412 ldr pc,[pc,#0x100-8]
5414 .long real_reset_vector
5415 .long real_ui_handler
5416 .long real_swi_handler
5418 .long real_data_abort
5419 .long 0 /* unused */
5420 .long real_irq_handler
5421 .long real_fiq_handler
5424 The debug handler must be placed somewhere in the address space using
5425 the @code{xscale debug_handler} command. The allowed locations for the
5426 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5427 0xfffff800). The default value is 0xfe000800.
5430 These commands are available to XScale based CPUs,
5431 which are implementations of the ARMv5TE architecture.
5433 @deffn Command {xscale analyze_trace}
5434 Displays the contents of the trace buffer.
5437 @deffn Command {xscale cache_clean_address} address
5438 Changes the address used when cleaning the data cache.
5441 @deffn Command {xscale cache_info}
5442 Displays information about the CPU caches.
5445 @deffn Command {xscale cp15} regnum [value]
5446 Display cp15 register @var{regnum};
5447 else if a @var{value} is provided, that value is written to that register.
5450 @deffn Command {xscale debug_handler} target address
5451 Changes the address used for the specified target's debug handler.
5454 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5455 Enables or disable the CPU's data cache.
5458 @deffn Command {xscale dump_trace} filename
5459 Dumps the raw contents of the trace buffer to @file{filename}.
5462 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5463 Enables or disable the CPU's instruction cache.
5466 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5467 Enables or disable the CPU's memory management unit.
5470 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5471 Enables or disables the trace buffer,
5472 and controls how it is emptied.
5475 @deffn Command {xscale trace_image} filename [offset [type]]
5476 Opens a trace image from @file{filename}, optionally rebasing
5477 its segment addresses by @var{offset}.
5478 The image @var{type} may be one of
5479 @option{bin} (binary), @option{ihex} (Intel hex),
5480 @option{elf} (ELF file), @option{s19} (Motorola s19),
5481 @option{mem}, or @option{builder}.
5484 @anchor{xscale vector_catch}
5485 @deffn Command {xscale vector_catch} [mask]
5486 @cindex vector_catch
5487 Display a bitmask showing the hardware vectors to catch.
5488 If the optional parameter is provided, first set the bitmask to that value.
5490 The mask bits correspond with bit 16..23 in the DCSR:
5493 0x02 Trap Undefined Instructions
5494 0x04 Trap Software Interrupt
5495 0x08 Trap Prefetch Abort
5496 0x10 Trap Data Abort
5503 @anchor{xscale vector_table}
5504 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5505 @cindex vector_table
5507 Set an entry in the mini-IC vector table. There are two tables: one for
5508 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5509 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5510 points to the debug handler entry and can not be overwritten.
5511 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5513 Without arguments, the current settings are displayed.
5517 @section ARMv6 Architecture
5520 @subsection ARM11 specific commands
5523 @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
5524 Write @var{value} to a coprocessor @var{pX} register
5525 passing parameters @var{CRn},
5526 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5527 and the MCR instruction.
5528 (The difference beween this and the MCR2 instruction is
5529 one bit in the encoding, effecively a fifth parameter.)
5532 @deffn Command {arm11 memwrite burst} [value]
5533 Displays the value of the memwrite burst-enable flag,
5534 which is enabled by default.
5535 If @var{value} is defined, first assigns that.
5538 @deffn Command {arm11 memwrite error_fatal} [value]
5539 Displays the value of the memwrite error_fatal flag,
5540 which is enabled by default.
5541 If @var{value} is defined, first assigns that.
5544 @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
5545 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5546 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5547 and the MRC instruction.
5548 (The difference beween this and the MRC2 instruction is
5549 one bit in the encoding, effecively a fifth parameter.)
5550 Displays the result.
5553 @deffn Command {arm11 no_increment} [value]
5554 Displays the value of the flag controlling whether
5555 some read or write operations increment the pointer
5556 (the default behavior) or not (acting like a FIFO).
5557 If @var{value} is defined, first assigns that.
5560 @deffn Command {arm11 step_irq_enable} [value]
5561 Displays the value of the flag controlling whether
5562 IRQs are enabled during single stepping;
5563 they are disabled by default.
5564 If @var{value} is defined, first assigns that.
5567 @deffn Command {arm11 vcr} [value]
5568 @cindex vector_catch
5569 Displays the value of the @emph{Vector Catch Register (VCR)},
5570 coprocessor 14 register 7.
5571 If @var{value} is defined, first assigns that.
5573 Vector Catch hardware provides dedicated breakpoints
5574 for certain hardware events.
5575 The specific bit values are core-specific (as in fact is using
5576 coprocessor 14 register 7 itself) but all current ARM11
5577 cores @emph{except the ARM1176} use the same six bits.
5580 @section ARMv7 Architecture
5583 @subsection ARMv7 Debug Access Port (DAP) specific commands
5584 @cindex Debug Access Port
5586 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5587 included on cortex-m3 and cortex-a8 systems.
5588 They are available in addition to other core-specific commands that may be available.
5590 @deffn Command {dap info} [num]
5591 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5594 @deffn Command {dap apsel} [num]
5595 Select AP @var{num}, defaulting to 0.
5598 @deffn Command {dap apid} [num]
5599 Displays id register from AP @var{num},
5600 defaulting to the currently selected AP.
5603 @deffn Command {dap baseaddr} [num]
5604 Displays debug base address from AP @var{num},
5605 defaulting to the currently selected AP.
5608 @deffn Command {dap memaccess} [value]
5609 Displays the number of extra tck for mem-ap memory bus access [0-255].
5610 If @var{value} is defined, first assigns that.
5613 @subsection ARMv7-A specific commands
5616 @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
5618 Disassembles @var{count} instructions starting at @var{address}.
5619 If @var{count} is not specified, a single instruction is disassembled.
5620 If @option{thumb} is specified, or the low bit of the address is set,
5621 Thumb2 (mixed 16/32-bit) instructions are used;
5622 else ARM (32-bit) instructions are used.
5623 With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
5624 ThumbEE disassembly currently has no explicit support.
5625 (Processors may also support the Jazelle state, but
5626 those instructions are not currently understood by OpenOCD.)
5630 @subsection Cortex-M3 specific commands
5633 @deffn Command {cortex_m3 disassemble} address [count]
5635 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5636 If @var{count} is not specified, a single instruction is disassembled.
5639 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5640 Control masking (disabling) interrupts during target step/resume.
5643 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5644 @cindex vector_catch
5645 Vector Catch hardware provides dedicated breakpoints
5646 for certain hardware events.
5648 Parameters request interception of
5649 @option{all} of these hardware event vectors,
5650 @option{none} of them,
5651 or one or more of the following:
5652 @option{hard_err} for a HardFault exception;
5653 @option{mm_err} for a MemManage exception;
5654 @option{bus_err} for a BusFault exception;
5657 @option{chk_err}, or
5658 @option{nocp_err} for various UsageFault exceptions; or
5660 If NVIC setup code does not enable them,
5661 MemManage, BusFault, and UsageFault exceptions
5662 are mapped to HardFault.
5663 UsageFault checks for
5664 divide-by-zero and unaligned access
5665 must also be explicitly enabled.
5667 This finishes by listing the current vector catch configuration.
5670 @anchor{Software Debug Messages and Tracing}
5671 @section Software Debug Messages and Tracing
5672 @cindex Linux-ARM DCC support
5676 OpenOCD can process certain requests from target software. Currently
5677 @command{target_request debugmsgs}
5678 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5679 These messages are received as part of target polling, so
5680 you need to have @command{poll on} active to receive them.
5681 They are intrusive in that they will affect program execution
5682 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5684 See @file{libdcc} in the contrib dir for more details.
5685 In addition to sending strings, characters, and
5686 arrays of various size integers from the target,
5687 @file{libdcc} also exports a software trace point mechanism.
5688 The target being debugged may
5689 issue trace messages which include a 24-bit @dfn{trace point} number.
5690 Trace point support includes two distinct mechanisms,
5691 each supported by a command:
5694 @item @emph{History} ... A circular buffer of trace points
5695 can be set up, and then displayed at any time.
5696 This tracks where code has been, which can be invaluable in
5697 finding out how some fault was triggered.
5699 The buffer may overflow, since it collects records continuously.
5700 It may be useful to use some of the 24 bits to represent a
5701 particular event, and other bits to hold data.
5703 @item @emph{Counting} ... An array of counters can be set up,
5704 and then displayed at any time.
5705 This can help establish code coverage and identify hot spots.
5707 The array of counters is directly indexed by the trace point
5708 number, so trace points with higher numbers are not counted.
5711 Linux-ARM kernels have a ``Kernel low-level debugging
5712 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5713 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5714 deliver messages before a serial console can be activated.
5715 This is not the same format used by @file{libdcc}.
5716 Other software, such as the U-Boot boot loader, sometimes
5717 does the same thing.
5719 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5720 Displays current handling of target DCC message requests.
5721 These messages may be sent to the debugger while the target is running.
5722 The optional @option{enable} and @option{charmsg} parameters
5723 both enable the messages, while @option{disable} disables them.
5725 With @option{charmsg} the DCC words each contain one character,
5726 as used by Linux with CONFIG_DEBUG_ICEDCC;
5727 otherwise the libdcc format is used.
5730 @deffn Command {trace history} [@option{clear}|count]
5731 With no parameter, displays all the trace points that have triggered
5732 in the order they triggered.
5733 With the parameter @option{clear}, erases all current trace history records.
5734 With a @var{count} parameter, allocates space for that many
5738 @deffn Command {trace point} [@option{clear}|identifier]
5739 With no parameter, displays all trace point identifiers and how many times
5740 they have been triggered.
5741 With the parameter @option{clear}, erases all current trace point counters.
5742 With a numeric @var{identifier} parameter, creates a new a trace point counter
5743 and associates it with that identifier.
5745 @emph{Important:} The identifier and the trace point number
5746 are not related except by this command.
5747 These trace point numbers always start at zero (from server startup,
5748 or after @command{trace point clear}) and count up from there.
5753 @chapter JTAG Commands
5754 @cindex JTAG Commands
5755 Most general purpose JTAG commands have been presented earlier.
5756 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5757 Lower level JTAG commands, as presented here,
5758 may be needed to work with targets which require special
5759 attention during operations such as reset or initialization.
5761 To use these commands you will need to understand some
5762 of the basics of JTAG, including:
5765 @item A JTAG scan chain consists of a sequence of individual TAP
5766 devices such as a CPUs.
5767 @item Control operations involve moving each TAP through the same
5768 standard state machine (in parallel)
5769 using their shared TMS and clock signals.
5770 @item Data transfer involves shifting data through the chain of
5771 instruction or data registers of each TAP, writing new register values
5772 while the reading previous ones.
5773 @item Data register sizes are a function of the instruction active in
5774 a given TAP, while instruction register sizes are fixed for each TAP.
5775 All TAPs support a BYPASS instruction with a single bit data register.
5776 @item The way OpenOCD differentiates between TAP devices is by
5777 shifting different instructions into (and out of) their instruction
5781 @section Low Level JTAG Commands
5783 These commands are used by developers who need to access
5784 JTAG instruction or data registers, possibly controlling
5785 the order of TAP state transitions.
5786 If you're not debugging OpenOCD internals, or bringing up a
5787 new JTAG adapter or a new type of TAP device (like a CPU or
5788 JTAG router), you probably won't need to use these commands.
5790 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5791 Loads the data register of @var{tap} with a series of bit fields
5792 that specify the entire register.
5793 Each field is @var{numbits} bits long with
5794 a numeric @var{value} (hexadecimal encouraged).
5795 The return value holds the original value of each
5798 For example, a 38 bit number might be specified as one
5799 field of 32 bits then one of 6 bits.
5800 @emph{For portability, never pass fields which are more
5801 than 32 bits long. Many OpenOCD implementations do not
5802 support 64-bit (or larger) integer values.}
5804 All TAPs other than @var{tap} must be in BYPASS mode.
5805 The single bit in their data registers does not matter.
5807 When @var{tap_state} is specified, the JTAG state machine is left
5809 For example @sc{drpause} might be specified, so that more
5810 instructions can be issued before re-entering the @sc{run/idle} state.
5811 If the end state is not specified, the @sc{run/idle} state is entered.
5814 OpenOCD does not record information about data register lengths,
5815 so @emph{it is important that you get the bit field lengths right}.
5816 Remember that different JTAG instructions refer to different
5817 data registers, which may have different lengths.
5818 Moreover, those lengths may not be fixed;
5819 the SCAN_N instruction can change the length of
5820 the register accessed by the INTEST instruction
5821 (by connecting a different scan chain).
5825 @deffn Command {flush_count}
5826 Returns the number of times the JTAG queue has been flushed.
5827 This may be used for performance tuning.
5829 For example, flushing a queue over USB involves a
5830 minimum latency, often several milliseconds, which does
5831 not change with the amount of data which is written.
5832 You may be able to identify performance problems by finding
5833 tasks which waste bandwidth by flushing small transfers too often,
5834 instead of batching them into larger operations.
5837 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5838 For each @var{tap} listed, loads the instruction register
5839 with its associated numeric @var{instruction}.
5840 (The number of bits in that instruction may be displayed
5841 using the @command{scan_chain} command.)
5842 For other TAPs, a BYPASS instruction is loaded.
5844 When @var{tap_state} is specified, the JTAG state machine is left
5846 For example @sc{irpause} might be specified, so the data register
5847 can be loaded before re-entering the @sc{run/idle} state.
5848 If the end state is not specified, the @sc{run/idle} state is entered.
5851 OpenOCD currently supports only a single field for instruction
5852 register values, unlike data register values.
5853 For TAPs where the instruction register length is more than 32 bits,
5854 portable scripts currently must issue only BYPASS instructions.
5858 @deffn Command {jtag_reset} trst srst
5859 Set values of reset signals.
5860 The @var{trst} and @var{srst} parameter values may be
5861 @option{0}, indicating that reset is inactive (pulled or driven high),
5862 or @option{1}, indicating it is active (pulled or driven low).
5863 The @command{reset_config} command should already have been used
5864 to configure how the board and JTAG adapter treat these two
5865 signals, and to say if either signal is even present.
5866 @xref{Reset Configuration}.
5869 @deffn Command {runtest} @var{num_cycles}
5870 Move to the @sc{run/idle} state, and execute at least
5871 @var{num_cycles} of the JTAG clock (TCK).
5872 Instructions often need some time
5873 to execute before they take effect.
5876 @c tms_sequence (short|long)
5877 @c ... temporary, debug-only, probably gone before 0.2 ships
5879 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5880 Verify values captured during @sc{ircapture} and returned
5881 during IR scans. Default is enabled, but this can be
5882 overridden by @command{verify_jtag}.
5885 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5886 Enables verification of DR and IR scans, to help detect
5887 programming errors. For IR scans, @command{verify_ircapture}
5888 must also be enabled.
5892 @section TAP state names
5893 @cindex TAP state names
5895 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5896 and @command{irscan} commands are:
5899 @item @b{RESET} ... should act as if TRST were active
5900 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5903 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5905 @item @b{DRPAUSE} ... data register ready for update or more shifting
5910 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5912 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5917 Note that only six of those states are fully ``stable'' in the
5918 face of TMS fixed (low except for @sc{reset})
5919 and a free-running JTAG clock. For all the
5920 others, the next TCK transition changes to a new state.
5923 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5924 produce side effects by changing register contents. The values
5925 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5926 may not be as expected.
5927 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5928 choices after @command{drscan} or @command{irscan} commands,
5929 since they are free of JTAG side effects.
5930 However, @sc{run/idle} may have side effects that appear at other
5931 levels, such as advancing the ARM9E-S instruction pipeline.
5932 Consult the documentation for the TAP(s) you are working with.
5935 @node Boundary Scan Commands
5936 @chapter Boundary Scan Commands
5938 One of the original purposes of JTAG was to support
5939 boundary scan based hardware testing.
5940 Although its primary focus is to support On-Chip Debugging,
5941 OpenOCD also includes some boundary scan commands.
5943 @section SVF: Serial Vector Format
5944 @cindex Serial Vector Format
5947 The Serial Vector Format, better known as @dfn{SVF}, is a
5948 way to represent JTAG test patterns in text files.
5949 OpenOCD supports running such test files.
5951 @deffn Command {svf} filename [@option{quiet}]
5952 This issues a JTAG reset (Test-Logic-Reset) and then
5953 runs the SVF script from @file{filename}.
5954 Unless the @option{quiet} option is specified,
5955 each command is logged before it is executed.
5958 @section XSVF: Xilinx Serial Vector Format
5959 @cindex Xilinx Serial Vector Format
5962 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
5963 binary representation of SVF which is optimized for use with
5965 OpenOCD supports running such test files.
5967 @quotation Important
5968 Not all XSVF commands are supported.
5971 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
5972 This issues a JTAG reset (Test-Logic-Reset) and then
5973 runs the XSVF script from @file{filename}.
5974 When a @var{tapname} is specified, the commands are directed at
5976 When @option{virt2} is specified, the @sc{xruntest} command counts
5977 are interpreted as TCK cycles instead of microseconds.
5978 Unless the @option{quiet} option is specified,
5979 messages are logged for comments and some retries.
5985 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5986 be used to access files on PCs (either the developer's PC or some other PC).
5988 The way this works on the ZY1000 is to prefix a filename by
5989 "/tftp/ip/" and append the TFTP path on the TFTP
5990 server (tftpd). For example,
5993 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5996 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5997 if the file was hosted on the embedded host.
5999 In order to achieve decent performance, you must choose a TFTP server
6000 that supports a packet size bigger than the default packet size (512 bytes). There
6001 are numerous TFTP servers out there (free and commercial) and you will have to do
6002 a bit of googling to find something that fits your requirements.
6004 @node GDB and OpenOCD
6005 @chapter GDB and OpenOCD
6007 OpenOCD complies with the remote gdbserver protocol, and as such can be used
6008 to debug remote targets.
6010 @anchor{Connecting to GDB}
6011 @section Connecting to GDB
6012 @cindex Connecting to GDB
6013 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
6014 instance GDB 6.3 has a known bug that produces bogus memory access
6015 errors, which has since been fixed: look up 1836 in
6016 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
6018 OpenOCD can communicate with GDB in two ways:
6022 A socket (TCP/IP) connection is typically started as follows:
6024 target remote localhost:3333
6026 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
6028 A pipe connection is typically started as follows:
6030 target remote | openocd --pipe
6032 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
6033 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
6037 To list the available OpenOCD commands type @command{monitor help} on the
6040 OpenOCD supports the gdb @option{qSupported} packet, this enables information
6041 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
6042 packet size and the device's memory map.
6044 Previous versions of OpenOCD required the following GDB options to increase
6045 the packet size and speed up GDB communication:
6047 set remote memory-write-packet-size 1024
6048 set remote memory-write-packet-size fixed
6049 set remote memory-read-packet-size 1024
6050 set remote memory-read-packet-size fixed
6052 This is now handled in the @option{qSupported} PacketSize and should not be required.
6054 @section Programming using GDB
6055 @cindex Programming using GDB
6057 By default the target memory map is sent to GDB. This can be disabled by
6058 the following OpenOCD configuration option:
6060 gdb_memory_map disable
6062 For this to function correctly a valid flash configuration must also be set
6063 in OpenOCD. For faster performance you should also configure a valid
6066 Informing GDB of the memory map of the target will enable GDB to protect any
6067 flash areas of the target and use hardware breakpoints by default. This means
6068 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
6069 using a memory map. @xref{gdb_breakpoint_override}.
6071 To view the configured memory map in GDB, use the GDB command @option{info mem}
6072 All other unassigned addresses within GDB are treated as RAM.
6074 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
6075 This can be changed to the old behaviour by using the following GDB command
6077 set mem inaccessible-by-default off
6080 If @command{gdb_flash_program enable} is also used, GDB will be able to
6081 program any flash memory using the vFlash interface.
6083 GDB will look at the target memory map when a load command is given, if any
6084 areas to be programmed lie within the target flash area the vFlash packets
6087 If the target needs configuring before GDB programming, an event
6088 script can be executed:
6090 $_TARGETNAME configure -event EVENTNAME BODY
6093 To verify any flash programming the GDB command @option{compare-sections}
6096 @node Tcl Scripting API
6097 @chapter Tcl Scripting API
6098 @cindex Tcl Scripting API
6102 The commands are stateless. E.g. the telnet command line has a concept
6103 of currently active target, the Tcl API proc's take this sort of state
6104 information as an argument to each proc.
6106 There are three main types of return values: single value, name value
6107 pair list and lists.
6109 Name value pair. The proc 'foo' below returns a name/value pair
6115 > set foo(you) Oyvind
6116 > set foo(mouse) Micky
6117 > set foo(duck) Donald
6125 me Duane you Oyvind mouse Micky duck Donald
6127 Thus, to get the names of the associative array is easy:
6129 foreach { name value } [set foo] {
6130 puts "Name: $name, Value: $value"
6134 Lists returned must be relatively small. Otherwise a range
6135 should be passed in to the proc in question.
6137 @section Internal low-level Commands
6139 By low-level, the intent is a human would not directly use these commands.
6141 Low-level commands are (should be) prefixed with "ocd_", e.g.
6142 @command{ocd_flash_banks}
6143 is the low level API upon which @command{flash banks} is implemented.
6146 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6148 Read memory and return as a Tcl array for script processing
6149 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6151 Convert a Tcl array to memory locations and write the values
6152 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
6154 Return information about the flash banks
6157 OpenOCD commands can consist of two words, e.g. "flash banks". The
6158 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
6159 called "flash_banks".
6161 @section OpenOCD specific Global Variables
6165 Real Tcl has ::tcl_platform(), and platform::identify, and many other
6166 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
6167 holds one of the following values:
6170 @item @b{winxx} Built using Microsoft Visual Studio
6171 @item @b{linux} Linux is the underlying operating sytem
6172 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
6173 @item @b{cygwin} Running under Cygwin
6174 @item @b{mingw32} Running under MingW32
6175 @item @b{other} Unknown, none of the above.
6178 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
6181 We should add support for a variable like Tcl variable
6182 @code{tcl_platform(platform)}, it should be called
6183 @code{jim_platform} (because it
6184 is jim, not real tcl).
6188 @chapter Deprecated/Removed Commands
6189 @cindex Deprecated/Removed Commands
6190 Certain OpenOCD commands have been deprecated or
6191 removed during the various revisions.
6193 Upgrade your scripts as soon as possible.
6194 These descriptions for old commands may be removed
6195 a year after the command itself was removed.
6196 This means that in January 2010 this chapter may
6197 become much shorter.
6200 @item @b{arm7_9 fast_writes}
6201 @cindex arm7_9 fast_writes
6202 @*Use @command{arm7_9 fast_memory_access} instead.
6203 @xref{arm7_9 fast_memory_access}.
6206 @*An buggy old command that would not really work since background polling would wipe out the global endstate
6207 @item @b{arm7_9 force_hw_bkpts}
6208 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
6209 for flash if the GDB memory map has been set up(default when flash is declared in
6210 target configuration). @xref{gdb_breakpoint_override}.
6211 @item @b{arm7_9 sw_bkpts}
6212 @*On by default. @xref{gdb_breakpoint_override}.
6213 @item @b{daemon_startup}
6214 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
6215 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
6216 and @option{target cortex_m3 little reset_halt 0}.
6217 @item @b{dump_binary}
6218 @*use @option{dump_image} command with same args. @xref{dump_image}.
6219 @item @b{flash erase}
6220 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
6221 @item @b{flash write}
6222 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6223 @item @b{flash write_binary}
6224 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6225 @item @b{flash auto_erase}
6226 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
6228 @item @b{jtag_device}
6229 @*use the @command{jtag newtap} command, converting from positional syntax
6230 to named prefixes, and naming the TAP.
6232 Note that if you try to use the old command, a message will tell you the
6233 right new command to use; and that the fourth parameter in the old syntax
6234 was never actually used.
6236 OLD: jtag_device 8 0x01 0xe3 0xfe
6237 NEW: jtag newtap CHIPNAME TAPNAME \
6238 -irlen 8 -ircapture 0x01 -irmask 0xe3
6241 @item @b{jtag_speed} value
6242 @*@xref{JTAG Speed}.
6243 Usually, a value of zero means maximum
6244 speed. The actual effect of this option depends on the JTAG interface used.
6246 @item wiggler: maximum speed / @var{number}
6247 @item ft2232: 6MHz / (@var{number}+1)
6248 @item amt jtagaccel: 8 / 2**@var{number}
6249 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
6250 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
6251 @comment end speed list.
6254 @item @b{load_binary}
6255 @*use @option{load_image} command with same args. @xref{load_image}.
6256 @item @b{run_and_halt_time}
6257 @*This command has been removed for simpler reset behaviour, it can be simulated with the
6264 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
6265 @*use the create subcommand of @option{target}.
6266 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
6267 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
6268 @item @b{working_area}
6269 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
6277 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
6279 @cindex adaptive clocking
6282 In digital circuit design it is often refered to as ``clock
6283 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
6284 operating at some speed, your target is operating at another. The two
6285 clocks are not synchronised, they are ``asynchronous''
6287 In order for the two to work together they must be synchronised. Otherwise
6288 the two systems will get out of sync with each other and nothing will
6289 work. There are 2 basic options:
6292 Use a special circuit.
6294 One clock must be some multiple slower than the other.
6297 @b{Does this really matter?} For some chips and some situations, this
6298 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6299 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6300 program/enable the oscillators and eventually the main clock. It is in
6301 those critical times you must slow the JTAG clock to sometimes 1 to
6304 Imagine debugging a 500MHz ARM926 hand held battery powered device
6305 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6308 @b{Solution #1 - A special circuit}
6310 In order to make use of this, your JTAG dongle must support the RTCK
6311 feature. Not all dongles support this - keep reading!
6313 The RTCK signal often found in some ARM chips is used to help with
6314 this problem. ARM has a good description of the problem described at
6315 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6316 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6317 work? / how does adaptive clocking work?''.
6319 The nice thing about adaptive clocking is that ``battery powered hand
6320 held device example'' - the adaptiveness works perfectly all the
6321 time. One can set a break point or halt the system in the deep power
6322 down code, slow step out until the system speeds up.
6324 Note that adaptive clocking may also need to work at the board level,
6325 when a board-level scan chain has multiple chips.
6326 Parallel clock voting schemes are good way to implement this,
6327 both within and between chips, and can easily be implemented
6329 It's not difficult to have logic fan a module's input TCK signal out
6330 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6331 back with the right polarity before changing the output RTCK signal.
6332 Texas Instruments makes some clock voting logic available
6333 for free (with no support) in VHDL form; see
6334 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6336 @b{Solution #2 - Always works - but may be slower}
6338 Often this is a perfectly acceptable solution.
6340 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6341 the target clock speed. But what that ``magic division'' is varies
6342 depending on the chips on your board.
6343 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6344 ARM11 cores use an 8:1 division.
6345 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6347 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6349 You can still debug the 'low power' situations - you just need to
6350 manually adjust the clock speed at every step. While painful and
6351 tedious, it is not always practical.
6353 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6354 have a special debug mode in your application that does a ``high power
6355 sleep''. If you are careful - 98% of your problems can be debugged
6358 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6359 operation in your idle loops even if you don't otherwise change the CPU
6361 That operation gates the CPU clock, and thus the JTAG clock; which
6362 prevents JTAG access. One consequence is not being able to @command{halt}
6363 cores which are executing that @emph{wait for interrupt} operation.
6365 To set the JTAG frequency use the command:
6373 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6375 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6376 around Windows filenames.
6389 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6391 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6392 claims to come with all the necessary DLLs. When using Cygwin, try launching
6393 OpenOCD from the Cygwin shell.
6395 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6396 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6397 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6399 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6400 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6401 software breakpoints consume one of the two available hardware breakpoints.
6403 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6405 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6406 clock at the time you're programming the flash. If you've specified the crystal's
6407 frequency, make sure the PLL is disabled. If you've specified the full core speed
6408 (e.g. 60MHz), make sure the PLL is enabled.
6410 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6411 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6412 out while waiting for end of scan, rtck was disabled".
6414 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6415 settings in your PC BIOS (ECP, EPP, and different versions of those).
6417 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6418 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6419 memory read caused data abort".
6421 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6422 beyond the last valid frame. It might be possible to prevent this by setting up
6423 a proper "initial" stack frame, if you happen to know what exactly has to
6424 be done, feel free to add this here.
6426 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6427 stack before calling main(). What GDB is doing is ``climbing'' the run
6428 time stack by reading various values on the stack using the standard
6429 call frame for the target. GDB keeps going - until one of 2 things
6430 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6431 stackframes have been processed. By pushing zeros on the stack, GDB
6434 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6435 your C code, do the same - artifically push some zeros onto the stack,
6436 remember to pop them off when the ISR is done.
6438 @b{Also note:} If you have a multi-threaded operating system, they
6439 often do not @b{in the intrest of saving memory} waste these few
6443 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6444 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6446 This warning doesn't indicate any serious problem, as long as you don't want to
6447 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6448 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6449 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6450 independently. With this setup, it's not possible to halt the core right out of
6451 reset, everything else should work fine.
6453 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6454 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6455 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6456 quit with an error message. Is there a stability issue with OpenOCD?
6458 No, this is not a stability issue concerning OpenOCD. Most users have solved
6459 this issue by simply using a self-powered USB hub, which they connect their
6460 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6461 supply stable enough for the Amontec JTAGkey to be operated.
6463 @b{Laptops running on battery have this problem too...}
6465 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6466 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6467 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6468 What does that mean and what might be the reason for this?
6470 First of all, the reason might be the USB power supply. Try using a self-powered
6471 hub instead of a direct connection to your computer. Secondly, the error code 4
6472 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6473 chip ran into some sort of error - this points us to a USB problem.
6475 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6476 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6477 What does that mean and what might be the reason for this?
6479 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6480 has closed the connection to OpenOCD. This might be a GDB issue.
6482 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6483 are described, there is a parameter for specifying the clock frequency
6484 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6485 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6486 specified in kilohertz. However, I do have a quartz crystal of a
6487 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6488 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6491 No. The clock frequency specified here must be given as an integral number.
6492 However, this clock frequency is used by the In-Application-Programming (IAP)
6493 routines of the LPC2000 family only, which seems to be very tolerant concerning
6494 the given clock frequency, so a slight difference between the specified clock
6495 frequency and the actual clock frequency will not cause any trouble.
6497 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6499 Well, yes and no. Commands can be given in arbitrary order, yet the
6500 devices listed for the JTAG scan chain must be given in the right
6501 order (jtag newdevice), with the device closest to the TDO-Pin being
6502 listed first. In general, whenever objects of the same type exist
6503 which require an index number, then these objects must be given in the
6504 right order (jtag newtap, targets and flash banks - a target
6505 references a jtag newtap and a flash bank references a target).
6507 You can use the ``scan_chain'' command to verify and display the tap order.
6509 Also, some commands can't execute until after @command{init} has been
6510 processed. Such commands include @command{nand probe} and everything
6511 else that needs to write to controller registers, perhaps for setting
6512 up DRAM and loading it with code.
6514 @anchor{FAQ TAP Order}
6515 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6518 Yes; whenever you have more than one, you must declare them in
6519 the same order used by the hardware.
6521 Many newer devices have multiple JTAG TAPs. For example: ST
6522 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6523 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6524 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6525 connected to the boundary scan TAP, which then connects to the
6526 Cortex-M3 TAP, which then connects to the TDO pin.
6528 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6529 (2) The boundary scan TAP. If your board includes an additional JTAG
6530 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6531 place it before or after the STM32 chip in the chain. For example:
6534 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6535 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6536 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6537 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6538 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6541 The ``jtag device'' commands would thus be in the order shown below. Note:
6544 @item jtag newtap Xilinx tap -irlen ...
6545 @item jtag newtap stm32 cpu -irlen ...
6546 @item jtag newtap stm32 bs -irlen ...
6547 @item # Create the debug target and say where it is
6548 @item target create stm32.cpu -chain-position stm32.cpu ...
6552 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6553 log file, I can see these error messages: Error: arm7_9_common.c:561
6554 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6560 @node Tcl Crash Course
6561 @chapter Tcl Crash Course
6564 Not everyone knows Tcl - this is not intended to be a replacement for
6565 learning Tcl, the intent of this chapter is to give you some idea of
6566 how the Tcl scripts work.
6568 This chapter is written with two audiences in mind. (1) OpenOCD users
6569 who need to understand a bit more of how JIM-Tcl works so they can do
6570 something useful, and (2) those that want to add a new command to
6573 @section Tcl Rule #1
6574 There is a famous joke, it goes like this:
6576 @item Rule #1: The wife is always correct
6577 @item Rule #2: If you think otherwise, See Rule #1
6580 The Tcl equal is this:
6583 @item Rule #1: Everything is a string
6584 @item Rule #2: If you think otherwise, See Rule #1
6587 As in the famous joke, the consequences of Rule #1 are profound. Once
6588 you understand Rule #1, you will understand Tcl.
6590 @section Tcl Rule #1b
6591 There is a second pair of rules.
6593 @item Rule #1: Control flow does not exist. Only commands
6594 @* For example: the classic FOR loop or IF statement is not a control
6595 flow item, they are commands, there is no such thing as control flow
6597 @item Rule #2: If you think otherwise, See Rule #1
6598 @* Actually what happens is this: There are commands that by
6599 convention, act like control flow key words in other languages. One of
6600 those commands is the word ``for'', another command is ``if''.
6603 @section Per Rule #1 - All Results are strings
6604 Every Tcl command results in a string. The word ``result'' is used
6605 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
6606 Everything is a string}
6608 @section Tcl Quoting Operators
6609 In life of a Tcl script, there are two important periods of time, the
6610 difference is subtle.
6613 @item Evaluation Time
6616 The two key items here are how ``quoted things'' work in Tcl. Tcl has
6617 three primary quoting constructs, the [square-brackets] the
6618 @{curly-braces@} and ``double-quotes''
6620 By now you should know $VARIABLES always start with a $DOLLAR
6621 sign. BTW: To set a variable, you actually use the command ``set'', as
6622 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
6623 = 1'' statement, but without the equal sign.
6626 @item @b{[square-brackets]}
6627 @* @b{[square-brackets]} are command substitutions. It operates much
6628 like Unix Shell `back-ticks`. The result of a [square-bracket]
6629 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6630 string}. These two statements are roughly identical:
6634 echo "The Date is: $X"
6637 puts "The Date is: $X"
6639 @item @b{``double-quoted-things''}
6640 @* @b{``double-quoted-things''} are just simply quoted
6641 text. $VARIABLES and [square-brackets] are expanded in place - the
6642 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6646 puts "It is now \"[date]\", $x is in 1 hour"
6648 @item @b{@{Curly-Braces@}}
6649 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6650 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6651 'single-quote' operators in BASH shell scripts, with the added
6652 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6653 nested 3 times@}@}@} NOTE: [date] is a bad example;
6654 at this writing, Jim/OpenOCD does not have a date command.
6657 @section Consequences of Rule 1/2/3/4
6659 The consequences of Rule 1 are profound.
6661 @subsection Tokenisation & Execution.
6663 Of course, whitespace, blank lines and #comment lines are handled in
6666 As a script is parsed, each (multi) line in the script file is
6667 tokenised and according to the quoting rules. After tokenisation, that
6668 line is immedatly executed.
6670 Multi line statements end with one or more ``still-open''
6671 @{curly-braces@} which - eventually - closes a few lines later.
6673 @subsection Command Execution
6675 Remember earlier: There are no ``control flow''
6676 statements in Tcl. Instead there are COMMANDS that simply act like
6677 control flow operators.
6679 Commands are executed like this:
6682 @item Parse the next line into (argc) and (argv[]).
6683 @item Look up (argv[0]) in a table and call its function.
6684 @item Repeat until End Of File.
6687 It sort of works like this:
6690 ReadAndParse( &argc, &argv );
6692 cmdPtr = LookupCommand( argv[0] );
6694 (*cmdPtr->Execute)( argc, argv );
6698 When the command ``proc'' is parsed (which creates a procedure
6699 function) it gets 3 parameters on the command line. @b{1} the name of
6700 the proc (function), @b{2} the list of parameters, and @b{3} the body
6701 of the function. Not the choice of words: LIST and BODY. The PROC
6702 command stores these items in a table somewhere so it can be found by
6705 @subsection The FOR command
6707 The most interesting command to look at is the FOR command. In Tcl,
6708 the FOR command is normally implemented in C. Remember, FOR is a
6709 command just like any other command.
6711 When the ascii text containing the FOR command is parsed, the parser
6712 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6716 @item The ascii text 'for'
6717 @item The start text
6718 @item The test expression
6723 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6724 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6725 Often many of those parameters are in @{curly-braces@} - thus the
6726 variables inside are not expanded or replaced until later.
6728 Remember that every Tcl command looks like the classic ``main( argc,
6729 argv )'' function in C. In JimTCL - they actually look like this:
6733 MyCommand( Jim_Interp *interp,
6735 Jim_Obj * const *argvs );
6738 Real Tcl is nearly identical. Although the newer versions have
6739 introduced a byte-code parser and intepreter, but at the core, it
6740 still operates in the same basic way.
6742 @subsection FOR command implementation
6744 To understand Tcl it is perhaps most helpful to see the FOR
6745 command. Remember, it is a COMMAND not a control flow structure.
6747 In Tcl there are two underlying C helper functions.
6749 Remember Rule #1 - You are a string.
6751 The @b{first} helper parses and executes commands found in an ascii
6752 string. Commands can be seperated by semicolons, or newlines. While
6753 parsing, variables are expanded via the quoting rules.
6755 The @b{second} helper evaluates an ascii string as a numerical
6756 expression and returns a value.
6758 Here is an example of how the @b{FOR} command could be
6759 implemented. The pseudo code below does not show error handling.
6761 void Execute_AsciiString( void *interp, const char *string );
6763 int Evaluate_AsciiExpression( void *interp, const char *string );
6766 MyForCommand( void *interp,
6771 SetResult( interp, "WRONG number of parameters");
6775 // argv[0] = the ascii string just like C
6777 // Execute the start statement.
6778 Execute_AsciiString( interp, argv[1] );
6782 i = Evaluate_AsciiExpression(interp, argv[2]);
6787 Execute_AsciiString( interp, argv[3] );
6789 // Execute the LOOP part
6790 Execute_AsciiString( interp, argv[4] );
6794 SetResult( interp, "" );
6799 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6800 in the same basic way.
6802 @section OpenOCD Tcl Usage
6804 @subsection source and find commands
6805 @b{Where:} In many configuration files
6806 @* Example: @b{ source [find FILENAME] }
6807 @*Remember the parsing rules
6809 @item The FIND command is in square brackets.
6810 @* The FIND command is executed with the parameter FILENAME. It should
6811 find the full path to the named file. The RESULT is a string, which is
6812 substituted on the orginal command line.
6813 @item The command source is executed with the resulting filename.
6814 @* SOURCE reads a file and executes as a script.
6816 @subsection format command
6817 @b{Where:} Generally occurs in numerous places.
6818 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6824 puts [format "The answer: %d" [expr $x * $y]]
6827 @item The SET command creates 2 variables, X and Y.
6828 @item The double [nested] EXPR command performs math
6829 @* The EXPR command produces numerical result as a string.
6831 @item The format command is executed, producing a single string
6832 @* Refer to Rule #1.
6833 @item The PUTS command outputs the text.
6835 @subsection Body or Inlined Text
6836 @b{Where:} Various TARGET scripts.
6839 proc someproc @{@} @{
6840 ... multiple lines of stuff ...
6842 $_TARGETNAME configure -event FOO someproc
6843 #2 Good - no variables
6844 $_TARGETNAME confgure -event foo "this ; that;"
6845 #3 Good Curly Braces
6846 $_TARGETNAME configure -event FOO @{
6849 #4 DANGER DANGER DANGER
6850 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6853 @item The $_TARGETNAME is an OpenOCD variable convention.
6854 @*@b{$_TARGETNAME} represents the last target created, the value changes
6855 each time a new target is created. Remember the parsing rules. When
6856 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6857 the name of the target which happens to be a TARGET (object)
6859 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6860 @*There are 4 examples:
6862 @item The TCLBODY is a simple string that happens to be a proc name
6863 @item The TCLBODY is several simple commands seperated by semicolons
6864 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6865 @item The TCLBODY is a string with variables that get expanded.
6868 In the end, when the target event FOO occurs the TCLBODY is
6869 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6870 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6872 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6873 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6874 and the text is evaluated. In case #4, they are replaced before the
6875 ``Target Object Command'' is executed. This occurs at the same time
6876 $_TARGETNAME is replaced. In case #4 the date will never
6877 change. @{BTW: [date] is a bad example; at this writing,
6878 Jim/OpenOCD does not have a date command@}
6880 @subsection Global Variables
6881 @b{Where:} You might discover this when writing your own procs @* In
6882 simple terms: Inside a PROC, if you need to access a global variable
6883 you must say so. See also ``upvar''. Example:
6885 proc myproc @{ @} @{
6886 set y 0 #Local variable Y
6887 global x #Global variable X
6888 puts [format "X=%d, Y=%d" $x $y]
6891 @section Other Tcl Hacks
6892 @b{Dynamic variable creation}
6894 # Dynamically create a bunch of variables.
6895 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6897 set vn [format "BIT%d" $x]
6901 set $vn [expr (1 << $x)]
6904 @b{Dynamic proc/command creation}
6906 # One "X" function - 5 uart functions.
6907 foreach who @{A B C D E@}
6908 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6912 @node Target Library
6913 @chapter Target Library
6914 @cindex Target Library
6916 OpenOCD comes with a target configuration script library. These scripts can be
6917 used as-is or serve as a starting point.
6919 The target library is published together with the OpenOCD executable and
6920 the path to the target library is in the OpenOCD script search path.
6921 Similarly there are example scripts for configuring the JTAG interface.
6923 The command line below uses the example parport configuration script
6924 that ship with OpenOCD, then configures the str710.cfg target and
6925 finally issues the init and reset commands. The communication speed
6926 is set to 10kHz for reset and 8MHz for post reset.
6929 openocd -f interface/parport.cfg -f target/str710.cfg \
6930 -c "init" -c "reset"
6933 To list the target scripts available:
6936 $ ls /usr/local/lib/openocd/target
6938 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6939 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6940 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6941 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6946 @node OpenOCD Concept Index
6947 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6948 @comment case issue with ``Index.html'' and ``index.html''
6949 @comment Occurs when creating ``--html --no-split'' output
6950 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6951 @unnumbered OpenOCD Concept Index
6955 @node Command and Driver Index
6956 @unnumbered Command and Driver Index