1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
29 Permission is granted to copy, distribute and/or modify this document
30 under the terms of the GNU Free Documentation License, Version 1.2 or
31 any later version published by the Free Software Foundation; with no
32 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
33 Texts. A copy of the license is included in the section entitled ``GNU
34 Free Documentation License''.
39 @titlefont{@emph{Open On-Chip Debugger:}}
41 @title OpenOCD User's Guide
42 @subtitle for release @value{VERSION}
43 @subtitle @value{UPDATED}
46 @vskip 0pt plus 1filll
55 @top OpenOCD User's Guide
61 * About:: About OpenOCD
62 * Developers:: OpenOCD Developers
63 * Building OpenOCD:: Building OpenOCD From SVN
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * Running:: Running OpenOCD
66 * Simple Configuration Files:: Simple Configuration Files
67 * Config File Guidelines:: Config File Guidelines
68 * About JIM-Tcl:: About JIM-Tcl
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Creation:: TAP Creation
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * General Commands:: General Commands
77 * Architecture and Core Commands:: Architecture and Core Commands
78 * JTAG Commands:: JTAG Commands
79 * Sample Scripts:: Sample Target Scripts
81 * GDB and OpenOCD:: Using GDB and OpenOCD
82 * Tcl Scripting API:: Tcl Scripting API
83 * Upgrading:: Deprecated/Removed Commands
84 * Target Library:: Target Library
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
109 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
110 in-system programming and boundary-scan testing for embedded target
113 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
114 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
115 A @dfn{TAP} is a ``Test Access Port'', a module which processes
116 special instructions and data. TAPs are daisy-chained within and
117 between chips and boards.
119 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
120 based, parallel port based, and other standalone boxes that run
121 OpenOCD internally. @xref{JTAG Hardware Dongles}.
123 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
124 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
125 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
126 debugged via the GDB protocol.
128 @b{Flash Programing:} Flash writing is supported for external CFI
129 compatible NOR flashes (Intel and AMD/Spansion command set) and several
130 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
131 STM32x). Preliminary support for various NAND flash controllers
132 (LPC3180, Orion, S3C24xx, more) controller is included.
134 @section OpenOCD Web Site
136 The OpenOCD web site provides the latest public news from the community:
138 @uref{http://openocd.berlios.de/web/}
140 @section Latest User's Guide:
142 The user's guide you are now reading may not be the latest one
143 available. A version for more recent code may be available.
144 Its HTML form is published irregularly at:
146 @uref{http://openocd.berlios.de/doc/}
148 PDF form is likewise published at:
150 @uref{http://openocd.berlios.de/doc/pdf/}
152 @section OpenOCD User's Forum
154 There is an OpenOCD forum (phpBB) hosted by SparkFun:
156 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
160 @chapter OpenOCD Developer Resources
163 If you are interested in improving the state of OpenOCD's debugging and
164 testing support, new contributions will be welcome. Motivated developers
165 can produce new target, flash or interface drivers, improve the
166 documentation, as well as more conventional bug fixes and enhancements.
168 The resources in this chapter are available for developers wishing to explore
169 or expand the OpenOCD source code.
171 @section OpenOCD Subversion Repository
173 The ``Building From Source'' section provides instructions to retrieve
174 and and build the latest version of the OpenOCD source code.
175 @xref{Building OpenOCD}.
177 Developers that want to contribute patches to the OpenOCD system are
178 @b{strongly} encouraged to base their work off of the most recent trunk
179 revision. Patches created against older versions may require additional
180 work from their submitter in order to be updated for newer releases.
182 @section Doxygen Developer Manual
184 During the development of the 0.2.0 release, the OpenOCD project began
185 providing a Doxygen reference manual. This document contains more
186 technical information about the software internals, development
187 processes, and similar documentation:
189 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
191 This document is a work-in-progress, but contributions would be welcome
192 to fill in the gaps. All of the source files are provided in-tree,
193 listed in the Doxyfile configuration in the top of the repository trunk.
195 @section OpenOCD Developer Mailing List
197 The OpenOCD Developer Mailing List provides the primary means of
198 communication between developers:
200 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
202 All drivers developers are enouraged to also subscribe to the list of
203 SVN commits to keep pace with the ongoing changes:
205 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
208 @node Building OpenOCD
209 @chapter Building OpenOCD
212 @section Pre-Built Tools
213 If you are interested in getting actual work done rather than building
214 OpenOCD, then check if your interface supplier provides binaries for
215 you. Chances are that that binary is from some SVN version that is more
216 stable than SVN trunk where bleeding edge development takes place.
218 @section Packagers Please Read!
220 You are a @b{PACKAGER} of OpenOCD if you
223 @item @b{Sell dongles} and include pre-built binaries
224 @item @b{Supply tools} i.e.: A complete development solution
225 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
226 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
229 As a @b{PACKAGER}, you will experience first reports of most issues.
230 When you fix those problems for your users, your solution may help
231 prevent hundreds (if not thousands) of other questions from other users.
233 If something does not work for you, please work to inform the OpenOCD
234 developers know how to improve the system or documentation to avoid
235 future problems, and follow-up to help us ensure the issue will be fully
236 resolved in our future releases.
238 That said, the OpenOCD developers would also like you to follow a few
242 @item @b{Always build with printer ports enabled.}
243 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
247 @item @b{Why YES to LIBFTDI + LIBUSB?}
249 @item @b{LESS} work - libusb perhaps already there
250 @item @b{LESS} work - identical code, multiple platforms
251 @item @b{MORE} dongles are supported
252 @item @b{MORE} platforms are supported
253 @item @b{MORE} complete solution
255 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
257 @item @b{LESS} speed - some say it is slower
258 @item @b{LESS} complex to distribute (external dependencies)
262 @section Building From Source
264 You can download the current SVN version with an SVN client of your choice from the
265 following repositories:
267 @uref{svn://svn.berlios.de/openocd/trunk}
271 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
273 Using the SVN command line client, you can use the following command to fetch the
274 latest version (make sure there is no (non-svn) directory called "openocd" in the
278 svn checkout svn://svn.berlios.de/openocd/trunk openocd
281 If you prefer GIT based tools, the @command{git-svn} package works too:
284 git svn clone -s svn://svn.berlios.de/openocd
287 Building OpenOCD from a repository requires a recent version of the
288 GNU autotools (autoconf >= 2.59 and automake >= 1.9).
289 For building on Windows,
290 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
291 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
292 paths, resulting in obscure dependency errors (This is an observation I've gathered
293 from the logs of one user - correct me if I'm wrong).
295 You further need the appropriate driver files, if you want to build support for
296 a FTDI FT2232 based interface:
299 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
300 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
301 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
302 homepage (@uref{http://www.amontec.com}). The JTAGkey uses a non-standard VID/PID.
305 libftdi is supported under Windows. Do not use versions earlier than 0.14.
307 In general, the D2XX driver provides superior performance (several times as fast),
308 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
309 a kernel module, only a user space library.
311 To build OpenOCD (on both Linux and Cygwin), use the following commands:
317 Bootstrap generates the configure script, and prepares building on your system.
320 ./configure [options, see below]
323 Configure generates the Makefiles used to build OpenOCD.
330 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
332 The configure script takes several options, specifying which JTAG interfaces
333 should be included (among other things):
337 @option{--enable-parport} - Enable building the PC parallel port driver.
339 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
341 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
343 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
345 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
347 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
349 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
351 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
353 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
355 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
357 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
359 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
361 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c driver,
362 give the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
364 @option{--with-ftd2xx-linux-tardir=PATH} - If using FTDICHIP.COM ft2232c driver
365 on Linux, give the directory where the Linux driver's TAR.GZ file was unpacked.
367 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
369 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
371 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
373 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
375 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
377 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
379 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
381 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
383 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
385 @option{--enable-dummy} - Enable building the dummy port driver.
388 @section Parallel Port Dongles
390 If you want to access the parallel port using the PPDEV interface you have to specify
391 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
392 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
393 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
395 The same is true for the @option{--enable-parport_giveio} option, you have to
396 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
398 @section FT2232C Based USB Dongles
400 There are 2 methods of using the FTD2232, either (1) using the
401 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
402 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
404 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
405 TAR.GZ file. You must unpack them ``some where'' convient. As of this
406 writing (12/26/2008) FTDICHIP does not supply means to install these
407 files ``in an appropriate place'' As a result, there are two
408 ``./configure'' options that help.
410 Below is an example build process:
413 @item Check out the latest version of ``openocd'' from SVN.
415 @item If you are using the FTDICHIP.COM driver, download
416 and unpack the Windows or Linux FTD2xx drivers
417 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
418 If you are using the libftdi driver, install that package
419 (e.g. @command{apt-get install libftdi} on systems with APT).
422 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents
423 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents
426 @item Configure with options resembling the following.
429 @item Cygwin FTDICHIP solution:
431 ./configure --prefix=/home/duane/mytools \
432 --enable-ft2232_ftd2xx \
433 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
436 @item Linux FTDICHIP solution:
438 ./configure --prefix=/home/duane/mytools \
439 --enable-ft2232_ftd2xx \
440 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
443 @item Cygwin/Linux LIBFTDI solution ... assuming that
445 @item For Windows -- that the Windows port of LIBUSB is in place.
446 @item For Linux -- that libusb has been built/installed and is in place.
447 @item That libftdi has been built and installed (relies on libusb).
450 Then configure the libftdi solution like this:
453 ./configure --prefix=/home/duane/mytools \
454 --enable-ft2232_libftdi
458 @item Then just type ``make'', and perhaps ``make install''.
462 @section Miscellaneous Configure Options
466 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
468 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
471 @option{--enable-release} - Enable building of an OpenOCD release, generally
472 this is for developers. It simply omits the svn version string when the
473 openocd @option{-v} is executed.
476 @node JTAG Hardware Dongles
477 @chapter JTAG Hardware Dongles
486 Defined: @b{dongle}: A small device that plugins into a computer and serves as
487 an adapter .... [snip]
489 In the OpenOCD case, this generally refers to @b{a small adapater} one
490 attaches to your computer via USB or the Parallel Printer Port. The
491 execption being the Zylin ZY1000 which is a small box you attach via
492 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
493 require any drivers to be installed on the developer PC. It also has
494 a built in web interface. It supports RTCK/RCLK or adaptive clocking
495 and has a built in relay to power cycle targets remotely.
498 @section Choosing a Dongle
500 There are three things you should keep in mind when choosing a dongle.
503 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
504 @item @b{Connection} Printer Ports - Does your computer have one?
505 @item @b{Connection} Is that long printer bit-bang cable practical?
506 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
509 @section Stand alone Systems
511 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
512 dongle, but a standalone box. The ZY1000 has the advantage that it does
513 not require any drivers installed on the developer PC. It also has
514 a built in web interface. It supports RTCK/RCLK or adaptive clocking
515 and has a built in relay to power cycle targets remotely.
517 @section USB FT2232 Based
519 There are many USB JTAG dongles on the market, many of them are based
520 on a chip from ``Future Technology Devices International'' (FTDI)
521 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
522 See: @url{http://www.ftdichip.com} for more information.
523 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
524 chips are starting to become available in JTAG adapters.
526 As of 28/Nov/2008, the following are supported:
530 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
532 @* See: @url{http://www.amontec.com/jtagkey.shtml}
534 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
536 @* See: @url{http://www.signalyzer.com}
537 @item @b{evb_lm3s811}
538 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
539 @item @b{olimex-jtag}
540 @* See: @url{http://www.olimex.com}
542 @* See: @url{http://www.tincantools.com}
543 @item @b{turtelizer2}
545 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
546 @url{http://www.ethernut.de}
548 @* Link: @url{http://www.hitex.com/index.php?id=383}
550 @* Link @url{http://www.hitex.com/stm32-stick}
551 @item @b{axm0432_jtag}
552 @* Axiom AXM-0432 Link @url{http://www.axman.com}
554 @* Link @url{http://www.hitex.com/index.php?id=cortino}
557 @section USB JLINK based
558 There are several OEM versions of the Segger @b{JLINK} adapter. It is
559 an example of a micro controller based JTAG adapter, it uses an
560 AT91SAM764 internally.
563 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
564 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
565 @item @b{SEGGER JLINK}
566 @* Link: @url{http://www.segger.com/jlink.html}
568 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
571 @section USB RLINK based
572 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
575 @item @b{Raisonance RLink}
576 @* Link: @url{http://www.raisonance.com/products/RLink.php}
577 @item @b{STM32 Primer}
578 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
579 @item @b{STM32 Primer2}
580 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
586 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
588 @item @b{USB - Presto}
589 @* Link: @url{http://tools.asix.net/prg_presto.htm}
591 @item @b{Versaloon-Link}
592 @* Link: @url{http://www.simonqian.com/en/Versaloon}
594 @item @b{ARM-JTAG-EW}
595 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
598 @section IBM PC Parallel Printer Port Based
600 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
601 and the MacGraigor Wiggler. There are many clones and variations of
606 @item @b{Wiggler} - There are many clones of this.
607 @* Link: @url{http://www.macraigor.com/wiggler.htm}
609 @item @b{DLC5} - From XILINX - There are many clones of this
610 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
611 produced, PDF schematics are easily found and it is easy to make.
613 @item @b{Amontec - JTAG Accelerator}
614 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
617 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
620 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
621 Improved parallel-port wiggler-style JTAG adapter}
623 @item @b{Wiggler_ntrst_inverted}
624 @* Yet another variation - See the source code, src/jtag/parport.c
626 @item @b{old_amt_wiggler}
627 @* Unknown - probably not on the market today
630 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
633 @* Link: @url{http://www.amontec.com/chameleon.shtml}
639 @* ispDownload from Lattice Semiconductor
640 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
643 @* From ST Microsystems;
644 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
645 FlashLINK JTAG programing cable for PSD and uPSD}
653 @* An EP93xx based Linux machine using the GPIO pins directly.
656 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
662 @cindex running OpenOCD
664 @cindex --debug_level
668 The @option{--help} option shows:
672 --help | -h display this help
673 --version | -v display OpenOCD version
674 --file | -f use configuration file <name>
675 --search | -s dir to search for config files and scripts
676 --debug | -d set debug level <0-3>
677 --log_output | -l redirect log output to file <name>
678 --command | -c run <command>
679 --pipe | -p use pipes when talking to gdb
682 By default OpenOCD reads the file configuration file ``openocd.cfg''
683 in the current directory. To specify a different (or multiple)
684 configuration file, you can use the ``-f'' option. For example:
687 openocd -f config1.cfg -f config2.cfg -f config3.cfg
690 Once started, OpenOCD runs as a daemon, waiting for connections from
691 clients (Telnet, GDB, Other).
693 If you are having problems, you can enable internal debug messages via
696 Also it is possible to interleave commands w/config scripts using the
697 @option{-c} command line switch.
699 To enable debug output (when reporting problems or working on OpenOCD
700 itself), use the @option{-d} command line switch. This sets the
701 @option{debug_level} to "3", outputting the most information,
702 including debug messages. The default setting is "2", outputting only
703 informational messages, warnings and errors. You can also change this
704 setting from within a telnet or gdb session using @option{debug_level
705 <n>} @xref{debug_level}.
707 You can redirect all output from the daemon to a file using the
708 @option{-l <logfile>} switch.
710 Search paths for config/script files can be added to OpenOCD by using
711 the @option{-s <search>} switch. The current directory and the OpenOCD
712 target library is in the search path by default.
714 For details on the @option{-p} option. @xref{Connecting to GDB}.
716 Note! OpenOCD will launch the GDB & telnet server even if it can not
717 establish a connection with the target. In general, it is possible for
718 the JTAG controller to be unresponsive until the target is set up
719 correctly via e.g. GDB monitor commands in a GDB init script.
721 @node Simple Configuration Files
722 @chapter Simple Configuration Files
723 @cindex configuration
726 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
729 @item A small openocd.cfg file which ``sources'' other configuration files
730 @item A monolithic openocd.cfg file
731 @item Many -f filename options on the command line
732 @item Your Mixed Solution
735 @section Small configuration file method
737 This is the preferred method. It is simple and works well for many
738 people. The developers of OpenOCD would encourage you to use this
739 method. If you create a new configuration please email new
740 configurations to the development list.
742 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
745 source [find interface/signalyzer.cfg]
747 # GDB can also flash my flash!
748 gdb_memory_map enable
749 gdb_flash_program enable
751 source [find target/sam7x256.cfg]
754 There are many example configuration scripts you can work with. You
755 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
759 @item @b{board} - eval board level configurations
760 @item @b{interface} - specific dongle configurations
761 @item @b{target} - the target chips
762 @item @b{tcl} - helper scripts
763 @item @b{xscale} - things specific to the xscale.
766 Look first in the ``boards'' area, then the ``targets'' area. Often a board
767 configuration is a good example to work from.
769 @section Many -f filename options
770 Some believe this is a wonderful solution, others find it painful.
772 You can use a series of ``-f filename'' options on the command line,
773 OpenOCD will read each filename in sequence, for example:
776 openocd -f file1.cfg -f file2.cfg -f file2.cfg
779 You can also intermix various commands with the ``-c'' command line
782 @section Monolithic file
783 The ``Monolithic File'' dispenses with all ``source'' statements and
784 puts everything in one self contained (monolithic) file. This is not
787 Please try to ``source'' various files or use the multiple -f
790 @section Advice for you
791 Often, one uses a ``mixed approach''. Where possible, please try to
792 ``source'' common things, and if needed cut/paste parts of the
793 standard distribution configuration files as needed.
795 @b{REMEMBER:} The ``important parts'' of your configuration file are:
798 @item @b{Interface} - Defines the dongle
799 @item @b{Taps} - Defines the JTAG Taps
800 @item @b{GDB Targets} - What GDB talks to
801 @item @b{Flash Programing} - Very Helpful
804 Some key things you should look at and understand are:
807 @item The reset configuration of your debug environment as a whole
808 @item Is there a ``work area'' that OpenOCD can use?
809 @* For ARM - work areas mean up to 10x faster downloads.
810 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
811 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
816 @node Config File Guidelines
817 @chapter Config File Guidelines
819 This section/chapter is aimed at developers and integrators of
820 OpenOCD. These are guidelines for creating new boards and new target
821 configurations as of 28/Nov/2008.
823 However, you, the user of OpenOCD, should be somewhat familiar with
824 this section as it should help explain some of the internals of what
825 you might be looking at.
827 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
831 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
833 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
834 contain initialization items that are specific to a board - for
835 example: The SDRAM initialization sequence for the board, or the type
836 of external flash and what address it is found at. Any initialization
837 sequence to enable that external flash or SDRAM should be found in the
838 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
839 a CPU and an FPGA or CPLD.
841 @* Think chip. The ``target'' directory represents the JTAG TAPs
843 which OpenOCD should control, not a board. Two common types of targets
844 are ARM chips and FPGA or CPLD chips.
845 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
846 the target config file defines all of them.
849 @b{If needed...} The user in their ``openocd.cfg'' file or the board
850 file might override a specific feature in any of the above files by
851 setting a variable or two before sourcing the target file. Or adding
852 various commands specific to their situation.
854 @section Interface Config Files
856 The user should be able to source one of these files via a command like this:
859 source [find interface/FOOBAR.cfg]
861 openocd -f interface/FOOBAR.cfg
864 A preconfigured interface file should exist for every interface in use
865 today, that said, perhaps some interfaces have only been used by the
866 sole developer who created it.
868 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
870 @section Board Config Files
872 @b{Note: BOARD directory NEW as of 28/nov/2008}
874 The user should be able to source one of these files via a command like this:
877 source [find board/FOOBAR.cfg]
879 openocd -f board/FOOBAR.cfg
883 The board file should contain one or more @t{source [find
884 target/FOO.cfg]} statements along with any board specific things.
886 In summary the board files should contain (if present)
889 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
890 @item SDRAM configuration (size, speed, etc.
891 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
892 @item Multiple TARGET source statements
893 @item All things that are not ``inside a chip''
894 @item Things inside a chip go in a 'target' file
897 @section Target Config Files
899 The user should be able to source one of these files via a command like this:
902 source [find target/FOOBAR.cfg]
904 openocd -f target/FOOBAR.cfg
907 In summary the target files should contain
911 @item Add TAPs to the scan chain
912 @item Add CPU targets
913 @item Reset configuration
914 @item CPU/Chip/CPU-Core specific features
918 @subsection Important variable names
920 By default, the end user should never need to set these
921 variables. However, if the user needs to override a setting they only
922 need to set the variable in a simple way.
926 @* This gives a name to the overall chip, and is used as part of the
927 tap identifier dotted name.
929 @* By default little - unless the chip or board is not normally used that way.
931 @* When OpenOCD examines the JTAG chain, it will attempt to identify
932 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
933 to verify the tap id number verses configuration file and may issue an
934 error or warning like this. The hope is that this will help to pinpoint
935 problems in OpenOCD configurations.
938 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
939 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
940 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678,
942 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
943 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
946 @item @b{_TARGETNAME}
947 @* By convention, this variable is created by the target configuration
948 script. The board configuration file may make use of this variable to
949 configure things like a ``reset init'' script, or other things
950 specific to that board and that target.
952 If the chip has 2 targets, use the names @b{_TARGETNAME0},
953 @b{_TARGETNAME1}, ... etc.
955 @b{Remember:} The ``board file'' may include multiple targets.
957 At no time should the name ``target0'' (the default target name if
958 none was specified) be used. The name ``target0'' is a hard coded name
959 - the next target on the board will be some other number.
960 In the same way, avoid using target numbers even when they are
961 permitted; use the right target name(s) for your board.
963 The user (or board file) should reasonably be able to:
966 source [find target/FOO.cfg]
967 $_TARGETNAME configure ... FOO specific parameters
969 source [find target/BAR.cfg]
970 $_TARGETNAME configure ... BAR specific parameters
975 @subsection Tcl Variables Guide Line
976 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
978 Thus the rule we follow in OpenOCD is this: Variables that begin with
979 a leading underscore are temporary in nature, and can be modified and
980 used at will within a ?TARGET? configuration file.
982 @b{EXAMPLE:} The user should be able to do this:
986 # PXA270 #1 network side, big endian
987 # PXA270 #2 video side, little endian
991 source [find target/pxa270.cfg]
992 # variable: _TARGETNAME = network.cpu
993 # other commands can refer to the "network.cpu" tap.
994 $_TARGETNAME configure .... params for this CPU..
998 source [find target/pxa270.cfg]
999 # variable: _TARGETNAME = video.cpu
1000 # other commands can refer to the "video.cpu" tap.
1001 $_TARGETNAME configure .... params for this CPU..
1005 source [find target/spartan3.cfg]
1007 # Since $_TARGETNAME is temporal..
1008 # these names still work!
1009 network.cpu configure ... params
1010 video.cpu configure ... params
1013 @subsection Default Value Boiler Plate Code
1015 All target configuration files should start with this (or a modified form)
1019 if @{ [info exists CHIPNAME] @} @{
1020 set _CHIPNAME $CHIPNAME
1022 set _CHIPNAME sam7x256
1025 if @{ [info exists ENDIAN] @} @{
1031 if @{ [info exists CPUTAPID ] @} @{
1032 set _CPUTAPID $CPUTAPID
1034 set _CPUTAPID 0x3f0f0f0f
1038 @subsection Adding TAPs to the Scan Chain
1039 After the ``defaults'' are set up,
1040 add the TAPs on each chip to the JTAG scan chain.
1041 @xref{TAP Creation}, and the naming convention
1044 In the simplest case the chip has only one TAP,
1045 probably for a CPU or FPGA.
1046 The config file for the Atmel AT91SAM7X256
1047 looks (in part) like this:
1050 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1051 -expected-id $_CPUTAPID
1054 A board with two such at91sam7 chips would be able
1055 to source such a config file twice, with different
1056 values for @code{CHIPNAME} and @code{CPUTAPID}, so
1057 it adds a different TAP each time.
1059 There are more complex examples too, with chips that have
1060 multiple TAPs. Ones worth looking at include:
1063 @item @file{target/omap3530.cfg} -- with a disabled ARM, and a JRC
1064 (there's a DSP too, which is not listed)
1065 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1066 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1067 is not currently used)
1070 @subsection Add CPU targets
1072 After adding a TAP for a CPU, you should set it up so that
1073 GDB and other commands can use it.
1074 @xref{CPU Configuration}.
1075 For the at91sam7 example above, the command can look like this:
1078 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1081 Work areas are small RAM areas associated with CPU targets.
1082 They are used by OpenOCD to speed up downloads,
1083 and to download small snippets of code to program flash chips.
1084 If the chip includes a form of ``on-chip-ram'' - and many do - define
1085 a work area if you can.
1086 Again using the at91sam7 as an example, this can look like:
1089 $_TARGETNAME configure -work-area-phys 0x00200000 \
1090 -work-area-size 0x4000 -work-area-backup 0
1093 @subsection Reset Configuration
1095 Some chips have specific ways the TRST and SRST signals are
1096 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1097 @b{BOARD SPECIFIC} they go in the board file.
1099 @subsection ARM Core Specific Hacks
1101 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1102 special high speed download features - enable it.
1104 If the chip has an ARM ``vector catch'' feature - by default enable
1105 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1106 user is really writing a handler for those situations - they can
1107 easily disable it. Experiance has shown the ``vector catch'' is
1108 helpful - for common programing errors.
1110 If present, the MMU, the MPU and the CACHE should be disabled.
1112 Some ARM cores are equipped with trace support, which permits
1113 examination of the instruction and data bus activity. Trace
1114 activity is controlled through an ``Embedded Trace Module'' (ETM)
1115 on one of the core's scan chains. The ETM emits voluminous data
1116 through a ``trace port''. (@xref{ARM Tracing}.)
1117 If you are using an external trace port,
1118 configure it in your board config file.
1119 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1120 configure it in your target config file.
1123 etm config $_TARGETNAME 16 normal full etb
1124 etb config $_TARGETNAME $_CHIPNAME.etb
1127 @subsection Internal Flash Configuration
1129 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1131 @b{Never ever} in the ``target configuration file'' define any type of
1132 flash that is external to the chip. (For example a BOOT flash on
1133 Chip Select 0.) Such flash information goes in a board file - not
1134 the TARGET (chip) file.
1138 @item at91sam7x256 - has 256K flash YES enable it.
1139 @item str912 - has flash internal YES enable it.
1140 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1141 @item pxa270 - again - CS0 flash - it goes in the board file.
1145 @chapter About JIM-Tcl
1149 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1150 learn more about JIM here: @url{http://jim.berlios.de}
1153 @item @b{JIM vs. Tcl}
1154 @* JIM-TCL is a stripped down version of the well known Tcl language,
1155 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1156 fewer features. JIM-Tcl is a single .C file and a single .H file and
1157 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1158 4.2 MB .zip file containing 1540 files.
1160 @item @b{Missing Features}
1161 @* Our practice has been: Add/clone the real Tcl feature if/when
1162 needed. We welcome JIM Tcl improvements, not bloat.
1165 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1166 command interpreter today (28/nov/2008) is a mixture of (newer)
1167 JIM-Tcl commands, and (older) the orginal command interpreter.
1170 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1171 can type a Tcl for() loop, set variables, etc.
1173 @item @b{Historical Note}
1174 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1176 @item @b{Need a crash course in Tcl?}
1177 @*@xref{Tcl Crash Course}.
1180 @node Daemon Configuration
1181 @chapter Daemon Configuration
1182 @cindex initialization
1183 The commands here are commonly found in the openocd.cfg file and are
1184 used to specify what TCP/IP ports are used, and how GDB should be
1187 @section Configuration Stage
1188 @cindex configuration stage
1189 @cindex configuration command
1191 When the OpenOCD server process starts up, it enters a
1192 @emph{configuration stage} which is the only time that
1193 certain commands, @emph{configuration commands}, may be issued.
1194 Those configuration commands include declaration of TAPs
1195 and other basic setup.
1196 The server must leave the configuration stage before it
1197 may access or activate TAPs.
1198 After it leaves this stage, configuration commands may no
1201 @deffn {Config Command} init
1202 This command terminates the configuration stage and
1203 enters the normal command mode. This can be useful to add commands to
1204 the startup scripts and commands such as resetting the target,
1205 programming flash, etc. To reset the CPU upon startup, add "init" and
1206 "reset" at the end of the config script or at the end of the OpenOCD
1207 command line using the @option{-c} command line switch.
1209 If this command does not appear in any startup/configuration file
1210 OpenOCD executes the command for you after processing all
1211 configuration files and/or command line options.
1213 @b{NOTE:} This command normally occurs at or near the end of your
1214 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1215 targets ready. For example: If your openocd.cfg file needs to
1216 read/write memory on your target, @command{init} must occur before
1217 the memory read/write commands. This includes @command{nand probe}.
1220 @section TCP/IP Ports
1224 The OpenOCD server accepts remote commands in several syntaxes.
1225 Each syntax uses a different TCP/IP port, which you may specify
1226 only during configuration (before those ports are opened).
1228 @deffn {Command} gdb_port (number)
1230 Specify or query the first port used for incoming GDB connections.
1231 The GDB port for the
1232 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1233 When not specified during the configuration stage,
1234 the port @var{number} defaults to 3333.
1237 @deffn {Command} tcl_port (number)
1238 Specify or query the port used for a simplified RPC
1239 connection that can be used by clients to issue TCL commands and get the
1240 output from the Tcl engine.
1241 Intended as a machine interface.
1242 When not specified during the configuration stage,
1243 the port @var{number} defaults to 6666.
1246 @deffn {Command} telnet_port (number)
1247 Specify or query the
1248 port on which to listen for incoming telnet connections.
1249 This port is intended for interaction with one human through TCL commands.
1250 When not specified during the configuration stage,
1251 the port @var{number} defaults to 4444.
1254 @anchor{GDB Configuration}
1255 @section GDB Configuration
1257 @cindex GDB configuration
1258 You can reconfigure some GDB behaviors if needed.
1259 The ones listed here are static and global.
1260 @xref{Target Create}, about declaring individual targets.
1261 @xref{Target Events}, about configuring target-specific event handling.
1263 @anchor{gdb_breakpoint_override}
1264 @deffn {Command} gdb_breakpoint_override <hard|soft|disable>
1265 Force breakpoint type for gdb @command{break} commands.
1266 The raison d'etre for this option is to support GDB GUI's which don't
1267 distinguish hard versus soft breakpoints, if the default OpenOCD and
1268 GDB behaviour is not sufficient. GDB normally uses hardware
1269 breakpoints if the memory map has been set up for flash regions.
1271 This option replaces older arm7_9 target commands that addressed
1275 @deffn {Config command} gdb_detach <resume|reset|halt|nothing>
1276 Configures what OpenOCD will do when GDB detaches from the daemon.
1277 Default behaviour is @var{resume}.
1280 @anchor{gdb_flash_program}
1281 @deffn {Config command} gdb_flash_program <enable|disable>
1282 Set to @var{enable} to cause OpenOCD to program the flash memory when a
1283 vFlash packet is received.
1284 The default behaviour is @var{enable}.
1287 @deffn {Config command} gdb_memory_map <enable|disable>
1288 Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
1289 requested. GDB will then know when to set hardware breakpoints, and program flash
1290 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1291 for flash programming to work.
1292 Default behaviour is @var{enable}.
1293 @xref{gdb_flash_program}.
1296 @deffn {Config command} gdb_report_data_abort <enable|disable>
1297 Specifies whether data aborts cause an error to be reported
1298 by GDB memory read packets.
1299 The default behaviour is @var{disable};
1300 use @var{enable} see these errors reported.
1303 @node Interface - Dongle Configuration
1304 @chapter Interface - Dongle Configuration
1305 Interface commands are normally found in an interface configuration
1306 file which is sourced by your openocd.cfg file. These commands tell
1307 OpenOCD what type of JTAG dongle you have and how to talk to it.
1308 @section Simple Complete Interface Examples
1309 @b{A Turtelizer FT2232 Based JTAG Dongle}
1313 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1314 ft2232_layout turtelizer2
1315 ft2232_vid_pid 0x0403 0xbdc8
1322 @b{A Raisonance RLink}
1331 parport_cable wiggler
1336 interface arm-jtag-ew
1339 @section Interface Configuration
1341 The interface command tells OpenOCD what type of JTAG dongle you are
1342 using. Depending on the type of dongle, you may need to have one or
1343 more additional commands.
1345 @deffn {Config Command} {interface} name
1346 Use the interface driver @var{name} to connect to the
1350 @deffn Command {jtag interface}
1351 Returns the name of the interface driver being used.
1354 @section Interface Drivers
1356 Currently supported interface drivers are:
1361 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1363 @item @b{amt_jtagaccel}
1364 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1368 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1369 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1370 platform. The libftdi uses libusb, and should be portable to all systems that provide
1374 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1377 @* ASIX PRESTO USB JTAG programmer.
1380 @* usbprog is a freely programmable USB adapter.
1383 @* Gateworks GW16012 JTAG programmer.
1386 @* Segger jlink USB adapter
1389 @* Raisonance RLink USB adapter
1392 @* vsllink is part of Versaloon which is a versatile USB programmer.
1394 @item @b{arm-jtag-ew}
1395 @* Olimex ARM-JTAG-EW USB adapter
1398 @subsection parport options
1401 @item @b{parport_port} <@var{number}>
1402 @cindex parport_port
1403 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1404 the @file{/dev/parport} device
1406 When using PPDEV to access the parallel port, use the number of the parallel port:
1407 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1408 you may encounter a problem.
1409 @item @b{parport_cable} <@var{name}>
1410 @cindex parport_cable
1411 @*The layout of the parallel port cable used to connect to the target.
1412 Currently supported cables are
1416 The original Wiggler layout, also supported by several clones, such
1417 as the Olimex ARM-JTAG
1420 Same as original wiggler except an led is fitted on D5.
1421 @item @b{wiggler_ntrst_inverted}
1422 @cindex wiggler_ntrst_inverted
1423 Same as original wiggler except TRST is inverted.
1424 @item @b{old_amt_wiggler}
1425 @cindex old_amt_wiggler
1426 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1427 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1430 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1431 program the Chameleon itself, not a connected target.
1434 The Xilinx Parallel cable III.
1437 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1438 This is also the layout used by the HollyGates design
1439 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1442 The ST Parallel cable.
1445 Same as original wiggler except SRST and TRST connections reversed and
1446 TRST is also inverted.
1449 Altium Universal JTAG cable.
1451 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1452 @cindex parport_write_on_exit
1453 @*This will configure the parallel driver to write a known value to the parallel
1454 interface on exiting OpenOCD
1457 @subsection amt_jtagaccel options
1459 @item @b{parport_port} <@var{number}>
1460 @cindex parport_port
1461 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1462 @file{/dev/parport} device
1464 @subsection ft2232 options
1467 @item @b{ft2232_device_desc} <@var{description}>
1468 @cindex ft2232_device_desc
1469 @*The USB device description of the FTDI FT2232 device. If not
1470 specified, the FTDI default value is used. This setting is only valid
1471 if compiled with FTD2XX support.
1473 @b{TODO:} Confirm the following: On Windows the name needs to end with
1474 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1475 this be added and when must it not be added? Why can't the code in the
1476 interface or in OpenOCD automatically add this if needed? -- Duane.
1478 @item @b{ft2232_serial} <@var{serial-number}>
1479 @cindex ft2232_serial
1480 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1482 @item @b{ft2232_layout} <@var{name}>
1483 @cindex ft2232_layout
1484 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1485 signals. Valid layouts are
1488 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1490 Amontec JTAGkey and JTAGkey-Tiny
1491 @item @b{signalyzer}
1493 @item @b{olimex-jtag}
1496 American Microsystems M5960
1497 @item @b{evb_lm3s811}
1498 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1499 SRST signals on external connector
1502 @item @b{stm32stick}
1503 Hitex STM32 Performance Stick
1504 @item @b{flyswatter}
1505 Tin Can Tools Flyswatter
1506 @item @b{turtelizer2}
1507 egnite Software turtelizer2
1510 @item @b{axm0432_jtag}
1513 Hitex Cortino JTAG interface
1516 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1517 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1518 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1520 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1522 @item @b{ft2232_latency} <@var{ms}>
1523 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1524 ft2232_read() fails to return the expected number of bytes. This can be caused by
1525 USB communication delays and has proved hard to reproduce and debug. Setting the
1526 FT2232 latency timer to a larger value increases delays for short USB packets but it
1527 also reduces the risk of timeouts before receiving the expected number of bytes.
1528 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1533 JTAG clock setup is part of system setup.
1534 It @emph{does not belong with interface setup} since any interface
1535 only knows a few of the constraints for the JTAG clock speed.
1536 Sometimes the JTAG speed is
1537 changed during the target initialization process: (1) slow at
1538 reset, (2) program the CPU clocks, (3) run fast.
1539 Both the "slow" and "fast" clock rates are functions of the
1540 oscillators used, the chip, the board design, and sometimes
1541 power management software that may be active.
1543 The speed used during reset can be adjusted using pre_reset
1544 and post_reset event handlers.
1545 @xref{Target Events}.
1547 If your system supports adaptive clocking (RTCK), configuring
1548 JTAG to use that is probably the most robust approach.
1549 However, it introduces delays to synchronize clocks; so it
1550 may not be the fastest solution.
1552 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1553 instead of @command{jtag_khz}.
1555 @deffn {Command} jtag_khz max_speed_kHz
1556 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1557 JTAG interfaces usually support a limited number of
1558 speeds. The speed actually used won't be faster
1559 than the speed specified.
1561 As a rule of thumb, if you specify a clock rate make
1562 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1563 This is especially true for synthesized cores (ARMxxx-S).
1565 Speed 0 (khz) selects RTCK method.
1567 If your system uses RTCK, you won't need to change the
1568 JTAG clocking after setup.
1569 Not all interfaces, boards, or targets support ``rtck''.
1570 If the interface device can not
1571 support it, an error is returned when you try to use RTCK.
1574 @defun jtag_rclk fallback_speed_kHz
1576 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
1577 If that fails (maybe the interface, board, or target doesn't
1578 support it), falls back to the specified frequency.
1580 # Fall back to 3mhz if RTCK is not supported
1585 @node Reset Configuration
1586 @chapter Reset Configuration
1587 @cindex Reset Configuration
1589 Every system configuration may require a different reset
1590 configuration. This can also be quite confusing.
1591 Resets also interact with @var{reset-init} event handlers,
1592 which do things like setting up clocks and DRAM, and
1593 JTAG clock rates. (@xref{JTAG Speed}.)
1594 Please see the various board files for examples.
1597 To maintainers and integrators:
1598 Reset configuration touches several things at once.
1599 Normally the board configuration file
1600 should define it and assume that the JTAG adapter supports
1601 everything that's wired up to the board's JTAG connector.
1602 However, the target configuration file could also make note
1603 of something the silicon vendor has done inside the chip,
1604 which will be true for most (or all) boards using that chip.
1605 And when the JTAG adapter doesn't support everything, the
1606 system configuration file will need to override parts of
1607 the reset configuration provided by other files.
1610 @section Types of Reset
1612 There are many kinds of reset possible through JTAG, but
1613 they may not all work with a given board and adapter.
1614 That's part of why reset configuration can be error prone.
1618 @emph{System Reset} ... the @emph{SRST} hardware signal
1619 resets all chips connected to the JTAG adapter, such as processors,
1620 power management chips, and I/O controllers. Normally resets triggered
1621 with this signal behave exactly like pressing a RESET button.
1623 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1624 just the TAP controllers connected to the JTAG adapter.
1625 Such resets should not be visible to the rest of the system; resetting a
1626 device's the TAP controller just puts that controller into a known state.
1628 @emph{Emulation Reset} ... many devices can be reset through JTAG
1629 commands. These resets are often distinguishable from system
1630 resets, either explicitly (a "reset reason" register says so)
1631 or implicitly (not all parts of the chip get reset).
1633 @emph{Other Resets} ... system-on-chip devices often support
1634 several other types of reset.
1635 You may need to arrange that a watchdog timer stops
1636 while debugging, preventing a watchdog reset.
1637 There may be individual module resets.
1640 In the best case, OpenOCD can hold SRST, then reset
1641 the TAPs via TRST and send commands through JTAG to halt the
1642 CPU at the reset vector before the 1st instruction is executed.
1643 Then when it finally releases the SRST signal, the system is
1644 halted under debugger control before any code has executed.
1645 This is the behavior required to support the @command{reset halt}
1646 and @command{reset init} commands; after @command{reset init} a
1647 board-specific script might do things like setting up DRAM.
1648 (@xref{Reset Command}.)
1650 @section SRST and TRST Issues
1652 Because SRST and TRST are hardware signals, they can have a
1653 variety of system-specific constraints. Some of the most
1658 @item @emph{Signal not available} ... Some boards don't wire
1659 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1660 support such signals even if they are wired up.
1661 Use the @command{reset_config} @var{signals} options to say
1662 when one of those signals is not connected.
1663 When SRST is not available, your code might not be able to rely
1664 on controllers having been fully reset during code startup.
1666 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1667 adapter will connect SRST to TRST, instead of keeping them separate.
1668 Use the @command{reset_config} @var{combination} options to say
1669 when those signals aren't properly independent.
1671 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1672 delay circuit, reset supervisor, or on-chip features can extend
1673 the effect of a JTAG adapter's reset for some time after the adapter
1674 stops issuing the reset. For example, there may be chip or board
1675 requirements that all reset pulses last for at least a
1676 certain amount of time; and reset buttons commonly have
1677 hardware debouncing.
1678 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1679 commands to say when extra delays are needed.
1681 @item @emph{Drive type} ... Reset lines often have a pullup
1682 resistor, letting the JTAG interface treat them as open-drain
1683 signals. But that's not a requirement, so the adapter may need
1684 to use push/pull output drivers.
1685 Also, with weak pullups it may be advisable to drive
1686 signals to both levels (push/pull) to minimize rise times.
1687 Use the @command{reset_config} @var{trst_type} and
1688 @var{srst_type} parameters to say how to drive reset signals.
1690 @item @emph{Special initialization} ... Targets sometimes need
1691 special JTAG initialization sequences to handle chip-specific
1692 issues (not limited to errata).
1693 For example, certain JTAG commands might need to be issued while
1694 the system as a whole is in a reset state (SRST active)
1695 but the JTAG scan chain is usable (TRST inactive).
1696 (@xref{JTAG Commands}, where the @command{jtag_reset}
1697 command is presented.)
1700 There can also be other issues.
1701 Some devices don't fully conform to the JTAG specifications.
1702 Trivial system-specific differences are common, such as
1703 SRST and TRST using slightly different names.
1704 There are also vendors who distribute key JTAG documentation for
1705 their chips only to developers who have signed a Non-Disclosure
1708 Sometimes there are chip-specific extensions like a requirement to use
1709 the normally-optional TRST signal (precluding use of JTAG adapters which
1710 don't pass TRST through), or needing extra steps to complete a TAP reset.
1712 In short, SRST and especially TRST handling may be very finicky,
1713 needing to cope with both architecture and board specific constraints.
1715 @section Commands for Handling Resets
1717 @deffn {Command} jtag_nsrst_delay milliseconds
1718 How long (in milliseconds) OpenOCD should wait after deasserting
1719 nSRST (active-low system reset) before starting new JTAG operations.
1720 When a board has a reset button connected to SRST line it will
1721 probably have hardware debouncing, implying you should use this.
1724 @deffn {Command} jtag_ntrst_delay milliseconds
1725 How long (in milliseconds) OpenOCD should wait after deasserting
1726 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1729 @deffn {Command} reset_config mode_flag ...
1730 This command tells OpenOCD the reset configuration
1731 of your combination of JTAG board and target in target
1732 configuration scripts.
1734 If you have an interface that does not support SRST and
1735 TRST(unlikely), then you may be able to work around that
1736 problem by using a reset_config command to override any
1737 settings in the target configuration script.
1739 SRST and TRST has a fairly well understood definition and
1740 behaviour in the JTAG specification, but vendors take
1741 liberties to achieve various more or less clearly understood
1742 goals. Sometimes documentation is available, other times it
1743 is not. OpenOCD has the reset_config command to allow OpenOCD
1744 to deal with the various common cases.
1746 The @var{mode_flag} options can be specified in any order, but only one
1747 of each type -- @var{signals}, @var{combination}, @var{trst_type},
1748 and @var{srst_type} -- may be specified at a time.
1749 If you don't provide a new value for a given type, its previous
1750 value (perhaps the default) is unchanged.
1751 For example, this means that you don't need to say anything at all about
1752 TRST just to declare that if the JTAG adapter should want to drive SRST,
1753 it must explicitly be driven high (@option{srst_push_pull}).
1755 @var{signals} can specify which of the reset signals are connected.
1756 For example, If the JTAG interface provides SRST, but the board doesn't
1757 connect that signal properly, then OpenOCD can't use it.
1758 Possible values are @option{none} (the default), @option{trst_only},
1759 @option{srst_only} and @option{trst_and_srst}.
1762 If your board provides SRST or TRST through the JTAG connector,
1763 you must declare that or else those signals will not be used.
1766 The @var{combination} is an optional value specifying broken reset
1767 signal implementations.
1768 The default behaviour if no option given is @option{separate},
1769 indicating everything behaves normally.
1770 @option{srst_pulls_trst} states that the
1771 test logic is reset together with the reset of the system (e.g. Philips
1772 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1773 the system is reset together with the test logic (only hypothetical, I
1774 haven't seen hardware with such a bug, and can be worked around).
1775 @option{combined} implies both @option{srst_pulls_trst} and
1776 @option{trst_pulls_srst}.
1778 The optional @var{trst_type} and @var{srst_type} parameters allow the
1779 driver mode of each reset line to be specified. These values only affect
1780 JTAG interfaces with support for different driver modes, like the Amontec
1781 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
1782 relevant signal (TRST or SRST) is not connected.
1784 Possible @var{trst_type} driver modes for the test reset signal (TRST)
1785 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
1786 Most boards connect this signal to a pulldown, so the JTAG TAPs
1787 never leave reset unless they are hooked up to a JTAG adapter.
1789 Possible @var{srst_type} driver modes for the system reset signal (SRST)
1790 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
1791 Most boards connect this signal to a pullup, and allow the
1792 signal to be pulled low by various events including system
1793 powerup and pressing a reset button.
1798 @chapter TAP Creation
1799 @cindex TAP creation
1800 @cindex TAP configuration
1802 @emph{Test Access Ports} (TAPs) are the core of JTAG.
1803 TAPs serve many roles, including:
1806 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
1807 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
1808 Others do it indirectly, making a CPU do it.
1809 @item @b{Program Download} Using the same CPU support GDB uses,
1810 you can initialize a DRAM controller, download code to DRAM, and then
1811 start running that code.
1812 @item @b{Boundary Scan} Most chips support boundary scan, which
1813 helps test for board assembly problems like solder bridges
1814 and missing connections
1817 OpenOCD must know about the active TAPs on your board(s).
1818 Setting up the TAPs is the core task of your configuration files.
1819 Once those TAPs are set up, you can pass their names to code
1820 which sets up CPUs and exports them as GDB targets,
1821 probes flash memory, performs low-level JTAG operations, and more.
1823 @section Scan Chains
1825 OpenOCD uses a JTAG adapter (interface) to talk to your board,
1826 which has a daisy chain of TAPs.
1827 That daisy chain is called a @dfn{scan chain}.
1828 Simple configurations may have a single TAP in the scan chain,
1829 perhaps for a microcontroller.
1830 Complex configurations might have a dozen or more TAPs:
1831 several in one chip, more in the next, and connecting
1832 to other boards with their own chips and TAPs.
1834 Unfortunately those TAPs can't always be autoconfigured,
1835 because not all devices provide good support for that.
1836 (JTAG doesn't require supporting IDCODE instructions.)
1837 The configuration mechanism currently supported by OpenOCD
1838 requires explicit configuration of all TAP devices using
1839 @command{jtag newtap} commands.
1840 One like this would create a tap named @code{chip1.cpu}:
1843 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
1846 Each target configuration file lists the TAPs provided
1848 Board configuration files combine all the targets on a board,
1850 Note that @emph{the order in which TAPs are created is very important.}
1851 It must match the order in the JTAG scan chain, both inside
1852 a single chip and between them.
1854 For example, the ST Microsystems STR912 chip has
1855 three separate TAPs@footnote{See the ST
1856 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1857 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1858 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1859 Checked: 28-Nov-2008}.
1860 To configure those taps, @file{target/str912.cfg}
1861 includes commands something like this:
1864 jtag newtap str912 flash ... params ...
1865 jtag newtap str912 cpu ... params ...
1866 jtag newtap str912 bs ... params ...
1869 Actual config files use a variable instead of literals like
1870 @option{str912}, to support more than one chip of each type.
1871 @xref{Config File Guidelines}.
1875 When a TAP objects is created with @command{jtag newtap},
1876 a @dfn{dotted.name} is created for the TAP, combining the
1877 name of a module (usually a chip) and a label for the TAP.
1878 For example: @code{xilinx.tap}, @code{str912.flash},
1879 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
1880 Many other commands use that dotted.name to manipulate or
1881 refer to the TAP. For example, CPU configuration uses the
1882 name, as does declaration of NAND or NOR flash banks.
1884 The components of a dotted name should follow ``C'' symbol
1885 name rules: start with an alphabetic character, then numbers
1886 and underscores are OK; while others (including dots!) are not.
1889 In older code, JTAG TAPs were numbered from 0..N.
1890 This feature is still present.
1891 However its use is highly discouraged, and
1892 should not be counted upon.
1893 Update all of your scripts to use TAP names rather than numbers.
1894 Using TAP numbers in target configuration scripts prevents
1895 reusing on boards with multiple targets.
1898 @anchor{TAP Creation Commands}
1899 @section TAP Creation Commands
1901 @c shouldn't this be(come) a {Config Command}?
1902 @anchor{jtag newtap}
1903 @deffn Command {jtag newtap} chipname tapname configparams...
1904 Creates a new TAP with the dotted name @var{chipname}.@var{tapname},
1905 and configured according to the various @var{configparams}.
1907 The @var{chipname} is a symbolic name for the chip.
1908 Conventionally target config files use @code{$_CHIPNAME},
1909 defaulting to the model name given by the chip vendor but
1912 @cindex TAP naming convention
1913 The @var{tapname} reflects the role of that TAP,
1914 and should follow this convention:
1917 @item @code{bs} -- For boundary scan if this is a seperate TAP;
1918 @item @code{cpu} -- The main CPU of the chip, alternatively
1919 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
1920 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
1921 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
1922 @item @code{flash} -- If the chip has a flash TAP, like the str912;
1923 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
1924 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
1925 @item @code{tap} -- Should be used only FPGA or CPLD like devices
1927 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
1928 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
1929 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
1930 a JTAG TAP; that TAP should be named @code{sdma}.
1933 Every TAP requires at least the following @var{configparams}:
1936 @item @code{-ircapture} @var{NUMBER}
1937 @*The IDCODE capture command, such as 0x01.
1938 @item @code{-irlen} @var{NUMBER}
1939 @*The length in bits of the
1940 instruction register, such as 4 or 5 bits.
1941 @item @code{-irmask} @var{NUMBER}
1942 @*A mask for the IR register.
1943 For some devices, there are bits in the IR that aren't used.
1944 This lets OpenOCD mask them off when doing IDCODE comparisons.
1945 In general, this should just be all ones for the size of the IR.
1948 A TAP may also provide optional @var{configparams}:
1951 @item @code{-disable} (or @code{-enable})
1952 @*Use the @code{-disable} paramater to flag a TAP which is not
1953 linked in to the scan chain when it is declared.
1954 You may use @code{-enable} to highlight the default state
1955 (the TAP is linked in).
1956 @xref{Enabling and Disabling TAPs}.
1957 @item @code{-expected-id} @var{number}
1958 @*A non-zero value represents the expected 32-bit IDCODE
1959 found when the JTAG chain is examined.
1960 These codes are not required by all JTAG devices.
1961 @emph{Repeat the option} as many times as required if more than one
1962 ID code could appear (for example, multiple versions).
1966 @c @deffn Command {jtag arp_init-reset}
1967 @c ... more or less "init" ?
1969 @anchor{Enabling and Disabling TAPs}
1970 @section Enabling and Disabling TAPs
1973 In some systems, a @dfn{JTAG Route Controller} (JRC)
1974 is used to enable and/or disable specific JTAG TAPs.
1975 Many ARM based chips from Texas Instruments include
1976 an ``ICEpick'' module, which is a JRC.
1977 Such chips include DaVinci and OMAP3 processors.
1979 A given TAP may not be visible until the JRC has been
1980 told to link it into the scan chain; and if the JRC
1981 has been told to unlink that TAP, it will no longer
1983 Such routers address problems that JTAG ``bypass mode''
1987 @item The scan chain can only go as fast as its slowest TAP.
1988 @item Having many TAPs slows instruction scans, since all
1989 TAPs receive new instructions.
1990 @item TAPs in the scan chain must be powered up, which wastes
1991 power and prevents debugging some power management mechanisms.
1994 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
1995 as implied by the existence of JTAG routers.
1996 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
1997 does include a kind of JTAG router functionality.
1999 @c (a) currently the event handlers don't seem to be able to
2000 @c fail in a way that could lead to no-change-of-state.
2001 @c (b) eventually non-event configuration should be possible,
2002 @c in which case some this documentation must move.
2004 @deffn Command {jtag cget} dotted.name @option{-event} name
2005 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2006 At this writing this mechanism is used only for event handling,
2007 and the only two events relate to TAP enabling and disabling.
2009 The @code{configure} subcommand assigns an event handler,
2010 a TCL string which is evaluated when the event is triggered.
2011 The @code{cget} subcommand returns that handler.
2012 The two possible values for an event @var{name}
2013 are @option{tap-disable} and @option{tap-enable}.
2015 So for example, when defining a TAP for a CPU connected to
2016 a JTAG router, you should define TAP event handlers using
2017 code that looks something like this:
2020 jtag configure CHIP.cpu -event tap-enable @{
2021 echo "Enabling CPU TAP"
2022 ... jtag operations using CHIP.jrc
2024 jtag configure CHIP.cpu -event tap-disable @{
2025 echo "Disabling CPU TAP"
2026 ... jtag operations using CHIP.jrc
2031 @deffn Command {jtag tapdisable} dotted.name
2032 @deffnx Command {jtag tapenable} dotted.name
2033 @deffnx Command {jtag tapisenabled} dotted.name
2034 These three commands all return the string "1" if the tap
2035 specified by @var{dotted.name} is enabled,
2036 and "0" if it is disbabled.
2037 The @command{tapenable} variant first enables the tap
2038 by sending it a @option{tap-enable} event.
2039 The @command{tapdisable} variant first disables the tap
2040 by sending it a @option{tap-disable} event.
2043 Humans will find the @command{scan_chain} command more helpful
2044 than the script-oriented @command{tapisenabled}
2045 for querying the state of the JTAG taps.
2049 @node CPU Configuration
2050 @chapter CPU Configuration
2053 This chapter discusses how to create a GDB debug target for a CPU.
2054 You can also access these targets without GDB
2055 (@pxref{Architecture and Core Commands}) and, where relevant,
2056 through various kinds of NAND and NOR flash commands.
2057 Also, if you have multiple CPUs you can have multiple such targets.
2059 Before creating a ``target'', you must have added its TAP to the scan chain.
2060 When you've added that TAP, you will have a @code{dotted.name}
2061 which is used to set up the CPU support.
2062 The chip-specific configuration file will normally configure its CPU(s)
2063 right after it adds all of the chip's TAPs to the scan chain.
2065 @section targets [NAME]
2066 @b{Note:} This command name is PLURAL - not singular.
2068 With NO parameter, this plural @b{targets} command lists all known
2069 targets in a human friendly form.
2071 With a parameter, this plural @b{targets} command sets the current
2072 target to the given name. (i.e.: If there are multiple debug targets)
2077 CmdName Type Endian ChainPos State
2078 -- ---------- ---------- ---------- -------- ----------
2079 0: target0 arm7tdmi little 0 halted
2082 @section target COMMANDS
2083 @b{Note:} This command name is SINGULAR - not plural. It is used to
2084 manipulate specific targets, to create targets and other things.
2086 Once a target is created, a TARGETNAME (object) command is created;
2087 see below for details.
2089 The TARGET command accepts these sub-commands:
2091 @item @b{create} .. parameters ..
2092 @* creates a new target, see below for details.
2094 @* Lists all supported target types (perhaps some are not yet in this document).
2096 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
2098 foreach t [target names] {
2099 puts [format "Target: %s\n" $t]
2103 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
2104 By default, commands like: ``mww'' (used to write memory) operate on the current target.
2105 @item @b{number} @b{NUMBER}
2106 @* Internally OpenOCD maintains a list of targets - in numerical index
2107 (0..N-1) this command returns the name of the target at index N.
2110 set thename [target number $x]
2111 puts [format "Target %d is: %s\n" $x $thename]
2114 @* Returns the number of targets known to OpenOCD (see number above)
2117 set c [target count]
2118 for { set x 0 } { $x < $c } { incr x } {
2119 # Assuming you have created this function
2120 print_target_details $x
2126 @section TARGETNAME (object) commands
2127 @b{Use:} Once a target is created, an ``object name'' that represents the
2128 target is created. By convention, the target name is identical to the
2129 tap name. In a multiple target system, one can precede many common
2130 commands with a specific target name and effect only that target.
2132 str912.cpu mww 0x1234 0x42
2133 omap3530.cpu mww 0x5555 123
2136 @b{Model:} The Tcl/Tk language has the concept of object commands. A
2137 good example is a on screen button, once a button is created a button
2138 has a name (a path in Tk terms) and that name is useable as a 1st
2139 class command. For example in Tk, one can create a button and later
2140 configure it like this:
2144 button .foobar -background red -command @{ foo @}
2146 .foobar configure -foreground blue
2148 set x [.foobar cget -background]
2150 puts [format "The button is %s" $x]
2153 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2154 button. Commands available as a ``target object'' are:
2156 @comment START targetobj commands.
2158 @item @b{configure} - configure the target; see Target Config/Cget Options below
2159 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
2160 @item @b{curstate} - current target state (running, halt, etc.
2162 @* Intended for a human to see/read the currently configure target events.
2163 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
2164 @comment start memory
2174 @item @b{Memory To Array, Array To Memory}
2175 @* These are aimed at a machine interface to memory
2177 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
2178 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
2180 @* @b{ARRAYNAME} is the name of an array variable
2181 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
2182 @* @b{ADDRESS} is the target memory address
2183 @* @b{COUNT} is the number of elements to process
2185 @item @b{Used during ``reset''}
2186 @* These commands are used internally by the OpenOCD scripts to deal
2187 with odd reset situations and are not documented here.
2189 @item @b{arp_examine}
2193 @item @b{arp_waitstate}
2195 @item @b{invoke-event} @b{EVENT-NAME}
2196 @* Invokes the specific event manually for the target
2199 @anchor{Target Events}
2200 @section Target Events
2202 At various times, certain things can happen, or you want them to happen.
2206 @item What should happen when GDB connects? Should your target reset?
2207 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2208 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
2211 All of the above items are handled by target events.
2213 To specify an event action, either during target creation, or later
2214 via ``$_TARGETNAME configure'' see this example.
2216 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
2217 target event name, and BODY is a Tcl procedure or string of commands
2220 The programmers model is the ``-command'' option used in Tcl/Tk
2221 buttons and events. Below are two identical examples, the first
2222 creates and invokes small procedure. The second inlines the procedure.
2225 proc my_attach_proc @{ @} @{
2229 mychip.cpu configure -event gdb-attach my_attach_proc
2230 mychip.cpu configure -event gdb-attach @{
2236 @section Current Events
2237 The following events are available:
2239 @item @b{debug-halted}
2240 @* The target has halted for debug reasons (i.e.: breakpoint)
2241 @item @b{debug-resumed}
2242 @* The target has resumed (i.e.: gdb said run)
2243 @item @b{early-halted}
2244 @* Occurs early in the halt process
2245 @item @b{examine-end}
2246 @* Currently not used (goal: when JTAG examine completes)
2247 @item @b{examine-start}
2248 @* Currently not used (goal: when JTAG examine starts)
2249 @item @b{gdb-attach}
2250 @* When GDB connects
2251 @item @b{gdb-detach}
2252 @* When GDB disconnects
2254 @* When the taret has halted and GDB is not doing anything (see early halt)
2255 @item @b{gdb-flash-erase-start}
2256 @* Before the GDB flash process tries to erase the flash
2257 @item @b{gdb-flash-erase-end}
2258 @* After the GDB flash process has finished erasing the flash
2259 @item @b{gdb-flash-write-start}
2260 @* Before GDB writes to the flash
2261 @item @b{gdb-flash-write-end}
2262 @* After GDB writes to the flash
2264 @* Before the taret steps, gdb is trying to start/resume the target
2266 @* The target has halted
2267 @item @b{old-gdb_program_config}
2268 @* DO NOT USE THIS: Used internally
2269 @item @b{old-pre_resume}
2270 @* DO NOT USE THIS: Used internally
2271 @item @b{reset-assert-pre}
2272 @* Before reset is asserted on the tap.
2273 @item @b{reset-assert-post}
2274 @* Reset is now asserted on the tap.
2275 @item @b{reset-deassert-pre}
2276 @* Reset is about to be released on the tap
2277 @item @b{reset-deassert-post}
2278 @* Reset has been released on the tap
2280 @* Currently not used.
2281 @item @b{reset-halt-post}
2282 @* Currently not usd
2283 @item @b{reset-halt-pre}
2284 @* Currently not used
2285 @item @b{reset-init}
2286 @* Used by @b{reset init} command for board-specific initialization.
2287 This is where you would configure PLLs and clocking, set up DRAM so
2288 you can download programs that don't fit in on-chip SRAM, set up pin
2289 multiplexing, and so on.
2290 @item @b{reset-start}
2291 @* Currently not used
2292 @item @b{reset-wait-pos}
2293 @* Currently not used
2294 @item @b{reset-wait-pre}
2295 @* Currently not used
2296 @item @b{resume-start}
2297 @* Before any target is resumed
2298 @item @b{resume-end}
2299 @* After all targets have resumed
2303 @* Target has resumed
2306 @anchor{Target Create}
2307 @section Target Create
2309 @cindex target creation
2312 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2314 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2315 @comment START params
2318 @* Is the name of the debug target. By convention it should be the tap
2319 DOTTED.NAME. This name is also used to create the target object
2320 command, and in other places the target needs to be identified.
2322 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2323 @comment START types
2340 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2341 @comment START mandatory
2343 @item @b{-endian big|little}
2344 @item @b{-chain-position DOTTED.NAME}
2345 @comment end MANDATORY
2350 @section Target Config/Cget Options
2351 These options can be specified when the target is created, or later
2352 via the configure option or to query the target via cget.
2354 You should specify a working area if you can; typically it uses some
2355 on-chip SRAM. Such a working area can speed up many things, including bulk
2356 writes to target memory; flash operations like checking to see if memory needs
2357 to be erased; GDB memory checksumming; and may help perform otherwise
2358 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2360 @item @b{-type} - returns the target type
2361 @item @b{-event NAME BODY} see Target events
2362 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2363 which will be used when an MMU is active.
2364 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2365 which will be used when an MMU is inactive.
2366 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2367 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2368 by default, it doesn't. When possible, use a working_area that doesn't
2369 need to be backed up, since performing a backup slows down operations.
2370 @item @b{-endian [big|little]}
2371 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2372 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2376 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2377 set name [target number $x]
2378 set y [$name cget -endian]
2379 set z [$name cget -type]
2380 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2384 @b{PROBLEM:} On more complex chips, the work area can become
2385 inaccessible when application code enables or disables the MMU.
2386 For example, the MMU context used to acess the virtual address
2387 will probably matter.
2389 @section Target Variants
2392 @* Use variant @option{lm3s} when debugging older Stellaris LM3S targets.
2393 This will cause OpenOCD to use a software reset rather than asserting
2394 SRST, to avoid a issue with clearing the debug registers.
2395 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2396 be detected and the normal reset behaviour used.
2398 @*Supported variants are
2399 @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
2400 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
2402 @* Use variant @option{ejtag_srst} when debugging targets that do not
2403 provide a functional SRST line on the EJTAG connector. This causes
2404 OpenOCD to instead use an EJTAG software reset command to reset the
2405 processor. You still need to enable @option{srst} on the reset
2406 configuration command to enable OpenOCD hardware reset functionality.
2407 @comment END variants
2410 @node Flash Commands
2411 @chapter Flash Commands
2413 OpenOCD has different commands for NOR and NAND flash;
2414 the ``flash'' command works with NOR flash, while
2415 the ``nand'' command works with NAND flash.
2416 This partially reflects different hardware technologies:
2417 NOR flash usually supports direct CPU instruction and data bus access,
2418 while data from a NAND flash must be copied to memory before it can be
2419 used. (SPI flash must also be copied to memory before use.)
2420 However, the documentation also uses ``flash'' as a generic term;
2421 for example, ``Put flash configuration in board-specific files''.
2424 As of 28-nov-2008 OpenOCD does not know how to program a SPI
2425 flash that a micro may boot from. Perhaps you, the reader, would like to
2426 contribute support for this.
2431 @item Configure via the command @command{flash bank}
2432 @* Do this in a board-specific configuration file,
2433 passing parameters as needed by the driver.
2434 @item Operate on the flash via @command{flash subcommand}
2435 @* Often commands to manipulate the flash are typed by a human, or run
2436 via a script in some automated way. Common tasks include writing a
2437 boot loader, operating system, or other data.
2439 @* Flashing via GDB requires the flash be configured via ``flash
2440 bank'', and the GDB flash features be enabled.
2441 @xref{GDB Configuration}.
2444 Many CPUs have the ablity to ``boot'' from the first flash bank.
2445 This means that misprograming that bank can ``brick'' a system,
2446 so that it can't boot.
2447 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
2448 board by (re)installing working boot firmware.
2450 @section Flash Configuration Commands
2451 @cindex flash configuration
2453 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
2454 Configures a flash bank which provides persistent storage
2455 for addresses from @math{base} to @math{base + size - 1}.
2456 These banks will often be visible to GDB through the target's memory map.
2457 In some cases, configuring a flash bank will activate extra commands;
2458 see the driver-specific documentation.
2461 @item @var{driver} ... identifies the controller driver
2462 associated with the flash bank being declared.
2463 This is usually @code{cfi} for external flash, or else
2464 the name of a microcontroller with embedded flash memory.
2465 @xref{Flash Driver List}.
2466 @item @var{base} ... Base address of the flash chip.
2467 @item @var{size} ... Size of the chip, in bytes.
2468 For some drivers, this value is detected from the hardware.
2469 @item @var{chip_width} ... Width of the flash chip, in bytes;
2470 ignored for most microcontroller drivers.
2471 @item @var{bus_width} ... Width of the data bus used to access the
2472 chip, in bytes; ignored for most microcontroller drivers.
2473 @item @var{target} ... Names the target used to issue
2474 commands to the flash controller.
2475 @comment Actually, it's currently a controller-specific parameter...
2476 @item @var{driver_options} ... drivers may support, or require,
2477 additional parameters. See the driver-specific documentation
2478 for more information.
2481 This command is not available after OpenOCD initialization has completed.
2482 Use it in board specific configuration files, not interactively.
2486 @comment the REAL name for this command is "ocd_flash_banks"
2487 @comment less confusing would be: "flash list" (like "nand list")
2488 @deffn Command {flash banks}
2489 Prints a one-line summary of each device declared
2490 using @command{flash bank}, numbered from zero.
2491 Note that this is the @emph{plural} form;
2492 the @emph{singular} form is a very different command.
2495 @deffn Command {flash probe} num
2496 Identify the flash, or validate the parameters of the configured flash. Operation
2497 depends on the flash type.
2498 The @var{num} parameter is a value shown by @command{flash banks}.
2499 Most flash commands will implicitly @emph{autoprobe} the bank;
2500 flash drivers can distinguish between probing and autoprobing,
2501 but most don't bother.
2504 @section Erasing, Reading, Writing to Flash
2505 @cindex flash erasing
2506 @cindex flash reading
2507 @cindex flash writing
2508 @cindex flash programming
2510 One feature distinguishing NOR flash from NAND or serial flash technologies
2511 is that for read access, it acts exactly like any other addressible memory.
2512 This means you can use normal memory read commands like @command{mdw} or
2513 @command{dump_image} with it, with no special @command{flash} subcommands.
2514 @xref{Memory access}, and @ref{Image access}.
2516 Write access works differently. Flash memory normally needs to be erased
2517 before it's written. Erasing a sector turns all of its bits to ones, and
2518 writing can turn ones into zeroes. This is why there are special commands
2519 for interactive erasing and writing, and why GDB needs to know which parts
2520 of the address space hold NOR flash memory.
2523 Most of these erase and write commands leverage the fact that NOR flash
2524 chips consume target address space. They implicitly refer to the current
2525 JTAG target, and map from an address in that target's address space
2526 back to a flash bank.
2527 @comment In May 2009, those mappings may fail if any bank associated
2528 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
2529 A few commands use abstract addressing based on bank and sector numbers,
2530 and don't depend on searching the current target and its address space.
2531 Avoid confusing the two command models.
2534 Some flash chips implement software protection against accidental writes,
2535 since such buggy writes could in some cases ``brick'' a system.
2536 For such systems, erasing and writing may require sector protection to be
2538 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
2539 and AT91SAM7 on-chip flash.
2540 @xref{flash protect}.
2542 @anchor{flash erase_sector}
2543 @deffn Command {flash erase_sector} num first last
2544 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
2545 @var{last}. Sector numbering starts at 0.
2546 The @var{num} parameter is a value shown by @command{flash banks}.
2549 @deffn Command {flash erase_address} address length
2550 Erase sectors starting at @var{address} for @var{length} bytes.
2551 The flash bank to use is inferred from the @var{address}, and
2552 the specified length must stay within that bank.
2553 As a special case, when @var{length} is zero and @var{address} is
2554 the start of the bank, the whole flash is erased.
2557 @deffn Command {flash fillw} address word length
2558 @deffnx Command {flash fillh} address halfword length
2559 @deffnx Command {flash fillb} address byte length
2560 Fills flash memory with the specified @var{word} (32 bits),
2561 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2562 starting at @var{address} and continuing
2563 for @var{length} units (word/halfword/byte).
2564 No erasure is done before writing; when needed, that must be done
2565 before issuing this command.
2566 Writes are done in blocks of up to 1024 bytes, and each write is
2567 verified by reading back the data and comparing it to what was written.
2568 The flash bank to use is inferred from the @var{address} of
2569 each block, and the specified length must stay within that bank.
2571 @comment no current checks for errors if fill blocks touch multiple banks!
2573 @anchor{flash write_bank}
2574 @deffn Command {flash write_bank} num filename offset
2575 Write the binary @file{filename} to flash bank @var{num},
2576 starting at @var{offset} bytes from the beginning of the bank.
2577 The @var{num} parameter is a value shown by @command{flash banks}.
2580 @anchor{flash write_image}
2581 @deffn Command {flash write_image} [erase] filename [offset] [type]
2582 Write the image @file{filename} to the current target's flash bank(s).
2583 A relocation @var{offset} may be specified, in which case it is added
2584 to the base address for each section in the image.
2585 The file [@var{type}] can be specified
2586 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
2587 @option{elf} (ELF file), @option{s19} (Motorola s19).
2588 @option{mem}, or @option{builder}.
2589 The relevant flash sectors will be erased prior to programming
2590 if the @option{erase} parameter is given.
2591 The flash bank to use is inferred from the @var{address} of
2595 @section Other Flash commands
2596 @cindex flash protection
2598 @deffn Command {flash erase_check} num
2599 Check erase state of sectors in flash bank @var{num},
2600 and display that status.
2601 The @var{num} parameter is a value shown by @command{flash banks}.
2602 This is the only operation that
2603 updates the erase state information displayed by @option{flash info}. That means you have
2604 to issue an @command{flash erase_check} command after erasing or programming the device
2605 to get updated information.
2606 (Code execution may have invalidated any state records kept by OpenOCD.)
2609 @deffn Command {flash info} num
2610 Print info about flash bank @var{num}
2611 The @var{num} parameter is a value shown by @command{flash banks}.
2612 The information includes per-sector protect status.
2615 @anchor{flash protect}
2616 @deffn Command {flash protect} num first last (on|off)
2617 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
2618 @var{first} to @var{last} of flash bank @var{num}.
2619 The @var{num} parameter is a value shown by @command{flash banks}.
2622 @deffn Command {flash protect_check} num
2623 Check protection state of sectors in flash bank @var{num}.
2624 The @var{num} parameter is a value shown by @command{flash banks}.
2625 @comment @option{flash erase_sector} using the same syntax.
2628 @anchor{Flash Driver List}
2629 @section Flash Drivers, Options, and Commands
2630 As noted above, the @command{flash bank} command requires a driver name,
2631 and allows driver-specific options and behaviors.
2632 Some drivers also activate driver-specific commands.
2634 @subsection External Flash
2636 @deffn {Flash Driver} cfi
2637 @cindex Common Flash Interface
2639 The ``Common Flash Interface'' (CFI) is the main standard for
2640 external NOR flash chips, each of which connects to a
2641 specific external chip select on the CPU.
2642 Frequently the first such chip is used to boot the system.
2643 Your board's @code{reset-init} handler might need to
2644 configure additional chip selects using other commands (like: @command{mww} to
2645 configure a bus and its timings) , or
2646 perhaps configure a GPIO pin that controls the ``write protect'' pin
2648 The CFI driver can use a target-specific working area to significantly
2651 The CFI driver can accept the following optional parameters, in any order:
2654 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
2655 like AM29LV010 and similar types.
2656 @item @var{x16_as_x8} ...
2659 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
2660 wide on a sixteen bit bus:
2663 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
2664 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
2668 @subsection Internal Flash (Microcontrollers)
2670 @deffn {Flash Driver} aduc702x
2671 The ADUC702x analog microcontrollers from ST Micro
2672 include internal flash and use ARM7TDMI cores.
2673 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
2674 The setup command only requires the @var{target} argument
2675 since all devices in this family have the same memory layout.
2678 flash bank aduc702x 0 0 0 0 $_TARGETNAME
2682 @deffn {Flash Driver} at91sam7
2683 All members of the AT91SAM7 microcontroller family from Atmel
2684 include internal flash and use ARM7TDMI cores.
2685 The driver automatically recognizes a number of these chips using
2686 the chip identification register, and autoconfigures itself.
2689 flash bank at91sam7 0 0 0 0 $_TARGETNAME
2692 For chips which are not recognized by the controller driver, you must
2693 provide additional parameters in the following order:
2696 @item @var{chip_model} ... label used with @command{flash info}
2698 @item @var{sectors_per_bank}
2699 @item @var{pages_per_sector}
2700 @item @var{pages_size}
2701 @item @var{num_nvm_bits}
2702 @item @var{freq_khz} ... required if an external clock is provided,
2703 optional (but recommended) when the oscillator frequency is known
2706 It is recommended that you provide zeroes for all of those values
2707 except the clock frequency, so that everything except that frequency
2708 will be autoconfigured.
2709 Knowing the frequency helps ensure correct timings for flash access.
2711 The flash controller handles erases automatically on a page (128/256 byte)
2712 basis, so explicit erase commands are not necessary for flash programming.
2713 However, there is an ``EraseAll`` command that can erase an entire flash
2714 plane (of up to 256KB), and it will be used automatically when you issue
2715 @command{flash erase_sector} or @command{flash erase_address} commands.
2717 @deffn Command {at91sam7 gpnvm} bitnum (set|clear)
2718 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
2719 bit for the processor. Each processor has a number of such bits,
2720 used for controlling features such as brownout detection (so they
2721 are not truly general purpose).
2723 This assumes that the first flash bank (number 0) is associated with
2724 the appropriate at91sam7 target.
2729 @deffn {Flash Driver} avr
2730 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
2731 @emph{The current implementation is incomplete.}
2732 @comment - defines mass_erase ... pointless given flash_erase_address
2735 @deffn {Flash Driver} ecosflash
2736 @emph{No idea what this is...}
2737 The @var{ecosflash} driver defines one mandatory parameter,
2738 the name of a modules of target code which is downloaded
2742 @deffn {Flash Driver} lpc2000
2743 Most members of the LPC2000 microcontroller family from NXP
2744 include internal flash and use ARM7TDMI cores.
2745 The @var{lpc2000} driver defines two mandatory and one optional parameters,
2746 which must appear in the following order:
2749 @item @var{variant} ... required, may be
2750 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2751 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
2752 @item @var{clock_kHz} ... the frequency, in kiloHertz,
2753 at which the core is running
2754 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
2755 telling the driver to calculate a valid checksum for the exception vector table.
2758 LPC flashes don't require the chip and bus width to be specified.
2761 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
2762 lpc2000_v2 14765 calc_checksum
2766 @deffn {Flash Driver} lpc288x
2767 The LPC2888 microcontroller from NXP needs slightly different flash
2768 support from its lpc2000 siblings.
2769 The @var{lpc288x} driver defines one mandatory parameter,
2770 the programming clock rate in Hz.
2771 LPC flashes don't require the chip and bus width to be specified.
2774 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
2778 @deffn {Flash Driver} ocl
2779 @emph{No idea what this is, other than using some arm7/arm9 core.}
2782 flash bank ocl 0 0 0 0 $_TARGETNAME
2786 @deffn {Flash Driver} pic32mx
2787 The PIC32MX microcontrollers are based on the MIPS 4K cores,
2788 and integrate flash memory.
2789 @emph{The current implementation is incomplete.}
2792 flash bank pix32mx 0 0 0 0 $_TARGETNAME
2795 @comment numerous *disabled* commands are defined:
2796 @comment - chip_erase ... pointless given flash_erase_address
2797 @comment - lock, unlock ... pointless given protect on/off (yes?)
2798 @comment - pgm_word ... shouldn't bank be deduced from address??
2799 Some pic32mx-specific commands are defined:
2800 @deffn Command {pic32mx pgm_word} address value bank
2801 Programs the specified 32-bit @var{value} at the given @var{address}
2802 in the specified chip @var{bank}.
2806 @deffn {Flash Driver} stellaris
2807 All members of the Stellaris LM3Sxxx microcontroller family from
2809 include internal flash and use ARM Cortex M3 cores.
2810 The driver automatically recognizes a number of these chips using
2811 the chip identification register, and autoconfigures itself.
2812 @footnote{Currently there is a @command{stellaris mass_erase} command.
2813 That seems pointless since the same effect can be had using the
2814 standard @command{flash erase_address} command.}
2817 flash bank stellaris 0 0 0 0 $_TARGETNAME
2821 @deffn {Flash Driver} stm32x
2822 All members of the STM32 microcontroller family from ST Microelectronics
2823 include internal flash and use ARM Cortex M3 cores.
2824 The driver automatically recognizes a number of these chips using
2825 the chip identification register, and autoconfigures itself.
2828 flash bank stm32x 0 0 0 0 $_TARGETNAME
2831 Some stm32x-specific commands
2832 @footnote{Currently there is a @command{stm32x mass_erase} command.
2833 That seems pointless since the same effect can be had using the
2834 standard @command{flash erase_address} command.}
2837 @deffn Command {stm32x lock} num
2838 Locks the entire stm32 device.
2839 The @var{num} parameter is a value shown by @command{flash banks}.
2842 @deffn Command {stm32x unlock} num
2843 Unlocks the entire stm32 device.
2844 The @var{num} parameter is a value shown by @command{flash banks}.
2847 @deffn Command {stm32x options_read} num
2848 Read and display the stm32 option bytes written by
2849 the @command{stm32x options_write} command.
2850 The @var{num} parameter is a value shown by @command{flash banks}.
2853 @deffn Command {stm32x options_write} num (SWWDG|HWWDG) (RSTSTNDBY|NORSTSTNDBY) (RSTSTOP|NORSTSTOP)
2854 Writes the stm32 option byte with the specified values.
2855 The @var{num} parameter is a value shown by @command{flash banks}.
2859 @deffn {Flash Driver} str7x
2860 All members of the STR7 microcontroller family from ST Microelectronics
2861 include internal flash and use ARM7TDMI cores.
2862 The @var{str7x} driver defines one mandatory parameter, @var{variant},
2863 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
2866 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
2870 @deffn {Flash Driver} str9x
2871 Most members of the STR9 microcontroller family from ST Microelectronics
2872 include internal flash and use ARM966E cores.
2873 The str9 needs the flash controller to be configured using
2874 the @command{str9x flash_config} command prior to Flash programming.
2877 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
2878 str9x flash_config 0 4 2 0 0x80000
2881 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
2882 Configures the str9 flash controller.
2883 The @var{num} parameter is a value shown by @command{flash banks}.
2886 @item @var{bbsr} - Boot Bank Size register
2887 @item @var{nbbsr} - Non Boot Bank Size register
2888 @item @var{bbadr} - Boot Bank Start Address register
2889 @item @var{nbbadr} - Boot Bank Start Address register
2895 @deffn {Flash Driver} tms470
2896 Most members of the TMS470 microcontroller family from Texas Instruments
2897 include internal flash and use ARM7TDMI cores.
2898 This driver doesn't require the chip and bus width to be specified.
2900 Some tms470-specific commands are defined:
2902 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
2903 Saves programming keys in a register, to enable flash erase and write commands.
2906 @deffn Command {tms470 osc_mhz} clock_mhz
2907 Reports the clock speed, which is used to calculate timings.
2910 @deffn Command {tms470 plldis} (0|1)
2911 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
2916 @subsection str9xpec driver
2919 Here is some background info to help
2920 you better understand how this driver works. OpenOCD has two flash drivers for
2924 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2925 flash programming as it is faster than the @option{str9xpec} driver.
2927 Direct programming @option{str9xpec} using the flash controller. This is an
2928 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2929 core does not need to be running to program using this flash driver. Typical use
2930 for this driver is locking/unlocking the target and programming the option bytes.
2933 Before we run any commands using the @option{str9xpec} driver we must first disable
2934 the str9 core. This example assumes the @option{str9xpec} driver has been
2935 configured for flash bank 0.
2937 # assert srst, we do not want core running
2938 # while accessing str9xpec flash driver
2940 # turn off target polling
2943 str9xpec enable_turbo 0
2945 str9xpec options_read 0
2946 # re-enable str9 core
2947 str9xpec disable_turbo 0
2951 The above example will read the str9 option bytes.
2952 When performing a unlock remember that you will not be able to halt the str9 - it
2953 has been locked. Halting the core is not required for the @option{str9xpec} driver
2954 as mentioned above, just issue the commands above manually or from a telnet prompt.
2956 @subsubsection str9xpec driver options
2958 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2959 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2960 @option{enable_turbo} <@var{num>.}
2962 Only use this driver for locking/unlocking the device or configuring the option bytes.
2963 Use the standard str9 driver for programming.
2965 @subsubsection str9xpec specific commands
2966 @cindex str9xpec specific commands
2967 These are flash specific commands when using the str9xpec driver.
2970 @item @b{str9xpec enable_turbo} <@var{num}>
2971 @cindex str9xpec enable_turbo
2972 @*enable turbo mode, will simply remove the str9 from the chain and talk
2973 directly to the embedded flash controller.
2974 @item @b{str9xpec disable_turbo} <@var{num}>
2975 @cindex str9xpec disable_turbo
2976 @*restore the str9 into JTAG chain.
2977 @item @b{str9xpec lock} <@var{num}>
2978 @cindex str9xpec lock
2979 @*lock str9 device. The str9 will only respond to an unlock command that will
2981 @item @b{str9xpec unlock} <@var{num}>
2982 @cindex str9xpec unlock
2983 @*unlock str9 device.
2984 @item @b{str9xpec options_read} <@var{num}>
2985 @cindex str9xpec options_read
2986 @*read str9 option bytes.
2987 @item @b{str9xpec options_write} <@var{num}>
2988 @cindex str9xpec options_write
2989 @*write str9 option bytes.
2992 @subsubsection STR9 option byte configuration
2993 @cindex STR9 option byte configuration
2996 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2997 @cindex str9xpec options_cmap
2998 @*configure str9 boot bank.
2999 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
3000 @cindex str9xpec options_lvdthd
3001 @*configure str9 lvd threshold.
3002 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
3003 @cindex str9xpec options_lvdsel
3004 @*configure str9 lvd source.
3005 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
3006 @cindex str9xpec options_lvdwarn
3007 @*configure str9 lvd reset warning source.
3012 @subsection mFlash Configuration
3013 @cindex mFlash Configuration
3014 @b{mflash bank} <@var{soc}> <@var{base}> <@var{RST pin}> <@var{target}>
3016 @*Configures a mflash for <@var{soc}> host bank at
3017 <@var{base}>. Pin number format is dependent on host GPIO calling convention.
3018 Currently, mflash bank support s3c2440 and pxa270.
3020 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1.
3023 mflash bank s3c2440 0x10000000 1b 0
3026 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43.
3029 mflash bank pxa270 0x08000000 43 0
3032 @subsection mFlash commands
3033 @cindex mFlash commands
3036 @item @b{mflash probe}
3037 @cindex mflash probe
3039 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
3040 @cindex mflash write
3041 @*Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
3042 <@var{offset}> bytes from the beginning of the bank.
3043 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
3045 @*Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
3047 @item @b{mflash config pll} <@var{frequency}>
3048 @cindex mflash config pll
3049 @*Configure mflash pll. <@var{frequency}> is input frequency of mflash. The order is Hz.
3050 Issuing this command will erase mflash's whole internal nand and write new pll.
3051 After this command, mflash needs power-on-reset for normal operation.
3052 If pll was newly configured, storage and boot(optional) info also need to be update.
3053 @item @b{mflash config boot}
3054 @cindex mflash config boot
3055 @*Configure bootable option. If bootable option is set, mflash offer the first 8 sectors
3057 @item @b{mflash config storage}
3058 @cindex mflash config storage
3059 @*Configure storage information. For the normal storage operation, this information must be
3063 @node NAND Flash Commands
3064 @chapter NAND Flash Commands
3067 Compared to NOR or SPI flash, NAND devices are inexpensive
3068 and high density. Today's NAND chips, and multi-chip modules,
3069 commonly hold multiple GigaBytes of data.
3071 NAND chips consist of a number of ``erase blocks'' of a given
3072 size (such as 128 KBytes), each of which is divided into a
3073 number of pages (of perhaps 512 or 2048 bytes each). Each
3074 page of a NAND flash has an ``out of band'' (OOB) area to hold
3075 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3076 of OOB for every 512 bytes of page data.
3078 One key characteristic of NAND flash is that its error rate
3079 is higher than that of NOR flash. In normal operation, that
3080 ECC is used to correct and detect errors. However, NAND
3081 blocks can also wear out and become unusable; those blocks
3082 are then marked "bad". NAND chips are even shipped from the
3083 manufacturer with a few bad blocks. The highest density chips
3084 use a technology (MLC) that wears out more quickly, so ECC
3085 support is increasingly important as a way to detect blocks
3086 that have begun to fail, and help to preserve data integrity
3087 with techniques such as wear leveling.
3089 Software is used to manage the ECC. Some controllers don't
3090 support ECC directly; in those cases, software ECC is used.
3091 Other controllers speed up the ECC calculations with hardware.
3092 Single-bit error correction hardware is routine. Controllers
3093 geared for newer MLC chips may correct 4 or more errors for
3094 every 512 bytes of data.
3096 You will need to make sure that any data you write using
3097 OpenOCD includes the apppropriate kind of ECC. For example,
3098 that may mean passing the @code{oob_softecc} flag when
3099 writing NAND data, or ensuring that the correct hardware
3102 The basic steps for using NAND devices include:
3104 @item Declare via the command @command{nand device}
3105 @* Do this in a board-specific configuration file,
3106 passing parameters as needed by the controller.
3107 @item Configure each device using @command{nand probe}.
3108 @* Do this only after the associated target is set up,
3109 such as in its reset-init script or in procures defined
3110 to access that device.
3111 @item Operate on the flash via @command{nand subcommand}
3112 @* Often commands to manipulate the flash are typed by a human, or run
3113 via a script in some automated way. Common task include writing a
3114 boot loader, operating system, or other data needed to initialize or
3118 @b{NOTE:} At the time this text was written, the largest NAND
3119 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3120 This is because the variables used to hold offsets and lengths
3121 are only 32 bits wide.
3122 (Larger chips may work in some cases, unless an offset or length
3123 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3124 Some larger devices will work, since they are actually multi-chip
3125 modules with two smaller chips and individual chipselect lines.
3127 @section NAND Configuration Commands
3128 @cindex NAND configuration
3130 NAND chips must be declared in configuration scripts,
3131 plus some additional configuration that's done after
3132 OpenOCD has initialized.
3134 @deffn {Config Command} {nand device} controller target [configparams...]
3135 Declares a NAND device, which can be read and written to
3136 after it has been configured through @command{nand probe}.
3137 In OpenOCD, devices are single chips; this is unlike some
3138 operating systems, which may manage multiple chips as if
3139 they were a single (larger) device.
3140 In some cases, configuring a device will activate extra
3141 commands; see the controller-specific documentation.
3143 @b{NOTE:} This command is not available after OpenOCD
3144 initialization has completed. Use it in board specific
3145 configuration files, not interactively.
3148 @item @var{controller} ... identifies the controller driver
3149 associated with the NAND device being declared.
3150 @xref{NAND Driver List}.
3151 @item @var{target} ... names the target used when issuing
3152 commands to the NAND controller.
3153 @comment Actually, it's currently a controller-specific parameter...
3154 @item @var{configparams} ... controllers may support, or require,
3155 additional parameters. See the controller-specific documentation
3156 for more information.
3160 @deffn Command {nand list}
3161 Prints a one-line summary of each device declared
3162 using @command{nand device}, numbered from zero.
3163 Note that un-probed devices show no details.
3166 @deffn Command {nand probe} num
3167 Probes the specified device to determine key characteristics
3168 like its page and block sizes, and how many blocks it has.
3169 The @var{num} parameter is the value shown by @command{nand list}.
3170 You must (successfully) probe a device before you can use
3171 it with most other NAND commands.
3174 @section Erasing, Reading, Writing to NAND Flash
3176 @deffn Command {nand dump} num filename offset length [oob_option]
3177 @cindex NAND reading
3178 Reads binary data from the NAND device and writes it to the file,
3179 starting at the specified offset.
3180 The @var{num} parameter is the value shown by @command{nand list}.
3182 Use a complete path name for @var{filename}, so you don't depend
3183 on the directory used to start the OpenOCD server.
3185 The @var{offset} and @var{length} must be exact multiples of the
3186 device's page size. They describe a data region; the OOB data
3187 associated with each such page may also be accessed.
3189 @b{NOTE:} At the time this text was written, no error correction
3190 was done on the data that's read, unless raw access was disabled
3191 and the underlying NAND controller driver had a @code{read_page}
3192 method which handled that error correction.
3194 By default, only page data is saved to the specified file.
3195 Use an @var{oob_option} parameter to save OOB data:
3197 @item no oob_* parameter
3198 @*Output file holds only page data; OOB is discarded.
3199 @item @code{oob_raw}
3200 @*Output file interleaves page data and OOB data;
3201 the file will be longer than "length" by the size of the
3202 spare areas associated with each data page.
3203 Note that this kind of "raw" access is different from
3204 what's implied by @command{nand raw_access}, which just
3205 controls whether a hardware-aware access method is used.
3206 @item @code{oob_only}
3207 @*Output file has only raw OOB data, and will
3208 be smaller than "length" since it will contain only the
3209 spare areas associated with each data page.
3213 @deffn Command {nand erase} num offset length
3214 @cindex NAND erasing
3215 @cindex NAND programming
3216 Erases blocks on the specified NAND device, starting at the
3217 specified @var{offset} and continuing for @var{length} bytes.
3218 Both of those values must be exact multiples of the device's
3219 block size, and the region they specify must fit entirely in the chip.
3220 The @var{num} parameter is the value shown by @command{nand list}.
3222 @b{NOTE:} This command will try to erase bad blocks, when told
3223 to do so, which will probably invalidate the manufacturer's bad
3225 For the remainder of the current server session, @command{nand info}
3226 will still report that the block ``is'' bad.
3229 @deffn Command {nand write} num filename offset [option...]
3230 @cindex NAND writing
3231 @cindex NAND programming
3232 Writes binary data from the file into the specified NAND device,
3233 starting at the specified offset. Those pages should already
3234 have been erased; you can't change zero bits to one bits.
3235 The @var{num} parameter is the value shown by @command{nand list}.
3237 Use a complete path name for @var{filename}, so you don't depend
3238 on the directory used to start the OpenOCD server.
3240 The @var{offset} must be an exact multiple of the device's page size.
3241 All data in the file will be written, assuming it doesn't run
3242 past the end of the device.
3243 Only full pages are written, and any extra space in the last
3244 page will be filled with 0xff bytes. (That includes OOB data,
3245 if that's being written.)
3247 @b{NOTE:} At the time this text was written, bad blocks are
3248 ignored. That is, this routine will not skip bad blocks,
3249 but will instead try to write them. This can cause problems.
3251 Provide at most one @var{option} parameter. With some
3252 NAND drivers, the meanings of these parameters may change
3253 if @command{nand raw_access} was used to disable hardware ECC.
3255 @item no oob_* parameter
3256 @*File has only page data, which is written.
3257 If raw acccess is in use, the OOB area will not be written.
3258 Otherwise, if the underlying NAND controller driver has
3259 a @code{write_page} routine, that routine may write the OOB
3260 with hardware-computed ECC data.
3261 @item @code{oob_only}
3262 @*File has only raw OOB data, which is written to the OOB area.
3263 Each page's data area stays untouched. @i{This can be a dangerous
3264 option}, since it can invalidate the ECC data.
3265 You may need to force raw access to use this mode.
3266 @item @code{oob_raw}
3267 @*File interleaves data and OOB data, both of which are written
3268 If raw access is enabled, the data is written first, then the
3270 Otherwise, if the underlying NAND controller driver has
3271 a @code{write_page} routine, that routine may modify the OOB
3272 before it's written, to include hardware-computed ECC data.
3273 @item @code{oob_softecc}
3274 @*File has only page data, which is written.
3275 The OOB area is filled with 0xff, except for a standard 1-bit
3276 software ECC code stored in conventional locations.
3277 You might need to force raw access to use this mode, to prevent
3278 the underlying driver from applying hardware ECC.
3279 @item @code{oob_softecc_kw}
3280 @*File has only page data, which is written.
3281 The OOB area is filled with 0xff, except for a 4-bit software ECC
3282 specific to the boot ROM in Marvell Kirkwood SoCs.
3283 You might need to force raw access to use this mode, to prevent
3284 the underlying driver from applying hardware ECC.
3288 @section Other NAND commands
3289 @cindex NAND other commands
3291 @deffn Command {nand check_bad_blocks} [offset length]
3292 Checks for manufacturer bad block markers on the specified NAND
3293 device. If no parameters are provided, checks the whole
3294 device; otherwise, starts at the specified @var{offset} and
3295 continues for @var{length} bytes.
3296 Both of those values must be exact multiples of the device's
3297 block size, and the region they specify must fit entirely in the chip.
3298 The @var{num} parameter is the value shown by @command{nand list}.
3300 @b{NOTE:} Before using this command you should force raw access
3301 with @command{nand raw_access enable} to ensure that the underlying
3302 driver will not try to apply hardware ECC.
3305 @deffn Command {nand info} num
3306 The @var{num} parameter is the value shown by @command{nand list}.
3307 This prints the one-line summary from "nand list", plus for
3308 devices which have been probed this also prints any known
3309 status for each block.
3312 @deffn Command {nand raw_access} num <enable|disable>
3313 Sets or clears an flag affecting how page I/O is done.
3314 The @var{num} parameter is the value shown by @command{nand list}.
3316 This flag is cleared (disabled) by default, but changing that
3317 value won't affect all NAND devices. The key factor is whether
3318 the underlying driver provides @code{read_page} or @code{write_page}
3319 methods. If it doesn't provide those methods, the setting of
3320 this flag is irrelevant; all access is effectively ``raw''.
3322 When those methods exist, they are normally used when reading
3323 data (@command{nand dump} or reading bad block markers) or
3324 writing it (@command{nand write}). However, enabling
3325 raw access (setting the flag) prevents use of those methods,
3326 bypassing hardware ECC logic.
3327 @i{This can be a dangerous option}, since writing blocks
3328 with the wrong ECC data can cause them to be marked as bad.
3331 @anchor{NAND Driver List}
3332 @section NAND Drivers, Options, and Commands
3333 As noted above, the @command{nand device} command allows
3334 driver-specific options and behaviors.
3335 Some controllers also activate controller-specific commands.
3337 @deffn {NAND Driver} davinci
3338 This driver handles the NAND controllers found on DaVinci family
3339 chips from Texas Instruments.
3340 It takes three extra parameters:
3341 address of the NAND chip;
3342 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
3343 address of the AEMIF controller on this processor.
3345 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
3347 All DaVinci processors support the single-bit ECC hardware,
3348 and newer ones also support the four-bit ECC hardware.
3349 The @code{write_page} and @code{read_page} methods are used
3350 to implement those ECC modes, unless they are disabled using
3351 the @command{nand raw_access} command.
3354 @deffn {NAND Driver} lpc3180
3355 These controllers require an extra @command{nand device}
3356 parameter: the clock rate used by the controller.
3357 @deffn Command {lpc3180 select} num [mlc|slc]
3358 Configures use of the MLC or SLC controller mode.
3359 MLC implies use of hardware ECC.
3360 The @var{num} parameter is the value shown by @command{nand list}.
3363 At this writing, this driver includes @code{write_page}
3364 and @code{read_page} methods. Using @command{nand raw_access}
3365 to disable those methods will prevent use of hardware ECC
3366 in the MLC controller mode, but won't change SLC behavior.
3368 @comment current lpc3180 code won't issue 5-byte address cycles
3370 @deffn {NAND Driver} orion
3371 These controllers require an extra @command{nand device}
3372 parameter: the address of the controller.
3374 nand device orion 0xd8000000
3376 These controllers don't define any specialized commands.
3377 At this writing, their drivers don't include @code{write_page}
3378 or @code{read_page} methods, so @command{nand raw_access} won't
3379 change any behavior.
3382 @deffn {NAND Driver} s3c2410
3383 @deffnx {NAND Driver} s3c2412
3384 @deffnx {NAND Driver} s3c2440
3385 @deffnx {NAND Driver} s3c2443
3386 These S3C24xx family controllers don't have any special
3387 @command{nand device} options, and don't define any
3388 specialized commands.
3389 At this writing, their drivers don't include @code{write_page}
3390 or @code{read_page} methods, so @command{nand raw_access} won't
3391 change any behavior.
3394 @node General Commands
3395 @chapter General Commands
3398 The commands documented in this chapter here are common commands that
3399 you, as a human, may want to type and see the output of. Configuration type
3400 commands are documented elsewhere.
3404 @item @b{Source Of Commands}
3405 @* OpenOCD commands can occur in a configuration script (discussed
3406 elsewhere) or typed manually by a human or supplied programatically,
3407 or via one of several TCP/IP Ports.
3409 @item @b{From the human}
3410 @* A human should interact with the telnet interface (default port: 4444)
3411 or via GDB (default port 3333).
3413 To issue commands from within a GDB session, use the @option{monitor}
3414 command, e.g. use @option{monitor poll} to issue the @option{poll}
3415 command. All output is relayed through the GDB session.
3417 @item @b{Machine Interface}
3418 The Tcl interface's intent is to be a machine interface. The default Tcl
3423 @section Daemon Commands
3425 @subsection sleep [@var{msec}]
3427 @*Wait for n milliseconds before resuming. Useful in connection with script files
3428 (@var{script} command and @var{target_script} configuration).
3430 @subsection shutdown
3432 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
3434 @anchor{debug_level}
3435 @subsection debug_level [@var{n}]
3437 @*Display or adjust debug level to n<0-3>
3439 @subsection fast [@var{enable|disable}]
3441 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
3442 downloads and fast memory access will work if the JTAG interface isn't too fast and
3443 the core doesn't run at a too low frequency. Note that this option only changes the default
3444 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
3447 The target specific "dangerous" optimisation tweaking options may come and go
3448 as more robust and user friendly ways are found to ensure maximum throughput
3449 and robustness with a minimum of configuration.
3451 Typically the "fast enable" is specified first on the command line:
3454 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
3457 @subsection echo <@var{message}>
3459 @*Output message to stdio. e.g. echo "Programming - please wait"
3461 @subsection log_output <@var{file}>
3463 @*Redirect logging to <file> (default: stderr)
3465 @subsection script <@var{file}>
3467 @*Execute commands from <file>
3468 See also: ``source [find FILENAME]''
3470 @section Target state handling
3471 @subsection power <@var{on}|@var{off}>
3473 @*Turn power switch to target on/off.
3474 No arguments: print status.
3475 Not all interfaces support this.
3477 @subsection reg [@option{#}|@option{name}] [value]
3479 @*Access a single register by its number[@option{#}] or by its [@option{name}].
3480 No arguments: list all available registers for the current target.
3481 Number or name argument: display a register.
3482 Number or name and value arguments: set register value.
3484 @subsection poll [@option{on}|@option{off}]
3486 @*Poll the target for its current state. If the target is in debug mode, architecture
3487 specific information about the current state is printed. An optional parameter
3488 allows continuous polling to be enabled and disabled.
3490 @subsection halt [@option{ms}]
3492 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
3493 Default [@option{ms}] is 5 seconds if no arg given.
3494 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
3495 will stop OpenOCD from waiting.
3497 @subsection wait_halt [@option{ms}]
3499 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
3500 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
3503 @subsection resume [@var{address}]
3505 @*Resume the target at its current code position, or at an optional address.
3506 OpenOCD will wait 5 seconds for the target to resume.
3508 @subsection step [@var{address}]
3510 @*Single-step the target at its current code position, or at an optional address.
3512 @anchor{Reset Command}
3513 @subsection reset [@option{run}|@option{halt}|@option{init}]
3515 @*Perform a hard-reset. The optional parameter specifies what should
3516 happen after the reset.
3517 If there is no parameter, a @command{reset run} is executed.
3518 The other options will not work on all systems.
3519 @xref{Reset Configuration}.
3523 @*Let the target run.
3526 @*Immediately halt the target (works only with certain configurations).
3529 @*Immediately halt the target, and execute the reset script (works only with certain
3533 @subsection soft_reset_halt
3535 @*Requesting target halt and executing a soft reset. This is often used
3536 when a target cannot be reset and halted. The target, after reset is
3537 released begins to execute code. OpenOCD attempts to stop the CPU and
3538 then sets the program counter back to the reset vector. Unfortunately
3539 the code that was executed may have left the hardware in an unknown
3543 @anchor{Memory access}
3544 @section Memory access commands
3546 display available RAM memory on OpenOCD host. Used in OpenOCD regression testing scripts. Mainly
3547 useful on embedded targets, PC type hosts have complimentary tools like Valgrind to address
3548 resource tracking problems.
3549 @subsection Memory peek/poke type commands
3550 These commands allow accesses of a specific size to the memory
3551 system. Often these are used to configure the current target in some
3552 special way. For example - one may need to write certian values to the
3553 SDRAM controller to enable SDRAM.
3556 @item To change the current target see the ``targets'' (plural) command
3557 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
3561 @item @b{mdw} <@var{addr}> [@var{count}]
3563 @*display memory words (32bit)
3564 @item @b{mdh} <@var{addr}> [@var{count}]
3566 @*display memory half-words (16bit)
3567 @item @b{mdb} <@var{addr}> [@var{count}]
3569 @*display memory bytes (8bit)
3570 @item @b{mww} <@var{addr}> <@var{value}>
3572 @*write memory word (32bit)
3573 @item @b{mwh} <@var{addr}> <@var{value}>
3575 @*write memory half-word (16bit)
3576 @item @b{mwb} <@var{addr}> <@var{value}>
3578 @*write memory byte (8bit)
3581 @anchor{Image access}
3582 @section Image loading commands
3584 @subsection load_image
3585 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3587 @*Load image <@var{file}> to target memory at <@var{address}>
3588 @subsection fast_load_image
3589 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3590 @cindex fast_load_image
3591 @*Normally you should be using @b{load_image} or GDB load. However, for
3592 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3593 host), storing the image in memory and uploading the image to the target
3594 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3595 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3596 memory, i.e. does not affect target. This approach is also useful when profiling
3597 target programming performance as I/O and target programming can easily be profiled
3599 @subsection fast_load
3602 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3604 @subsection dump_image
3605 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3607 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3608 (binary) <@var{file}>.
3609 @subsection verify_image
3610 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3611 @cindex verify_image
3612 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3613 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3616 @section Breakpoint commands
3617 @cindex Breakpoint commands
3619 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3621 @*set breakpoint <address> <length> [hw]
3622 @item @b{rbp} <@var{addr}>
3624 @*remove breakpoint <adress>
3625 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3627 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3628 @item @b{rwp} <@var{addr}>
3630 @*remove watchpoint <adress>
3633 @section Misc Commands
3634 @cindex Other Target Commands
3636 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3638 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3642 @node Architecture and Core Commands
3643 @chapter Architecture and Core Commands
3644 @cindex Architecture Specific Commands
3645 @cindex Core Specific Commands
3647 Most CPUs have specialized JTAG operations to support debugging.
3648 OpenOCD packages most such operations in its standard command framework.
3649 Some of those operations don't fit well in that framework, so they are
3650 exposed here as architecture or implementation (core) specific commands.
3652 @anchor{ARM Tracing}
3653 @section ARM Tracing
3657 CPUs based on ARM cores may include standard tracing interfaces,
3658 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
3659 address and data bus trace records to a ``Trace Port''.
3663 Development-oriented boards will sometimes provide a high speed
3664 trace connector for collecting that data, when the particular CPU
3665 supports such an interface.
3666 (The standard connector is a 38-pin Mictor, with both JTAG
3667 and trace port support.)
3668 Those trace connectors are supported by higher end JTAG adapters
3669 and some logic analyzer modules; frequently those modules can
3670 buffer several megabytes of trace data.
3671 Configuring an ETM coupled to such an external trace port belongs
3672 in the board-specific configuration file.
3674 If the CPU doesn't provide an external interface, it probably
3675 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
3676 dedicated SRAM. 4KBytes is one common ETB size.
3677 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
3678 (target) configuration file, since it works the same on all boards.
3681 ETM support in OpenOCD doesn't seem to be widely used yet.
3684 ETM support may be buggy, and at least some @command{etm config}
3685 parameters should be detected by asking the ETM for them.
3686 It seems like a GDB hookup should be possible,
3687 as well as triggering trace on specific events
3688 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
3689 There should be GUI tools to manipulate saved trace data and help
3690 analyse it in conjunction with the source code.
3691 It's unclear how much of a common interface is shared
3692 with the current XScale trace support, or should be
3693 shared with eventual Nexus-style trace module support.
3696 @subsection ETM Configuration
3697 ETM setup is coupled with the trace port driver configuration.
3699 @deffn {Config Command} {etm config} target width mode clocking driver
3700 Declares the ETM associated with @var{target}, and associates it
3701 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
3703 Several of the parameters must reflect the trace port configuration.
3704 The @var{width} must be either 4, 8, or 16.
3705 The @var{mode} must be @option{normal}, @option{multiplexted},
3706 or @option{demultiplexted}.
3707 The @var{clocking} must be @option{half} or @option{full}.
3710 You can see the ETM registers using the @command{reg} command, although
3711 not all of those possible registers are present in every ETM.
3715 @deffn Command {etm info}
3716 Displays information about the current target's ETM.
3719 @deffn Command {etm status}
3720 Displays status of the current target's ETM:
3721 is the ETM idle, or is it collecting data?
3722 Did trace data overflow?
3726 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
3727 Displays what data that ETM will collect.
3728 If arguments are provided, first configures that data.
3729 When the configuration changes, tracing is stopped
3730 and any buffered trace data is invalidated.
3733 @item @var{type} ... one of
3734 @option{none} (save nothing),
3735 @option{data} (save data),
3736 @option{address} (save addresses),
3737 @option{all} (save data and addresses)
3738 @item @var{context_id_bits} ... 0, 8, 16, or 32
3739 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
3740 @item @var{branch_output} ... @option{enable} or @option{disable}
3744 @deffn Command {etm trigger_percent} percent
3745 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
3748 @subsection ETM Trace Operation
3750 After setting up the ETM, you can use it to collect data.
3751 That data can be exported to files for later analysis.
3752 It can also be parsed with OpenOCD, for basic sanity checking.
3754 @deffn Command {etm analyze}
3755 Reads trace data into memory, if it wasn't already present.
3756 Decodes and prints the data that was collected.
3759 @deffn Command {etm dump} filename
3760 Stores the captured trace data in @file{filename}.
3763 @deffn Command {etm image} filename [base_address] [type]
3764 Opens an image file.
3767 @deffn Command {etm load} filename
3768 Loads captured trace data from @file{filename}.
3771 @deffn Command {etm start}
3772 Starts trace data collection.
3775 @deffn Command {etm stop}
3776 Stops trace data collection.
3779 @anchor{Trace Port Drivers}
3780 @subsection Trace Port Drivers
3782 To use an ETM trace port it must be associated with a driver.
3784 @deffn {Trace Port Driver} dummy
3785 Use the @option{dummy} driver if you are configuring an ETM that's
3786 not connected to anything (on-chip ETB or off-chip trace connector).
3787 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
3788 any trace data collection.}
3789 @deffn {Config Command} {etm_dummy config} target
3790 Associates the ETM for @var{target} with a dummy driver.
3794 @deffn {Trace Port Driver} etb
3795 Use the @option{etb} driver if you are configuring an ETM
3796 to use on-chip ETB memory.
3797 @deffn {Config Command} {etb config} target etb_tap
3798 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
3799 You can see the ETB registers using the @command{reg} command.
3803 @deffn {Trace Port Driver} oocd_trace
3804 This driver isn't available unless OpenOCD was explicitly configured
3805 with the @option{--enable-oocd_trace} option. You probably don't want
3806 to configure it unless you've built the appropriate prototype hardware;
3807 it's @emph{proof-of-concept} software.
3809 Use the @option{oocd_trace} driver if you are configuring an ETM that's
3810 connected to an off-chip trace connector.
3812 @deffn {Config Command} {oocd_trace config} target tty
3813 Associates the ETM for @var{target} with a trace driver which
3814 collects data through the serial port @var{tty}.
3817 @deffn Command {oocd_trace resync}
3818 Re-synchronizes with the capture clock.
3821 @deffn Command {oocd_trace status}
3822 Reports whether the capture clock is locked or not.
3827 @section ARMv4 and ARMv5 Architecture
3828 @cindex ARMv4 specific commands
3829 @cindex ARMv5 specific commands
3831 These commands are specific to ARM architecture v4 and v5,
3832 including all ARM7 or ARM9 systems and Intel XScale.
3833 They are available in addition to other core-specific
3834 commands that may be available.
3836 @deffn Command {armv4_5 core_state} [arm|thumb]
3837 Displays the core_state, optionally changing it to process
3838 either @option{arm} or @option{thumb} instructions.
3839 The target may later be resumed in the currently set core_state.
3840 (Processors may also support the Jazelle state, but
3841 that is not currently supported in OpenOCD.)
3844 @deffn Command {armv4_5 disassemble} address count [thumb]
3846 Disassembles @var{count} instructions starting at @var{address}.
3847 If @option{thumb} is specified, Thumb (16-bit) instructions are used;
3848 else ARM (32-bit) instructions are used.
3849 (Processors may also support the Jazelle state, but
3850 those instructions are not currently understood by OpenOCD.)
3853 @deffn Command {armv4_5 reg}
3854 Display a list of all banked core registers, fetching the current value from every
3855 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3859 @subsection ARM7 and ARM9 specific commands
3860 @cindex ARM7 specific commands
3861 @cindex ARM9 specific commands
3863 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
3864 ARM9TDMI, ARM920T or ARM926EJ-S.
3865 They are available in addition to the ARMv4/5 commands,
3866 and any other core-specific commands that may be available.
3868 @deffn Command {arm7_9 dbgrq} (enable|disable)
3869 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
3870 instead of breakpoints. This should be
3871 safe for all but ARM7TDMI--S cores (like Philips LPC).
3874 @deffn Command {arm7_9 dcc_downloads} (enable|disable)
3876 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
3877 amounts of memory. DCC downloads offer a huge speed increase, but might be
3878 unsafe, especially with targets running at very low speeds. This command was introduced
3879 with OpenOCD rev. 60, and requires a few bytes of working area.
3882 @anchor{arm7_9 fast_memory_access}
3883 @deffn Command {arm7_9 fast_memory_access} (enable|disable)
3884 Enable or disable memory writes and reads that don't check completion of
3885 the operation. This provides a huge speed increase, especially with USB JTAG
3886 cables (FT2232), but might be unsafe if used with targets running at very low
3887 speeds, like the 32kHz startup clock of an AT91RM9200.
3890 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
3891 @emph{This is intended for use while debugging OpenOCD; you probably
3894 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
3895 as used in the specified @var{mode}
3896 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
3897 the M4..M0 bits of the PSR).
3898 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
3899 Register 16 is the mode-specific SPSR,
3900 unless the specified mode is 0xffffffff (32-bit all-ones)
3901 in which case register 16 is the CPSR.
3902 The write goes directly to the CPU, bypassing the register cache.
3905 @deffn {Debug Command} {arm7_9 write_xpsr} word (0|1)
3906 @emph{This is intended for use while debugging OpenOCD; you probably
3909 If the second parameter is zero, writes @var{word} to the
3910 Current Program Status register (CPSR).
3911 Else writes @var{word} to the current mode's Saved PSR (SPSR).
3912 In both cases, this bypasses the register cache.
3915 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (0|1)
3916 @emph{This is intended for use while debugging OpenOCD; you probably
3919 Writes eight bits to the CPSR or SPSR,
3920 first rotating them by @math{2*rotate} bits,
3921 and bypassing the register cache.
3922 This has lower JTAG overhead than writing the entire CPSR or SPSR
3923 with @command{arm7_9 write_xpsr}.
3926 @subsection ARM720T specific commands
3927 @cindex ARM720T specific commands
3929 These commands are available to ARM720T based CPUs,
3930 which are implementations of the ARMv4T architecture
3931 based on the ARM7TDMI-S integer core.
3932 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
3934 @deffn Command {arm720t cp15} regnum [value]
3935 Display cp15 register @var{regnum};
3936 else if a @var{value} is provided, that value is written to that register.
3939 @deffn Command {arm720t mdw_phys} addr [count]
3940 @deffnx Command {arm720t mdh_phys} addr [count]
3941 @deffnx Command {arm720t mdb_phys} addr [count]
3942 Display contents of physical address @var{addr}, as
3943 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
3944 or 8-bit bytes (@command{mdb_phys}).
3945 If @var{count} is specified, displays that many units.
3948 @deffn Command {arm720t mww_phys} addr word
3949 @deffnx Command {arm720t mwh_phys} addr halfword
3950 @deffnx Command {arm720t mwb_phys} addr byte
3951 Writes the specified @var{word} (32 bits),
3952 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3953 at the specified physical address @var{addr}.
3956 @deffn Command {arm720t virt2phys} va
3957 Translate a virtual address @var{va} to a physical address
3958 and display the result.
3961 @subsection ARM9TDMI specific commands
3962 @cindex ARM9TDMI specific commands
3964 Many ARM9-family CPUs are built around ARM9TDMI integer cores,
3965 or processors resembling ARM9TDMI, and can use these commands.
3966 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
3968 @deffn Command {arm9tdmi vector_catch} (all|none|list)
3969 Catch arm9 interrupt vectors, can be @option{all}, @option{none},
3970 or a list with one or more of the following:
3971 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3972 @option{irq} @option{fiq}.
3975 @subsection ARM920T specific commands
3976 @cindex ARM920T specific commands
3978 These commands are available to ARM920T based CPUs,
3979 which are implementations of the ARMv4T architecture
3980 built using the ARM9TDMI integer core.
3981 They are available in addition to the ARMv4/5, ARM7/ARM9,
3982 and ARM9TDMI commands.
3984 @deffn Command {arm920t cache_info}
3985 Print information about the caches found. This allows to see whether your target
3986 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3989 @deffn Command {arm920t cp15} regnum [value]
3990 Display cp15 register @var{regnum};
3991 else if a @var{value} is provided, that value is written to that register.
3994 @deffn Command {arm920t cp15i} opcode [value [address]]
3995 Interpreted access using cp15 @var{opcode}.
3996 If no @var{value} is provided, the result is displayed.
3997 Else if that value is written using the specified @var{address},
3998 or using zero if no other address is not provided.
4001 @deffn Command {arm920t mdw_phys} addr [count]
4002 @deffnx Command {arm920t mdh_phys} addr [count]
4003 @deffnx Command {arm920t mdb_phys} addr [count]
4004 Display contents of physical address @var{addr}, as
4005 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4006 or 8-bit bytes (@command{mdb_phys}).
4007 If @var{count} is specified, displays that many units.
4010 @deffn Command {arm920t mww_phys} addr word
4011 @deffnx Command {arm920t mwh_phys} addr halfword
4012 @deffnx Command {arm920t mwb_phys} addr byte
4013 Writes the specified @var{word} (32 bits),
4014 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4015 at the specified physical address @var{addr}.
4018 @deffn Command {arm920t read_cache} filename
4019 Dump the content of ICache and DCache to a file named @file{filename}.
4022 @deffn Command {arm920t read_mmu} filename
4023 Dump the content of the ITLB and DTLB to a file named @file{filename}.
4026 @deffn Command {arm920t virt2phys} @var{va}
4027 Translate a virtual address @var{va} to a physical address
4028 and display the result.
4031 @subsection ARM926EJ-S specific commands
4032 @cindex ARM926EJ-S specific commands
4034 These commands are available to ARM926EJ-S based CPUs,
4035 which are implementations of the ARMv5TEJ architecture
4036 based on the ARM9EJ-S integer core.
4037 They are available in addition to the ARMv4/5, ARM7/ARM9,
4038 and ARM9TDMI commands.
4040 @deffn Command {arm926ejs cache_info}
4041 Print information about the caches found.
4044 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
4045 Accesses cp15 register @var{regnum} using
4046 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
4047 If a @var{value} is provided, that value is written to that register.
4048 Else that register is read and displayed.
4051 @deffn Command {arm926ejs mdw_phys} addr [count]
4052 @deffnx Command {arm926ejs mdh_phys} addr [count]
4053 @deffnx Command {arm926ejs mdb_phys} addr [count]
4054 Display contents of physical address @var{addr}, as
4055 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4056 or 8-bit bytes (@command{mdb_phys}).
4057 If @var{count} is specified, displays that many units.
4060 @deffn Command {arm926ejs mww_phys} addr word
4061 @deffnx Command {arm926ejs mwh_phys} addr halfword
4062 @deffnx Command {arm926ejs mwb_phys} addr byte
4063 Writes the specified @var{word} (32 bits),
4064 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4065 at the specified physical address @var{addr}.
4068 @deffn Command {arm926ejs virt2phys} @var{va}
4069 Translate a virtual address @var{va} to a physical address
4070 and display the result.
4073 @subsection ARM966E specific commands
4074 @cindex ARM966E specific commands
4076 These commands are available to ARM966 based CPUs,
4077 which are implementations of the ARMv5TE architecture.
4078 They are available in addition to the ARMv4/5, ARM7/ARM9,
4079 and ARM9TDMI commands.
4081 @deffn Command {arm966e cp15} regnum [value]
4082 Display cp15 register @var{regnum};
4083 else if a @var{value} is provided, that value is written to that register.
4086 @subsection XScale specific commands
4087 @cindex XScale specific commands
4089 These commands are available to XScale based CPUs,
4090 which are implementations of the ARMv5TE architecture.
4092 @deffn Command {xscale analyze_trace}
4093 Displays the contents of the trace buffer.
4096 @deffn Command {xscale cache_clean_address} address
4097 Changes the address used when cleaning the data cache.
4100 @deffn Command {xscale cache_info}
4101 Displays information about the CPU caches.
4104 @deffn Command {xscale cp15} regnum [value]
4105 Display cp15 register @var{regnum};
4106 else if a @var{value} is provided, that value is written to that register.
4109 @deffn Command {xscale debug_handler} target address
4110 Changes the address used for the specified target's debug handler.
4113 @deffn Command {xscale dcache} (enable|disable)
4114 Enables or disable the CPU's data cache.
4117 @deffn Command {xscale dump_trace} filename
4118 Dumps the raw contents of the trace buffer to @file{filename}.
4121 @deffn Command {xscale icache} (enable|disable)
4122 Enables or disable the CPU's instruction cache.
4125 @deffn Command {xscale mmu} (enable|disable)
4126 Enables or disable the CPU's memory management unit.
4129 @deffn Command {xscale trace_buffer} (enable|disable) [fill [n] | wrap]
4130 Enables or disables the trace buffer,
4131 and controls how it is emptied.
4134 @deffn Command {xscale trace_image} filename [offset [type]]
4135 Opens a trace image from @file{filename}, optionally rebasing
4136 its segment addresses by @var{offset}.
4137 The image @var{type} may be one of
4138 @option{bin} (binary), @option{ihex} (Intel hex),
4139 @option{elf} (ELF file), @option{s19} (Motorola s19),
4140 @option{mem}, or @option{builder}.
4143 @deffn Command {xscale vector_catch} mask
4144 Provide a bitmask showing the vectors to catch.
4147 @section ARMv6 Architecture
4149 @subsection ARM11 specific commands
4150 @cindex ARM11 specific commands
4152 @deffn Command {arm11 mcr} p1 p2 p3 p4 p5
4153 Read coprocessor register
4156 @deffn Command {arm11 memwrite burst} [value]
4157 Displays the value of the memwrite burst-enable flag,
4158 which is enabled by default.
4159 If @var{value} is defined, first assigns that.
4162 @deffn Command {arm11 memwrite error_fatal} [value]
4163 Displays the value of the memwrite error_fatal flag,
4164 which is enabled by default.
4165 If @var{value} is defined, first assigns that.
4168 @deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
4169 Write coprocessor register
4172 @deffn Command {arm11 no_increment} [value]
4173 Displays the value of the flag controlling whether
4174 some read or write operations increment the pointer
4175 (the default behavior) or not (acting like a FIFO).
4176 If @var{value} is defined, first assigns that.
4179 @deffn Command {arm11 step_irq_enable} [value]
4180 Displays the value of the flag controlling whether
4181 IRQs are enabled during single stepping;
4182 they is disabled by default.
4183 If @var{value} is defined, first assigns that.
4186 @section ARMv7 Architecture
4188 @subsection ARMv7 Debug Access Port (DAP) specific commands
4189 @cindex ARMv7 Debug Access Port (DAP) specific commands
4190 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
4191 included on cortex-m3 and cortex-a8 systems.
4192 They are available in addition to other core-specific commands that may be available.
4194 @deffn Command {dap info} [num]
4195 Displays dap info for ap [num], default currently selected AP.
4198 @deffn Command {dap apsel} [num]
4199 Select a different AP [num] (default 0).
4202 @deffn Command {dap apid} [num]
4203 Displays id reg from AP [num], default currently selected AP.
4206 @deffn Command {dap baseaddr} [num]
4207 Displays debug base address from AP [num], default currently selected AP.
4210 @deffn Command {dap memaccess} [value]
4211 Displays the number of extra tck for mem-ap memory bus access [0-255].
4212 If value is defined, first assigns that.
4215 @subsection Cortex-M3 specific commands
4216 @cindex Cortex-M3 specific commands
4218 @deffn Command {cortex_m3 maskisr} (on|off)
4219 Control masking (disabling) interrupts during target step/resume.
4222 @section Target DCC Requests
4223 @cindex Linux-ARM DCC support
4226 OpenOCD can handle certain target requests; currently debugmsgs
4227 @command{target_request debugmsgs}
4228 are only supported for arm7_9 and cortex_m3.
4230 See libdcc in the contrib dir for more details.
4231 Linux-ARM kernels have a ``Kernel low-level debugging
4232 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
4233 depends on CONFIG_DEBUG_LL) which uses this mechanism to
4234 deliver messages before a serial console can be activated.
4236 @deffn Command {target_request debugmsgs} [enable|disable|charmsg]
4237 Displays current handling of target DCC message requests.
4238 These messages may be sent to the debugger while the target is running.
4239 The optional @option{enable} and @option{charmsg} parameters
4240 both enable the messages, while @option{disable} disables them.
4241 With @option{charmsg} the DCC words each contain one character,
4242 as used by Linux with CONFIG_DEBUG_ICEDCC;
4243 otherwise the libdcc format is used.
4247 @chapter JTAG Commands
4248 @cindex JTAG Commands
4249 Most general purpose JTAG commands have been presented earlier.
4250 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Creation}.)
4251 Lower level JTAG commands, as presented here,
4252 may be needed to work with targets which require special
4253 attention during operations such as reset or initialization.
4255 To use these commands you will need to understand some
4256 of the basics of JTAG, including:
4259 @item A JTAG scan chain consists of a sequence of individual TAP
4260 devices such as a CPUs.
4261 @item Control operations involve moving each TAP through the same
4262 standard state machine (in parallel)
4263 using their shared TMS and clock signals.
4264 @item Data transfer involves shifting data through the chain of
4265 instruction or data registers of each TAP, writing new register values
4266 while the reading previous ones.
4267 @item Data register sizes are a function of the instruction active in
4268 a given TAP, while instruction register sizes are fixed for each TAP.
4269 All TAPs support a BYPASS instruction with a single bit data register.
4270 @item The way OpenOCD differentiates between TAP devices is by
4271 shifting different instructions into (and out of) their instruction
4275 @section Low Level JTAG Commands
4277 These commands are used by developers who need to access
4278 JTAG instruction or data registers, possibly controlling
4279 the order of TAP state transitions.
4280 If you're not debugging OpenOCD internals, or bringing up a
4281 new JTAG adapter or a new type of TAP device (like a CPU or
4282 JTAG router), you probably won't need to use these commands.
4284 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
4285 Loads the data register of @var{tap} with a series of bit fields
4286 that specify the entire register.
4287 Each field is @var{numbits} bits long with
4288 a numeric @var{value} (hexadecimal encouraged).
4289 The return value holds the original value of each
4292 For example, a 38 bit number might be specified as one
4293 field of 32 bits then one of 6 bits.
4294 @emph{For portability, never pass fields which are more
4295 than 32 bits long. Many OpenOCD implementations do not
4296 support 64-bit (or larger) integer values.}
4298 All TAPs other than @var{tap} must be in BYPASS mode.
4299 The single bit in their data registers does not matter.
4301 When @var{tap_state} is specified, the JTAG state machine is left
4303 For example @sc{drpause} might be specified, so that more
4304 instructions can be issued before re-entering the @sc{run/idle} state.
4305 If the end state is not specified, the @sc{run/idle} state is entered.
4308 OpenOCD does not record information about data register lengths,
4309 so @emph{it is important that you get the bit field lengths right}.
4310 Remember that different JTAG instructions refer to different
4311 data registers, which may have different lengths.
4312 Moreover, those lengths may not be fixed;
4313 the SCAN_N instruction can change the length of
4314 the register accessed by the INTEST instruction
4315 (by connecting a different scan chain).
4319 @deffn Command {flush_count}
4320 Returns the number of times the JTAG queue has been flushed.
4321 This may be used for performance tuning.
4323 For example, flushing a queue over USB involves a
4324 minimum latency, often several milliseconds, which does
4325 not change with the amount of data which is written.
4326 You may be able to identify performance problems by finding
4327 tasks which waste bandwidth by flushing small transfers too often,
4328 instead of batching them into larger operations.
4331 @deffn Command {endstate} tap_state
4332 Flush any pending JTAG operations,
4333 and return with all TAPs in @var{tap_state}.
4334 This state should be a stable state such as @sc{reset},
4336 @sc{drpause}, or @sc{irpause}.
4339 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
4340 For each @var{tap} listed, loads the instruction register
4341 with its associated numeric @var{instruction}.
4342 (The number of bits in that instruction may be displayed
4343 using the @command{scan_chain} command.)
4344 For other TAPs, a BYPASS instruction is loaded.
4346 When @var{tap_state} is specified, the JTAG state machine is left
4348 For example @sc{irpause} might be specified, so the data register
4349 can be loaded before re-entering the @sc{run/idle} state.
4350 If the end state is not specified, the @sc{run/idle} state is entered.
4353 OpenOCD currently supports only a single field for instruction
4354 register values, unlike data register values.
4355 For TAPs where the instruction register length is more than 32 bits,
4356 portable scripts currently must issue only BYPASS instructions.
4360 @deffn Command {jtag_reset} trst srst
4361 Set values of reset signals.
4362 The @var{trst} and @var{srst} parameter values may be
4363 @option{0}, indicating that reset is inactive (pulled or driven high),
4364 or @option{1}, indicating it is active (pulled or driven low).
4365 The @command{reset_config} command should already have been used
4366 to configure how the board and JTAG adapter treat these two
4367 signals, and to say if either signal is even present.
4368 @xref{Reset Configuration}.
4371 @deffn Command {runtest} @var{num_cycles}
4372 Move to the @sc{run/idle} state, and execute at least
4373 @var{num_cycles} of the JTAG clock (TCK).
4374 Instructions often need some time
4375 to execute before they take effect.
4378 @deffn Command {scan_chain}
4379 Displays the TAPs in the scan chain configuration,
4381 The set of TAPs listed by this command is fixed by
4382 exiting the OpenOCD configuration stage,
4383 but systems with a JTAG router can
4384 enable or disable TAPs dynamically.
4385 In addition to the enable/disable status, the contents of
4386 each TAP's instruction register can also change.
4389 @c tms_sequence (short|long)
4390 @c ... temporary, debug-only, probably gone before 0.2 ships
4392 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
4393 Verify values captured during @sc{ircapture} and returned
4394 during IR scans. Default is enabled, but this can be
4395 overridden by @command{verify_jtag}.
4398 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
4399 Enables verification of DR and IR scans, to help detect
4400 programming errors. For IR scans, @command{verify_ircapture}
4401 must also be enabled.
4405 @section TAP state names
4406 @cindex TAP state names
4408 The @var{tap_state} names used by OpenOCD in the @command{drscan},
4409 @command{endstate}, and @command{irscan} commands are:
4430 Note that only six of those states are fully ``stable'' in the
4431 face of TMS fixed and a free-running JTAG clock; for all the
4432 others, the next TCK transition changes to a new state.
4435 @item @sc{reset} is probably most useful with @command{endstate},
4436 but entering it frequently has side effects.
4437 (This is the only stable state with TMS high.)
4438 @item From @sc{drshift} and @sc{irshift}, clock transitions will
4439 produce side effects by changing register contents. The values
4440 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
4441 may not be as expected.
4442 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
4443 choices after @command{drscan} or @command{irscan} commands,
4444 since they are free of side effects.
4450 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
4451 be used to access files on PCs (either the developer's PC or some other PC).
4453 The way this works on the ZY1000 is to prefix a filename by
4454 "/tftp/ip/" and append the TFTP path on the TFTP
4455 server (tftpd). For example,
4458 load_image /tftp/10.0.0.96/c:\temp\abc.elf
4461 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
4462 if the file was hosted on the embedded host.
4464 In order to achieve decent performance, you must choose a TFTP server
4465 that supports a packet size bigger than the default packet size (512 bytes). There
4466 are numerous TFTP servers out there (free and commercial) and you will have to do
4467 a bit of googling to find something that fits your requirements.
4469 @node Sample Scripts
4470 @chapter Sample Scripts
4473 This page shows how to use the Target Library.
4475 The configuration script can be divided into the following sections:
4477 @item Daemon configuration
4479 @item JTAG scan chain
4480 @item Target configuration
4481 @item Flash configuration
4484 Detailed information about each section can be found at OpenOCD configuration.
4486 @section AT91R40008 example
4487 @cindex AT91R40008 example
4488 To start OpenOCD with a target script for the AT91R40008 CPU and reset
4489 the CPU upon startup of the OpenOCD daemon.
4491 openocd -f interface/parport.cfg -f target/at91r40008.cfg \
4492 -c "init" -c "reset"
4496 @node GDB and OpenOCD
4497 @chapter GDB and OpenOCD
4499 OpenOCD complies with the remote gdbserver protocol, and as such can be used
4500 to debug remote targets.
4502 @anchor{Connecting to GDB}
4503 @section Connecting to GDB
4504 @cindex Connecting to GDB
4505 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
4506 instance GDB 6.3 has a known bug that produces bogus memory access
4507 errors, which has since been fixed: look up 1836 in
4508 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
4510 OpenOCD can communicate with GDB in two ways:
4514 A socket (TCP/IP) connection is typically started as follows:
4516 target remote localhost:3333
4518 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
4520 A pipe connection is typically started as follows:
4522 target remote | openocd --pipe
4524 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
4525 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
4529 To list the available OpenOCD commands type @command{monitor help} on the
4532 OpenOCD supports the gdb @option{qSupported} packet, this enables information
4533 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
4534 packet size and the device's memory map.
4536 Previous versions of OpenOCD required the following GDB options to increase
4537 the packet size and speed up GDB communication:
4539 set remote memory-write-packet-size 1024
4540 set remote memory-write-packet-size fixed
4541 set remote memory-read-packet-size 1024
4542 set remote memory-read-packet-size fixed
4544 This is now handled in the @option{qSupported} PacketSize and should not be required.
4546 @section Programming using GDB
4547 @cindex Programming using GDB
4549 By default the target memory map is sent to GDB. This can be disabled by
4550 the following OpenOCD configuration option:
4552 gdb_memory_map disable
4554 For this to function correctly a valid flash configuration must also be set
4555 in OpenOCD. For faster performance you should also configure a valid
4558 Informing GDB of the memory map of the target will enable GDB to protect any
4559 flash areas of the target and use hardware breakpoints by default. This means
4560 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
4561 using a memory map. @xref{gdb_breakpoint_override}.
4563 To view the configured memory map in GDB, use the GDB command @option{info mem}
4564 All other unassigned addresses within GDB are treated as RAM.
4566 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
4567 This can be changed to the old behaviour by using the following GDB command
4569 set mem inaccessible-by-default off
4572 If @command{gdb_flash_program enable} is also used, GDB will be able to
4573 program any flash memory using the vFlash interface.
4575 GDB will look at the target memory map when a load command is given, if any
4576 areas to be programmed lie within the target flash area the vFlash packets
4579 If the target needs configuring before GDB programming, an event
4580 script can be executed:
4582 $_TARGETNAME configure -event EVENTNAME BODY
4585 To verify any flash programming the GDB command @option{compare-sections}
4588 @node Tcl Scripting API
4589 @chapter Tcl Scripting API
4590 @cindex Tcl Scripting API
4594 The commands are stateless. E.g. the telnet command line has a concept
4595 of currently active target, the Tcl API proc's take this sort of state
4596 information as an argument to each proc.
4598 There are three main types of return values: single value, name value
4599 pair list and lists.
4601 Name value pair. The proc 'foo' below returns a name/value pair
4607 > set foo(you) Oyvind
4608 > set foo(mouse) Micky
4609 > set foo(duck) Donald
4617 me Duane you Oyvind mouse Micky duck Donald
4619 Thus, to get the names of the associative array is easy:
4621 foreach { name value } [set foo] {
4622 puts "Name: $name, Value: $value"
4626 Lists returned must be relatively small. Otherwise a range
4627 should be passed in to the proc in question.
4629 @section Internal low-level Commands
4631 By low-level, the intent is a human would not directly use these commands.
4633 Low-level commands are (should be) prefixed with "ocd_", e.g.
4634 @command{ocd_flash_banks}
4635 is the low level API upon which @command{flash banks} is implemented.
4638 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
4640 Read memory and return as a Tcl array for script processing
4641 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
4643 Convert a Tcl array to memory locations and write the values
4644 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
4646 Return information about the flash banks
4649 OpenOCD commands can consist of two words, e.g. "flash banks". The
4650 startup.tcl "unknown" proc will translate this into a Tcl proc
4651 called "flash_banks".
4653 @section OpenOCD specific Global Variables
4657 Real Tcl has ::tcl_platform(), and platform::identify, and many other
4658 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
4659 holds one of the following values:
4662 @item @b{winxx} Built using Microsoft Visual Studio
4663 @item @b{linux} Linux is the underlying operating sytem
4664 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
4665 @item @b{cygwin} Running under Cygwin
4666 @item @b{mingw32} Running under MingW32
4667 @item @b{other} Unknown, none of the above.
4670 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
4673 We should add support for a variable like Tcl variable
4674 @code{tcl_platform(platform)}, it should be called
4675 @code{jim_platform} (because it
4676 is jim, not real tcl).
4680 @chapter Deprecated/Removed Commands
4681 @cindex Deprecated/Removed Commands
4682 Certain OpenOCD commands have been deprecated or
4683 removed during the various revisions.
4685 Upgrade your scripts as soon as possible.
4686 These descriptions for old commands may be removed
4687 a year after the command itself was removed.
4688 This means that in January 2010 this chapter may
4689 become much shorter.
4692 @item @b{arm7_9 fast_writes}
4693 @cindex arm7_9 fast_writes
4694 @*Use @command{arm7_9 fast_memory_access} instead.
4695 @xref{arm7_9 fast_memory_access}.
4696 @item @b{arm7_9 force_hw_bkpts}
4697 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
4698 for flash if the GDB memory map has been set up(default when flash is declared in
4699 target configuration). @xref{gdb_breakpoint_override}.
4700 @item @b{arm7_9 sw_bkpts}
4701 @*On by default. @xref{gdb_breakpoint_override}.
4702 @item @b{daemon_startup}
4703 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
4704 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
4705 and @option{target cortex_m3 little reset_halt 0}.
4706 @item @b{dump_binary}
4707 @*use @option{dump_image} command with same args. @xref{dump_image}.
4708 @item @b{flash erase}
4709 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
4710 @item @b{flash write}
4711 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
4712 @item @b{flash write_binary}
4713 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
4714 @item @b{flash auto_erase}
4715 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
4717 @item @b{jtag_device}
4718 @*use the @command{jtag newtap} command, converting from positional syntax
4719 to named prefixes, and naming the TAP.
4721 Note that if you try to use the old command, a message will tell you the
4722 right new command to use; and that the fourth parameter in the old syntax
4723 was never actually used.
4725 OLD: jtag_device 8 0x01 0xe3 0xfe
4726 NEW: jtag newtap CHIPNAME TAPNAME \
4727 -irlen 8 -ircapture 0x01 -irmask 0xe3
4730 @item @b{jtag_speed} value
4731 @*@xref{JTAG Speed}.
4732 Usually, a value of zero means maximum
4733 speed. The actual effect of this option depends on the JTAG interface used.
4735 @item wiggler: maximum speed / @var{number}
4736 @item ft2232: 6MHz / (@var{number}+1)
4737 @item amt jtagaccel: 8 / 2**@var{number}
4738 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
4739 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
4740 @comment end speed list.
4743 @item @b{load_binary}
4744 @*use @option{load_image} command with same args. @xref{load_image}.
4745 @item @b{run_and_halt_time}
4746 @*This command has been removed for simpler reset behaviour, it can be simulated with the
4753 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
4754 @*use the create subcommand of @option{target}.
4755 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
4756 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
4757 @item @b{working_area}
4758 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
4766 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
4768 @cindex adaptive clocking
4771 In digital circuit design it is often refered to as ``clock
4772 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
4773 operating at some speed, your target is operating at another. The two
4774 clocks are not synchronised, they are ``asynchronous''
4776 In order for the two to work together they must be synchronised. Otherwise
4777 the two systems will get out of sync with each other and nothing will
4778 work. There are 2 basic options:
4781 Use a special circuit.
4783 One clock must be some multiple slower than the other.
4786 @b{Does this really matter?} For some chips and some situations, this
4787 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
4788 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
4789 program/enable the oscillators and eventually the main clock. It is in
4790 those critical times you must slow the JTAG clock to sometimes 1 to
4793 Imagine debugging a 500MHz ARM926 hand held battery powered device
4794 that ``deep sleeps'' at 32kHz between every keystroke. It can be
4797 @b{Solution #1 - A special circuit}
4799 In order to make use of this, your JTAG dongle must support the RTCK
4800 feature. Not all dongles support this - keep reading!
4802 The RTCK signal often found in some ARM chips is used to help with
4803 this problem. ARM has a good description of the problem described at
4804 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
4805 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
4806 work? / how does adaptive clocking work?''.
4808 The nice thing about adaptive clocking is that ``battery powered hand
4809 held device example'' - the adaptiveness works perfectly all the
4810 time. One can set a break point or halt the system in the deep power
4811 down code, slow step out until the system speeds up.
4813 @b{Solution #2 - Always works - but may be slower}
4815 Often this is a perfectly acceptable solution.
4817 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
4818 the target clock speed. But what that ``magic division'' is varies
4819 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
4820 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
4821 1/12 the clock speed.
4823 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
4825 You can still debug the 'low power' situations - you just need to
4826 manually adjust the clock speed at every step. While painful and
4827 tedious, it is not always practical.
4829 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
4830 have a special debug mode in your application that does a ``high power
4831 sleep''. If you are careful - 98% of your problems can be debugged
4834 To set the JTAG frequency use the command:
4842 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
4844 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
4845 around Windows filenames.
4858 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
4860 Make sure you have Cygwin installed, or at least a version of OpenOCD that
4861 claims to come with all the necessary DLLs. When using Cygwin, try launching
4862 OpenOCD from the Cygwin shell.
4864 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
4865 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
4866 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
4868 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
4869 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
4870 software breakpoints consume one of the two available hardware breakpoints.
4872 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
4874 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
4875 clock at the time you're programming the flash. If you've specified the crystal's
4876 frequency, make sure the PLL is disabled. If you've specified the full core speed
4877 (e.g. 60MHz), make sure the PLL is enabled.
4879 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
4880 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
4881 out while waiting for end of scan, rtck was disabled".
4883 Make sure your PC's parallel port operates in EPP mode. You might have to try several
4884 settings in your PC BIOS (ECP, EPP, and different versions of those).
4886 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
4887 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
4888 memory read caused data abort".
4890 The errors are non-fatal, and are the result of GDB trying to trace stack frames
4891 beyond the last valid frame. It might be possible to prevent this by setting up
4892 a proper "initial" stack frame, if you happen to know what exactly has to
4893 be done, feel free to add this here.
4895 @b{Simple:} In your startup code - push 8 registers of zeros onto the
4896 stack before calling main(). What GDB is doing is ``climbing'' the run
4897 time stack by reading various values on the stack using the standard
4898 call frame for the target. GDB keeps going - until one of 2 things
4899 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
4900 stackframes have been processed. By pushing zeros on the stack, GDB
4903 @b{Debugging Interrupt Service Routines} - In your ISR before you call
4904 your C code, do the same - artifically push some zeros onto the stack,
4905 remember to pop them off when the ISR is done.
4907 @b{Also note:} If you have a multi-threaded operating system, they
4908 often do not @b{in the intrest of saving memory} waste these few
4912 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
4913 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
4915 This warning doesn't indicate any serious problem, as long as you don't want to
4916 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
4917 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
4918 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
4919 independently. With this setup, it's not possible to halt the core right out of
4920 reset, everything else should work fine.
4922 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
4923 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
4924 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
4925 quit with an error message. Is there a stability issue with OpenOCD?
4927 No, this is not a stability issue concerning OpenOCD. Most users have solved
4928 this issue by simply using a self-powered USB hub, which they connect their
4929 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
4930 supply stable enough for the Amontec JTAGkey to be operated.
4932 @b{Laptops running on battery have this problem too...}
4934 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
4935 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
4936 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
4937 What does that mean and what might be the reason for this?
4939 First of all, the reason might be the USB power supply. Try using a self-powered
4940 hub instead of a direct connection to your computer. Secondly, the error code 4
4941 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
4942 chip ran into some sort of error - this points us to a USB problem.
4944 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
4945 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
4946 What does that mean and what might be the reason for this?
4948 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
4949 has closed the connection to OpenOCD. This might be a GDB issue.
4951 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
4952 are described, there is a parameter for specifying the clock frequency
4953 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
4954 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
4955 specified in kilohertz. However, I do have a quartz crystal of a
4956 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
4957 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
4960 No. The clock frequency specified here must be given as an integral number.
4961 However, this clock frequency is used by the In-Application-Programming (IAP)
4962 routines of the LPC2000 family only, which seems to be very tolerant concerning
4963 the given clock frequency, so a slight difference between the specified clock
4964 frequency and the actual clock frequency will not cause any trouble.
4966 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
4968 Well, yes and no. Commands can be given in arbitrary order, yet the
4969 devices listed for the JTAG scan chain must be given in the right
4970 order (jtag newdevice), with the device closest to the TDO-Pin being
4971 listed first. In general, whenever objects of the same type exist
4972 which require an index number, then these objects must be given in the
4973 right order (jtag newtap, targets and flash banks - a target
4974 references a jtag newtap and a flash bank references a target).
4976 You can use the ``scan_chain'' command to verify and display the tap order.
4978 Also, some commands can't execute until after @command{init} has been
4979 processed. Such commands include @command{nand probe} and everything
4980 else that needs to write to controller registers, perhaps for setting
4981 up DRAM and loading it with code.
4983 @item @b{JTAG Tap Order} JTAG tap order - command order
4985 Many newer devices have multiple JTAG taps. For example: ST
4986 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
4987 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
4988 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
4989 connected to the boundary scan tap, which then connects to the
4990 Cortex-M3 tap, which then connects to the TDO pin.
4992 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
4993 (2) The boundary scan tap. If your board includes an additional JTAG
4994 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
4995 place it before or after the STM32 chip in the chain. For example:
4998 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
4999 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
5000 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
5001 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
5002 @item Xilinx TDO Pin -> OpenOCD TDO (input)
5005 The ``jtag device'' commands would thus be in the order shown below. Note:
5008 @item jtag newtap Xilinx tap -irlen ...
5009 @item jtag newtap stm32 cpu -irlen ...
5010 @item jtag newtap stm32 bs -irlen ...
5011 @item # Create the debug target and say where it is
5012 @item target create stm32.cpu -chain-position stm32.cpu ...
5016 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
5017 log file, I can see these error messages: Error: arm7_9_common.c:561
5018 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
5024 @node Tcl Crash Course
5025 @chapter Tcl Crash Course
5028 Not everyone knows Tcl - this is not intended to be a replacement for
5029 learning Tcl, the intent of this chapter is to give you some idea of
5030 how the Tcl scripts work.
5032 This chapter is written with two audiences in mind. (1) OpenOCD users
5033 who need to understand a bit more of how JIM-Tcl works so they can do
5034 something useful, and (2) those that want to add a new command to
5037 @section Tcl Rule #1
5038 There is a famous joke, it goes like this:
5040 @item Rule #1: The wife is always correct
5041 @item Rule #2: If you think otherwise, See Rule #1
5044 The Tcl equal is this:
5047 @item Rule #1: Everything is a string
5048 @item Rule #2: If you think otherwise, See Rule #1
5051 As in the famous joke, the consequences of Rule #1 are profound. Once
5052 you understand Rule #1, you will understand Tcl.
5054 @section Tcl Rule #1b
5055 There is a second pair of rules.
5057 @item Rule #1: Control flow does not exist. Only commands
5058 @* For example: the classic FOR loop or IF statement is not a control
5059 flow item, they are commands, there is no such thing as control flow
5061 @item Rule #2: If you think otherwise, See Rule #1
5062 @* Actually what happens is this: There are commands that by
5063 convention, act like control flow key words in other languages. One of
5064 those commands is the word ``for'', another command is ``if''.
5067 @section Per Rule #1 - All Results are strings
5068 Every Tcl command results in a string. The word ``result'' is used
5069 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
5070 Everything is a string}
5072 @section Tcl Quoting Operators
5073 In life of a Tcl script, there are two important periods of time, the
5074 difference is subtle.
5077 @item Evaluation Time
5080 The two key items here are how ``quoted things'' work in Tcl. Tcl has
5081 three primary quoting constructs, the [square-brackets] the
5082 @{curly-braces@} and ``double-quotes''
5084 By now you should know $VARIABLES always start with a $DOLLAR
5085 sign. BTW: To set a variable, you actually use the command ``set'', as
5086 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
5087 = 1'' statement, but without the equal sign.
5090 @item @b{[square-brackets]}
5091 @* @b{[square-brackets]} are command substitutions. It operates much
5092 like Unix Shell `back-ticks`. The result of a [square-bracket]
5093 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
5094 string}. These two statements are roughly identical:
5098 echo "The Date is: $X"
5101 puts "The Date is: $X"
5103 @item @b{``double-quoted-things''}
5104 @* @b{``double-quoted-things''} are just simply quoted
5105 text. $VARIABLES and [square-brackets] are expanded in place - the
5106 result however is exactly 1 string. @i{Remember Rule #1 - Everything
5110 puts "It is now \"[date]\", $x is in 1 hour"
5112 @item @b{@{Curly-Braces@}}
5113 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
5114 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
5115 'single-quote' operators in BASH shell scripts, with the added
5116 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
5117 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
5118 28/nov/2008, Jim/OpenOCD does not have a date command.
5121 @section Consequences of Rule 1/2/3/4
5123 The consequences of Rule 1 are profound.
5125 @subsection Tokenisation & Execution.
5127 Of course, whitespace, blank lines and #comment lines are handled in
5130 As a script is parsed, each (multi) line in the script file is
5131 tokenised and according to the quoting rules. After tokenisation, that
5132 line is immedatly executed.
5134 Multi line statements end with one or more ``still-open''
5135 @{curly-braces@} which - eventually - closes a few lines later.
5137 @subsection Command Execution
5139 Remember earlier: There are no ``control flow''
5140 statements in Tcl. Instead there are COMMANDS that simply act like
5141 control flow operators.
5143 Commands are executed like this:
5146 @item Parse the next line into (argc) and (argv[]).
5147 @item Look up (argv[0]) in a table and call its function.
5148 @item Repeat until End Of File.
5151 It sort of works like this:
5154 ReadAndParse( &argc, &argv );
5156 cmdPtr = LookupCommand( argv[0] );
5158 (*cmdPtr->Execute)( argc, argv );
5162 When the command ``proc'' is parsed (which creates a procedure
5163 function) it gets 3 parameters on the command line. @b{1} the name of
5164 the proc (function), @b{2} the list of parameters, and @b{3} the body
5165 of the function. Not the choice of words: LIST and BODY. The PROC
5166 command stores these items in a table somewhere so it can be found by
5169 @subsection The FOR command
5171 The most interesting command to look at is the FOR command. In Tcl,
5172 the FOR command is normally implemented in C. Remember, FOR is a
5173 command just like any other command.
5175 When the ascii text containing the FOR command is parsed, the parser
5176 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
5180 @item The ascii text 'for'
5181 @item The start text
5182 @item The test expression
5187 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
5188 Remember @i{Rule #1 - Everything is a string.} The key point is this:
5189 Often many of those parameters are in @{curly-braces@} - thus the
5190 variables inside are not expanded or replaced until later.
5192 Remember that every Tcl command looks like the classic ``main( argc,
5193 argv )'' function in C. In JimTCL - they actually look like this:
5197 MyCommand( Jim_Interp *interp,
5199 Jim_Obj * const *argvs );
5202 Real Tcl is nearly identical. Although the newer versions have
5203 introduced a byte-code parser and intepreter, but at the core, it
5204 still operates in the same basic way.
5206 @subsection FOR command implementation
5208 To understand Tcl it is perhaps most helpful to see the FOR
5209 command. Remember, it is a COMMAND not a control flow structure.
5211 In Tcl there are two underlying C helper functions.
5213 Remember Rule #1 - You are a string.
5215 The @b{first} helper parses and executes commands found in an ascii
5216 string. Commands can be seperated by semicolons, or newlines. While
5217 parsing, variables are expanded via the quoting rules.
5219 The @b{second} helper evaluates an ascii string as a numerical
5220 expression and returns a value.
5222 Here is an example of how the @b{FOR} command could be
5223 implemented. The pseudo code below does not show error handling.
5225 void Execute_AsciiString( void *interp, const char *string );
5227 int Evaluate_AsciiExpression( void *interp, const char *string );
5230 MyForCommand( void *interp,
5235 SetResult( interp, "WRONG number of parameters");
5239 // argv[0] = the ascii string just like C
5241 // Execute the start statement.
5242 Execute_AsciiString( interp, argv[1] );
5246 i = Evaluate_AsciiExpression(interp, argv[2]);
5251 Execute_AsciiString( interp, argv[3] );
5253 // Execute the LOOP part
5254 Execute_AsciiString( interp, argv[4] );
5258 SetResult( interp, "" );
5263 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
5264 in the same basic way.
5266 @section OpenOCD Tcl Usage
5268 @subsection source and find commands
5269 @b{Where:} In many configuration files
5270 @* Example: @b{ source [find FILENAME] }
5271 @*Remember the parsing rules
5273 @item The FIND command is in square brackets.
5274 @* The FIND command is executed with the parameter FILENAME. It should
5275 find the full path to the named file. The RESULT is a string, which is
5276 substituted on the orginal command line.
5277 @item The command source is executed with the resulting filename.
5278 @* SOURCE reads a file and executes as a script.
5280 @subsection format command
5281 @b{Where:} Generally occurs in numerous places.
5282 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
5288 puts [format "The answer: %d" [expr $x * $y]]
5291 @item The SET command creates 2 variables, X and Y.
5292 @item The double [nested] EXPR command performs math
5293 @* The EXPR command produces numerical result as a string.
5295 @item The format command is executed, producing a single string
5296 @* Refer to Rule #1.
5297 @item The PUTS command outputs the text.
5299 @subsection Body or Inlined Text
5300 @b{Where:} Various TARGET scripts.
5303 proc someproc @{@} @{
5304 ... multiple lines of stuff ...
5306 $_TARGETNAME configure -event FOO someproc
5307 #2 Good - no variables
5308 $_TARGETNAME confgure -event foo "this ; that;"
5309 #3 Good Curly Braces
5310 $_TARGETNAME configure -event FOO @{
5313 #4 DANGER DANGER DANGER
5314 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
5317 @item The $_TARGETNAME is an OpenOCD variable convention.
5318 @*@b{$_TARGETNAME} represents the last target created, the value changes
5319 each time a new target is created. Remember the parsing rules. When
5320 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
5321 the name of the target which happens to be a TARGET (object)
5323 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
5324 @*There are 4 examples:
5326 @item The TCLBODY is a simple string that happens to be a proc name
5327 @item The TCLBODY is several simple commands seperated by semicolons
5328 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
5329 @item The TCLBODY is a string with variables that get expanded.
5332 In the end, when the target event FOO occurs the TCLBODY is
5333 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
5334 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
5336 Remember the parsing rules. In case #3, @{curly-braces@} mean the
5337 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
5338 and the text is evaluated. In case #4, they are replaced before the
5339 ``Target Object Command'' is executed. This occurs at the same time
5340 $_TARGETNAME is replaced. In case #4 the date will never
5341 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
5342 Jim/OpenOCD does not have a date command@}
5344 @subsection Global Variables
5345 @b{Where:} You might discover this when writing your own procs @* In
5346 simple terms: Inside a PROC, if you need to access a global variable
5347 you must say so. See also ``upvar''. Example:
5349 proc myproc @{ @} @{
5350 set y 0 #Local variable Y
5351 global x #Global variable X
5352 puts [format "X=%d, Y=%d" $x $y]
5355 @section Other Tcl Hacks
5356 @b{Dynamic variable creation}
5358 # Dynamically create a bunch of variables.
5359 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
5361 set vn [format "BIT%d" $x]
5365 set $vn [expr (1 << $x)]
5368 @b{Dynamic proc/command creation}
5370 # One "X" function - 5 uart functions.
5371 foreach who @{A B C D E@}
5372 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
5376 @node Target Library
5377 @chapter Target Library
5378 @cindex Target Library
5380 OpenOCD comes with a target configuration script library. These scripts can be
5381 used as-is or serve as a starting point.
5383 The target library is published together with the OpenOCD executable and
5384 the path to the target library is in the OpenOCD script search path.
5385 Similarly there are example scripts for configuring the JTAG interface.
5387 The command line below uses the example parport configuration script
5388 that ship with OpenOCD, then configures the str710.cfg target and
5389 finally issues the init and reset commands. The communication speed
5390 is set to 10kHz for reset and 8MHz for post reset.
5393 openocd -f interface/parport.cfg -f target/str710.cfg \
5394 -c "init" -c "reset"
5397 To list the target scripts available:
5400 $ ls /usr/local/lib/openocd/target
5402 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
5403 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
5404 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
5405 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
5410 @node OpenOCD Concept Index
5411 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
5412 @comment case issue with ``Index.html'' and ``index.html''
5413 @comment Occurs when creating ``--html --no-split'' output
5414 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
5415 @unnumbered OpenOCD Concept Index
5419 @node Command and Driver Index
5420 @unnumbered Command and Driver Index