1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}@*
15 Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
17 Permission is granted to copy, distribute and/or modify this document
18 under the terms of the GNU Free Documentation License, Version 1.2 or
19 any later version published by the Free Software Foundation; with no
20 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
21 Texts. A copy of the license is included in the section entitled ``GNU
22 Free Documentation License''.
27 @title Open On-Chip Debugger (OpenOCD)
28 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
29 @subtitle @value{UPDATED}
31 @vskip 0pt plus 1filll
37 @node Top, About, , (dir)
40 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
41 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
46 * About:: About OpenOCD.
47 * Developers:: OpenOCD developers
48 * Building:: Building OpenOCD
49 * Running:: Running OpenOCD
50 * Configuration:: OpenOCD Configuration.
51 * Target library:: Target library
52 * Commands:: OpenOCD Commands
53 * Sample Scripts:: Sample Target Scripts
54 * GDB and OpenOCD:: Using GDB and OpenOCD
55 * TCL and OpenOCD:: Using TCL and OpenOCD
56 * TCL scripting API:: Tcl scripting API
57 * Upgrading:: Deprecated/Removed Commands
58 * FAQ:: Frequently Asked Questions
59 * License:: GNU Free Documentation License
67 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
68 and boundary-scan testing for embedded target devices. The targets are interfaced
69 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
70 connection types in the future.
72 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
73 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
74 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
75 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
77 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
78 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
79 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
85 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
86 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
87 Others interested in improving the state of free and open debug and testing technology
88 are welcome to participate.
90 Other developers have contributed support for additional targets and flashes as well
91 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
93 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
97 @cindex building OpenOCD
99 If you are interested in getting actual work done rather than building
100 OpenOCD, then check if your interface supplier provides binaries for
101 you. Chances are that that binary is from some SVN version that is more
102 stable than SVN trunk where bleeding edge development takes place.
105 You can download the current SVN version with SVN client of your choice from the
106 following repositories:
108 (@uref{svn://svn.berlios.de/openocd/trunk})
112 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
114 Using the SVN command line client, you can use the following command to fetch the
115 latest version (make sure there is no (non-svn) directory called "openocd" in the
119 svn checkout svn://svn.berlios.de/openocd/trunk openocd
122 Building OpenOCD requires a recent version of the GNU autotools.
123 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
124 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
125 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
126 paths, resulting in obscure dependency errors (This is an observation I've gathered
127 from the logs of one user - correct me if I'm wrong).
129 You further need the appropriate driver files, if you want to build support for
130 a FTDI FT2232 based interface:
132 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
133 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
134 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
135 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
138 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
139 see contrib/libftdi for more details.
141 In general, the D2XX driver provides superior performance (several times as fast),
142 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
143 a kernel module, only a user space library.
145 To build OpenOCD (on both Linux and Cygwin), use the following commands:
149 Bootstrap generates the configure script, and prepares building on your system.
153 Configure generates the Makefiles used to build OpenOCD.
157 Make builds OpenOCD, and places the final executable in ./src/.
159 The configure script takes several options, specifying which JTAG interfaces
164 @option{--enable-parport}
166 @option{--enable-parport_ppdev}
168 @option{--enable-parport_giveio}
170 @option{--enable-amtjtagaccel}
172 @option{--enable-ft2232_ftd2xx}
173 @footnote{Using the latest D2XX drivers from FTDI and following their installation
174 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
177 @option{--enable-ft2232_libftdi}
179 @option{--with-ftd2xx=/path/to/d2xx/}
181 @option{--enable-gw16012}
183 @option{--enable-usbprog}
185 @option{--enable-presto_libftdi}
187 @option{--enable-presto_ftd2xx}
189 @option{--enable-jlink}
192 If you want to access the parallel port using the PPDEV interface you have to specify
193 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
194 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
195 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
197 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
198 absolute path containing no spaces.
200 Linux users should copy the various parts of the D2XX package to the appropriate
201 locations, i.e. /usr/include, /usr/lib.
203 Miscellaneous configure options
207 @option{--enable-gccwarnings} - enable extra gcc warnings during build
212 @cindex running OpenOCD
214 @cindex --debug_level
217 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
218 Run with @option{--help} or @option{-h} to view the available command line switches.
220 It reads its configuration by default from the file openocd.cfg located in the current
221 working directory. This may be overwritten with the @option{-f <configfile>} command line
222 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
223 are executed in order.
225 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
227 To enable debug output (when reporting problems or working on OpenOCD itself), use
228 the @option{-d} command line switch. This sets the @option{debug_level} to "3", outputting
229 the most information, including debug messages. The default setting is "2", outputting
230 only informational messages, warnings and errors. You can also change this setting
231 from within a telnet or gdb session using @option{debug_level <n>} @xref{debug_level}.
233 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
235 Search paths for config/script files can be added to OpenOCD by using
236 the @option{-s <search>} switch. The current directory and the OpenOCD target library
237 is in the search path by default.
239 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
240 with the target. In general, it is possible for the JTAG controller to be unresponsive until
241 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
244 @chapter Configuration
245 @cindex configuration
246 OpenOCD runs as a daemon, and reads it current configuration
247 by default from the file openocd.cfg in the current directory. A different configuration
248 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
250 The configuration file is used to specify on which ports the daemon listens for new
251 connections, the JTAG interface used to connect to the target, the layout of the JTAG
252 chain, the targets that should be debugged, and connected flashes.
254 @section Daemon configuration
258 @*This command terminates the configuration stage and enters the normal
259 command mode. This can be useful to add commands to the startup scripts and commands
260 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
261 add "init" and "reset" at the end of the config script or at the end of the
262 OpenOCD command line using the @option{-c} command line switch.
264 @item @b{telnet_port} <@var{number}>
266 @*Port on which to listen for incoming telnet connections
267 @item @b{tcl_port} <@var{number}>
269 @*Port on which to listen for incoming TCL syntax. This port is intended as
270 a simplified RPC connection that can be used by clients to issue commands
271 and get the output from the TCL engine.
272 @item @b{gdb_port} <@var{number}>
274 @*First port on which to listen for incoming GDB connections. The GDB port for the
275 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
276 @item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
277 @cindex gdb_breakpoint_override
278 @*Force breakpoint type for gdb 'break' commands.
279 The raison d'etre for this option is to support GDB GUI's without
280 a hard/soft breakpoint concept where the default OpenOCD and
281 GDB behaviour is not sufficient. Note that GDB will use hardware
282 breakpoints if the memory map has been set up for flash regions.
284 This option replaces older arm7_9 target commands that addressed
286 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
288 @*Configures what OpenOCD will do when gdb detaches from the daeman.
289 Default behaviour is <@var{resume}>
290 @item @b{gdb_memory_map} <@var{enable|disable}>
291 @cindex gdb_memory_map
292 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
293 requested. gdb will then know when to set hardware breakpoints, and program flash
294 using the gdb load command. @option{gdb_flash_program enable} (@xref{gdb_flash_program})
295 will also need enabling for flash programming to work.
296 Default behaviour is <@var{enable}>
297 @item @b{gdb_flash_program} <@var{enable|disable}>
298 @cindex gdb_flash_program
299 @anchor{gdb_flash_program}
300 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
301 vFlash packet is received.
302 Default behaviour is <@var{enable}>
305 @section JTAG interface configuration
308 @item @b{interface} <@var{name}>
310 @*Use the interface driver <@var{name}> to connect to the target. Currently supported
314 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
317 @item @b{amt_jtagaccel}
318 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
323 FTDI FT2232 based devices using either the open-source libftdi or the binary only
324 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
325 platform. The libftdi uses libusb, and should be portable to all systems that provide
330 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
334 ASIX PRESTO USB JTAG programmer.
338 usbprog is a freely programmable USB adapter.
342 Gateworks GW16012 JTAG programmer.
346 Segger jlink usb adapter
351 @item @b{jtag_speed} <@var{reset speed}>
353 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
354 speed. The actual effect of this option depends on the JTAG interface used.
356 The speed used during reset can be adjusted using setting jtag_speed during
357 pre_reset and post_reset events.
360 @item wiggler: maximum speed / @var{number}
361 @item ft2232: 6MHz / (@var{number}+1)
362 @item amt jtagaccel: 8 / 2**@var{number}
363 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
366 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
367 especially true for synthesized cores (-S).
369 @item @b{jtag_khz} <@var{reset speed kHz}>
371 @*Same as jtag_speed, except that the speed is specified in maximum kHz. If
372 the device can not support the rate asked for, or can not translate from
373 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
374 is not supported, then an error is reported.
376 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
378 @*The configuration of the reset signals available on the JTAG interface AND the target.
379 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
380 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
381 @option{srst_only} or @option{trst_and_srst}.
383 [@var{combination}] is an optional value specifying broken reset signal implementations.
384 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
385 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
386 that the system is reset together with the test logic (only hypothetical, I haven't
387 seen hardware with such a bug, and can be worked around).
388 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
389 The default behaviour if no option given is @option{separate}.
391 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
392 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
393 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
394 (default) and @option{srst_push_pull} for the system reset. These values only affect
395 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
397 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
399 @*Describes the devices that form the JTAG daisy chain, with the first device being
400 the one closest to TDO. The parameters are the length of the instruction register
401 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
402 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
403 The IDCODE instruction will in future be used to query devices for their JTAG
404 identification code. This line is the same for all ARM7 and ARM9 devices.
405 Other devices, like CPLDs, require different parameters. An example configuration
406 line for a Xilinx XC9500 CPLD would look like this:
408 jtag_device 8 0x01 0x0e3 0xfe
410 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
411 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
412 The IDCODE instruction is 0xfe.
414 @item @b{jtag_nsrst_delay} <@var{ms}>
415 @cindex jtag_nsrst_delay
416 @*How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
417 starting new JTAG operations.
418 @item @b{jtag_ntrst_delay} <@var{ms}>
419 @cindex jtag_ntrst_delay
420 @*Same @b{jtag_nsrst_delay}, but for nTRST
422 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
423 or on-chip features) keep a reset line asserted for some time after the external reset
427 @section parport options
430 @item @b{parport_port} <@var{number}>
432 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
433 the @file{/dev/parport} device
435 When using PPDEV to access the parallel port, use the number of the parallel port:
436 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
437 you may encounter a problem.
438 @item @b{parport_cable} <@var{name}>
439 @cindex parport_cable
440 @*The layout of the parallel port cable used to connect to the target.
441 Currently supported cables are
445 The original Wiggler layout, also supported by several clones, such
446 as the Olimex ARM-JTAG
449 Same as original wiggler except an led is fitted on D5.
450 @item @b{wiggler_ntrst_inverted}
451 @cindex wiggler_ntrst_inverted
452 Same as original wiggler except TRST is inverted.
453 @item @b{old_amt_wiggler}
454 @cindex old_amt_wiggler
455 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
456 version available from the website uses the original Wiggler layout ('@var{wiggler}')
459 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
460 program the Chameleon itself, not a connected target.
463 The Xilinx Parallel cable III.
466 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
467 This is also the layout used by the HollyGates design
468 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
471 The ST Parallel cable.
474 Same as original wiggler except SRST and TRST connections reversed and
475 TRST is also inverted.
478 Altium Universal JTAG cable.
480 @item @b{parport_write_on_exit} <@var{on|off}>
481 @cindex parport_write_on_exit
482 @*This will configure the parallel driver to write a known value to the parallel
483 interface on exiting OpenOCD
486 @section amt_jtagaccel options
488 @item @b{parport_port} <@var{number}>
490 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
491 @file{/dev/parport} device
493 @section ft2232 options
496 @item @b{ft2232_device_desc} <@var{description}>
497 @cindex ft2232_device_desc
498 @*The USB device description of the FTDI FT2232 device. If not specified, the FTDI
499 default value is used. This setting is only valid if compiled with FTD2XX support.
500 @item @b{ft2232_layout} <@var{name}>
501 @cindex ft2232_layout
502 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
503 signals. Valid layouts are
506 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
508 Amontec JTAGkey and JTAGkey-tiny
511 @item @b{olimex-jtag}
514 American Microsystems M5960
515 @item @b{evb_lm3s811}
516 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
517 SRST signals on external connector
521 Hitex STM32 Performance Stick
523 Tin Can Tools Flyswatter
524 @item @b{turtelizer2}
525 egnite Software turtelizer2
530 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
531 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
532 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
534 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
536 @item @b{ft2232_latency} <@var{ms}>
537 @*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
538 ft2232_read() fails to return the expected number of bytes. This can be caused by
539 USB communication delays and has proved hard to reproduce and debug. Setting the
540 FT2232 latency timer to a larger value increases delays for short USB packages but it
541 also reduces the risk of timeouts before receiving the expected number of bytes.
542 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
545 @section ep93xx options
546 @cindex ep93xx options
547 Currently, there are no options available for the ep93xx interface.
550 @section Target configuration
553 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
556 @*Defines a target that should be debugged. Currently supported types are:
571 If you want to use a target board that is not on this list, see Adding a new
574 Endianess may be @option{little} or @option{big}.
576 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
577 @cindex target_script
578 @*Event is one of the following:
579 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
580 @option{pre_resume} or @option{gdb_program_config}.
581 @option{post_reset} and @option{reset} will produce the same results.
583 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
584 <@var{backup}|@var{nobackup}>
586 @*Specifies a working area for the debugger to use. This may be used to speed-up
587 downloads to target memory and flash operations, or to perform otherwise unavailable
588 operations (some coprocessor operations on ARM7/9 systems, for example). The last
589 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
590 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
593 @subsection arm7tdmi options
594 @cindex arm7tdmi options
595 target arm7tdmi <@var{endianess}> <@var{jtag#}>
596 @*The arm7tdmi target definition requires at least one additional argument, specifying
597 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
598 The optional [@var{variant}] parameter has been removed in recent versions.
599 The correct feature set is determined at runtime.
601 @subsection arm720t options
602 @cindex arm720t options
603 ARM720t options are similar to ARM7TDMI options.
605 @subsection arm9tdmi options
606 @cindex arm9tdmi options
607 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
608 @option{arm920t}, @option{arm922t} and @option{arm940t}.
609 This enables the hardware single-stepping support found on these cores.
611 @subsection arm920t options
612 @cindex arm920t options
613 ARM920t options are similar to ARM9TDMI options.
615 @subsection arm966e options
616 @cindex arm966e options
617 ARM966e options are similar to ARM9TDMI options.
619 @subsection cortex_m3 options
620 @cindex cortex_m3 options
621 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
622 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
623 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
624 be detected and the normal reset behaviour used.
626 @subsection xscale options
627 @cindex xscale options
628 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
629 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
631 @section Flash configuration
632 @cindex Flash configuration
635 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
636 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
638 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
639 and <@var{bus_width}> bytes using the selected flash <driver>.
642 @subsection lpc2000 options
643 @cindex lpc2000 options
645 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
646 <@var{clock}> [@var{calc_checksum}]
647 @*LPC flashes don't require the chip and bus width to be specified. Additional
648 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
649 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
650 of the target this flash belongs to (first is 0), the frequency at which the core
651 is currently running (in kHz - must be an integral number), and the optional keyword
652 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
655 @subsection cfi options
658 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
659 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
660 @*CFI flashes require the number of the target they're connected to as an additional
661 argument. The CFI driver makes use of a working area (specified for the target)
662 to significantly speed up operation.
664 @var{chip_width} and @var{bus_width} are specified in bytes.
666 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
670 @subsection at91sam7 options
671 @cindex at91sam7 options
673 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
674 @*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
675 reading the chip-id and type.
677 @subsection str7 options
680 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
681 @*variant can be either STR71x, STR73x or STR75x.
683 @subsection str9 options
686 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
687 @*The str9 needs the flash controller to be configured prior to Flash programming, eg.
689 str9x flash_config 0 4 2 0 0x80000
691 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
693 @subsection str9 options (str9xpec driver)
695 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
696 @*Before using the flash commands the turbo mode will need enabling using str9xpec
697 @option{enable_turbo} <@var{num>.}
699 Only use this driver for locking/unlocking the device or configuring the option bytes.
700 Use the standard str9 driver for programming.
702 @subsection stellaris (LM3Sxxx) options
703 @cindex stellaris (LM3Sxxx) options
705 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
706 @*stellaris flash plugin only require the @var{target#}.
708 @subsection stm32x options
709 @cindex stm32x options
711 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
712 @*stm32x flash plugin only require the @var{target#}.
714 @subsection aduc702x options
715 @cindex aduc702x options
717 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
718 @*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
721 @chapter Target library
722 @cindex Target library
724 OpenOCD comes with a target configuration script library. These scripts can be
725 used as-is or serve as a starting point.
727 The target library is published together with the openocd executable and
728 the path to the target library is in the OpenOCD script search path.
729 Similarly there are example scripts for configuring the JTAG interface.
731 The command line below uses the example parport configuration scripts
732 that ship with OpenOCD, then configures the str710.cfg target and
733 finally issues the init and reset command. The communication speed
734 is set to 10kHz for reset and 8MHz for post reset.
738 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
742 To list the target scripts available:
745 $ ls /usr/local/lib/openocd/target
747 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
748 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
749 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
750 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
758 OpenOCD allows user interaction through a GDB server (default: port 3333),
759 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
760 is available from both the telnet interface and a GDB session. To issue commands to the
761 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
762 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
765 The TCL interface is used as a simplified RPC mechanism that feeds all the
766 input into the TCL interpreter and returns the output from the evaluation of
772 @item @b{sleep} <@var{msec}>
774 @*Wait for n milliseconds before resuming. Useful in connection with script files
775 (@var{script} command and @var{target_script} configuration).
779 @*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
781 @item @b{debug_level} [@var{n}]
784 @*Display or adjust debug level to n<0-3>
786 @item @b{fast} [@var{enable|disable}]
788 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
789 downloads and fast memory access will work if the JTAG interface isn't too fast and
790 the core doesn't run at a too low frequency. Note that this option only changes the default
791 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
794 The target specific "dangerous" optimisation tweaking options may come and go
795 as more robust and user friendly ways are found to ensure maximum throughput
796 and robustness with a minimum of configuration.
798 Typically the "fast enable" is specified first on the command line:
801 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
804 @item @b{log_output} <@var{file}>
806 @*Redirect logging to <file> (default: stderr)
808 @item @b{script} <@var{file}>
810 @*Execute commands from <file>
814 @subsection Target state handling
816 @item @b{poll} [@option{on}|@option{off}]
818 @*Poll the target for its current state. If the target is in debug mode, architecture
819 specific information about the current state is printed. An optional parameter
820 allows continuous polling to be enabled and disabled.
822 @item @b{halt} [@option{ms}]
824 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
825 Default [@option{ms}] is 5 seconds if no arg given.
826 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
827 will stop OpenOCD from waiting.
829 @item @b{wait_halt} [@option{ms}]
831 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
832 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
835 @item @b{resume} [@var{address}]
837 @*Resume the target at its current code position, or at an optional address.
838 OpenOCD will wait 5 seconds for the target to resume.
840 @item @b{step} [@var{address}]
842 @*Single-step the target at its current code position, or at an optional address.
844 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
846 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
848 With no arguments a "reset run" is executed
852 @*Let the target run.
855 @*Immediately halt the target (works only with certain configurations).
858 @*Immediately halt the target, and execute the reset script (works only with certain
863 @subsection Memory access commands
864 These commands allow accesses of a specific size to the memory system:
866 @item @b{mdw} <@var{addr}> [@var{count}]
868 @*display memory words
869 @item @b{mdh} <@var{addr}> [@var{count}]
871 @*display memory half-words
872 @item @b{mdb} <@var{addr}> [@var{count}]
874 @*display memory bytes
875 @item @b{mww} <@var{addr}> <@var{value}>
878 @item @b{mwh} <@var{addr}> <@var{value}>
880 @*write memory half-word
881 @item @b{mwb} <@var{addr}> <@var{value}>
885 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
887 @*Load image <@var{file}> to target memory at <@var{address}>
888 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
890 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
891 (binary) <@var{file}>.
892 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
894 @*Verify <@var{file}> against target memory starting at <@var{address}>.
895 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
898 @subsection Flash commands
899 @cindex Flash commands
901 @item @b{flash banks}
903 @*List configured flash banks
904 @item @b{flash info} <@var{num}>
906 @*Print info about flash bank <@option{num}>
907 @item @b{flash probe} <@var{num}>
909 @*Identify the flash, or validate the parameters of the configured flash. Operation
910 depends on the flash type.
911 @item @b{flash erase_check} <@var{num}>
912 @cindex flash erase_check
913 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
914 updates the erase state information displayed by @option{flash info}. That means you have
915 to issue an @option{erase_check} command after erasing or programming the device to get
917 @item @b{flash protect_check} <@var{num}>
918 @cindex flash protect_check
919 @*Check protection state of sectors in flash bank <num>.
920 @option{flash erase_sector} using the same syntax.
921 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
922 @cindex flash erase_sector
923 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
924 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
925 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
927 @item @b{flash erase_address} <@var{address}> <@var{length}>
928 @cindex flash erase_address
929 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
930 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
931 @cindex flash write_bank
932 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
933 <@option{offset}> bytes from the beginning of the bank.
934 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
935 @cindex flash write_image
936 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
937 [@var{offset}] can be specified and the file [@var{type}] can be specified
938 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
939 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
940 if the @option{erase} parameter is given.
941 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
942 @cindex flash protect
943 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
944 <@var{last}> of @option{flash bank} <@var{num}>.
948 @section Target Specific Commands
949 @cindex Target Specific Commands
951 @subsection AT91SAM7 specific commands
952 @cindex AT91SAM7 specific commands
953 The flash configuration is deduced from the chip identification register. The flash
954 controller handles erases automatically on a page (128/265 byte) basis so erase is
955 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
956 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
957 that can be erased separatly. Only an EraseAll command is supported by the controller
958 for each flash plane and this is called with
960 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
961 @*bulk erase flash planes first_plane to last_plane.
962 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
963 @cindex at91sam7 gpnvm
964 @*set or clear a gpnvm bit for the processor
967 @subsection STR9 specific commands
968 @cindex STR9 specific commands
969 These are flash specific commands when using the str9xpec driver.
971 @item @b{str9xpec enable_turbo} <@var{num}>
972 @cindex str9xpec enable_turbo
973 @*enable turbo mode, simply this will remove the str9 from the chain and talk
974 directly to the embedded flash controller.
975 @item @b{str9xpec disable_turbo} <@var{num}>
976 @cindex str9xpec disable_turbo
977 @*restore the str9 into jtag chain.
978 @item @b{str9xpec lock} <@var{num}>
979 @cindex str9xpec lock
980 @*lock str9 device. The str9 will only respond to an unlock command that will
982 @item @b{str9xpec unlock} <@var{num}>
983 @cindex str9xpec unlock
984 @*unlock str9 device.
985 @item @b{str9xpec options_read} <@var{num}>
986 @cindex str9xpec options_read
987 @*read str9 option bytes.
988 @item @b{str9xpec options_write} <@var{num}>
989 @cindex str9xpec options_write
990 @*write str9 option bytes.
993 @subsection STR9 configuration
994 @cindex STR9 configuration
996 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
997 <@var{BBADR}> <@var{NBBADR}>
998 @cindex str9x flash_config
999 @*Configure str9 flash controller.
1001 eg. str9x flash_config 0 4 2 0 0x80000
1003 BBSR - Boot Bank Size register
1004 NBBSR - Non Boot Bank Size register
1005 BBADR - Boot Bank Start Address register
1006 NBBADR - Boot Bank Start Address register
1010 @subsection STR9 option byte configuration
1011 @cindex STR9 option byte configuration
1013 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
1014 @cindex str9xpec options_cmap
1015 @*configure str9 boot bank.
1016 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1017 @cindex str9xpec options_lvdthd
1018 @*configure str9 lvd threshold.
1019 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1020 @cindex str9xpec options_lvdsel
1021 @*configure str9 lvd source.
1022 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1023 @cindex str9xpec options_lvdwarn
1024 @*configure str9 lvd reset warning source.
1027 @subsection STM32x specific commands
1028 @cindex STM32x specific commands
1030 These are flash specific commands when using the stm32x driver.
1032 @item @b{stm32x lock} <@var{num}>
1034 @*lock stm32 device.
1035 @item @b{stm32x unlock} <@var{num}>
1036 @cindex stm32x unlock
1037 @*unlock stm32 device.
1038 @item @b{stm32x options_read} <@var{num}>
1039 @cindex stm32x options_read
1040 @*read stm32 option bytes.
1041 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1042 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1043 @cindex stm32x options_write
1044 @*write stm32 option bytes.
1045 @item @b{stm32x mass_erase} <@var{num}>
1046 @cindex stm32x mass_erase
1047 @*mass erase flash memory.
1050 @subsection Stellaris specific commands
1051 @cindex Stellaris specific commands
1053 These are flash specific commands when using the Stellaris driver.
1055 @item @b{stellaris mass_erase} <@var{num}>
1056 @cindex stellaris mass_erase
1057 @*mass erase flash memory.
1061 @section Architecture Specific Commands
1062 @cindex Architecture Specific Commands
1064 @subsection ARMV4/5 specific commands
1065 @cindex ARMV4/5 specific commands
1067 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1068 or Intel XScale (XScale isn't supported yet).
1070 @item @b{armv4_5 reg}
1072 @*Display a list of all banked core registers, fetching the current value from every
1073 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1075 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1076 @cindex armv4_5 core_mode
1077 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1078 The target is resumed in the currently set @option{core_mode}.
1081 @subsection ARM7/9 specific commands
1082 @cindex ARM7/9 specific commands
1084 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1085 ARM920t or ARM926EJ-S.
1087 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1088 @cindex arm7_9 dbgrq
1089 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
1090 safe for all but ARM7TDMI--S cores (like Philips LPC).
1091 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1092 @cindex arm7_9 fast_memory_access
1093 @*Allow OpenOCD to read and write memory without checking completion of
1094 the operation. This provides a huge speed increase, especially with USB JTAG
1095 cables (FT2232), but might be unsafe if used with targets running at a very low
1096 speed, like the 32kHz startup clock of an AT91RM9200.
1097 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1098 @cindex arm7_9 dcc_downloads
1099 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1100 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1101 unsafe, especially with targets running at a very low speed. This command was introduced
1102 with OpenOCD rev. 60.
1105 @subsection ARM720T specific commands
1106 @cindex ARM720T specific commands
1109 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1110 @cindex arm720t cp15
1111 @*display/modify cp15 register <@option{num}> [@option{value}].
1112 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1113 @cindex arm720t md<bhw>_phys
1114 @*Display memory at physical address addr.
1115 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1116 @cindex arm720t mw<bhw>_phys
1117 @*Write memory at physical address addr.
1118 @item @b{arm720t virt2phys} <@var{va}>
1119 @cindex arm720t virt2phys
1120 @*Translate a virtual address to a physical address.
1123 @subsection ARM9TDMI specific commands
1124 @cindex ARM9TDMI specific commands
1127 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1128 @cindex arm9tdmi vector_catch
1129 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1130 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1131 @option{irq} @option{fiq}.
1133 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1136 @subsection ARM966E specific commands
1137 @cindex ARM966E specific commands
1140 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1141 @cindex arm966e cp15
1142 @*display/modify cp15 register <@option{num}> [@option{value}].
1145 @subsection ARM920T specific commands
1146 @cindex ARM920T specific commands
1149 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1150 @cindex arm920t cp15
1151 @*display/modify cp15 register <@option{num}> [@option{value}].
1152 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1153 @cindex arm920t cp15i
1154 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1155 @item @b{arm920t cache_info}
1156 @cindex arm920t cache_info
1157 @*Print information about the caches found. This allows you to see if your target
1158 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1159 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1160 @cindex arm920t md<bhw>_phys
1161 @*Display memory at physical address addr.
1162 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1163 @cindex arm920t mw<bhw>_phys
1164 @*Write memory at physical address addr.
1165 @item @b{arm920t read_cache} <@var{filename}>
1166 @cindex arm920t read_cache
1167 @*Dump the content of ICache and DCache to a file.
1168 @item @b{arm920t read_mmu} <@var{filename}>
1169 @cindex arm920t read_mmu
1170 @*Dump the content of the ITLB and DTLB to a file.
1171 @item @b{arm920t virt2phys} <@var{va}>
1172 @cindex arm920t virt2phys
1173 @*Translate a virtual address to a physical address.
1176 @subsection ARM926EJS specific commands
1177 @cindex ARM926EJS specific commands
1180 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1181 @cindex arm926ejs cp15
1182 @*display/modify cp15 register <@option{num}> [@option{value}].
1183 @item @b{arm926ejs cache_info}
1184 @cindex arm926ejs cache_info
1185 @*Print information about the caches found.
1186 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1187 @cindex arm926ejs md<bhw>_phys
1188 @*Display memory at physical address addr.
1189 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1190 @cindex arm926ejs mw<bhw>_phys
1191 @*Write memory at physical address addr.
1192 @item @b{arm926ejs virt2phys} <@var{va}>
1193 @cindex arm926ejs virt2phys
1194 @*Translate a virtual address to a physical address.
1198 @section Debug commands
1199 @cindex Debug commands
1200 The following commands give direct access to the core, and are most likely
1201 only useful while debugging OpenOCD.
1203 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1204 @cindex arm7_9 write_xpsr
1205 @*Immediately write either the current program status register (CPSR) or the saved
1206 program status register (SPSR), without changing the register cache (as displayed
1207 by the @option{reg} and @option{armv4_5 reg} commands).
1208 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1209 <@var{0=cpsr},@var{1=spsr}>
1210 @cindex arm7_9 write_xpsr_im8
1211 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1212 operation (similar to @option{write_xpsr}).
1213 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1214 @cindex arm7_9 write_core_reg
1215 @*Write a core register, without changing the register cache (as displayed by the
1216 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1217 encoding of the [M4:M0] bits of the PSR.
1221 @section JTAG commands
1222 @cindex JTAG commands
1224 @item @b{scan_chain}
1226 @*Print current scan chain configuration.
1227 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1229 @*Toggle reset lines.
1230 @item @b{endstate} <@var{tap_state}>
1232 @*Finish JTAG operations in <@var{tap_state}>.
1233 @item @b{runtest} <@var{num_cycles}>
1235 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
1236 @item @b{statemove} [@var{tap_state}]
1238 @*Move to current endstate or [@var{tap_state}]
1239 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1241 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1242 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1244 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1245 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1246 @cindex verify_ircapture
1247 @*Verify value captured during Capture-IR. Default is enabled.
1248 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1250 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1251 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1253 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1257 @section Target Requests
1258 @cindex Target Requests
1259 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1260 See libdcc in the contrib dir for more details.
1262 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1263 @cindex target_request debugmsgs
1264 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1267 @node Sample Scripts
1268 @chapter Sample Scripts
1271 This page shows how to use the target library.
1273 The configuration script can be divided in the following section:
1275 @item daemon configuration
1277 @item jtag scan chain
1278 @item target configuration
1279 @item flash configuration
1282 Detailed information about each section can be found at OpenOCD configuration.
1284 @section AT91R40008 example
1285 @cindex AT91R40008 example
1286 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1287 the CPU upon startup of the OpenOCD daemon.
1289 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1293 @node GDB and OpenOCD
1294 @chapter GDB and OpenOCD
1295 @cindex GDB and OpenOCD
1296 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1297 to debug remote targets.
1299 @section Connecting to gdb
1300 @cindex Connecting to gdb
1301 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a
1302 known bug where it produces bogus memory access errors, which has since
1303 been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb
1306 A connection is typically started as follows:
1308 target remote localhost:3333
1310 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1312 To see a list of available OpenOCD commands type @option{monitor help} on the
1315 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1316 to be sent by the gdb server (openocd) to gdb. Typical information includes
1317 packet size and device memory map.
1319 Previous versions of OpenOCD required the following gdb options to increase
1320 the packet size and speed up gdb communication.
1322 set remote memory-write-packet-size 1024
1323 set remote memory-write-packet-size fixed
1324 set remote memory-read-packet-size 1024
1325 set remote memory-read-packet-size fixed
1327 This is now handled in the @option{qSupported} PacketSize.
1329 @section Programming using gdb
1330 @cindex Programming using gdb
1332 By default the target memory map is sent to gdb, this can be disabled by
1333 the following OpenOCD config option:
1335 gdb_memory_map disable
1337 For this to function correctly a valid flash config must also be configured
1338 in OpenOCD. For faster performance you should also configure a valid
1341 Informing gdb of the memory map of the target will enable gdb to protect any
1342 flash area of the target and use hardware breakpoints by default. This means
1343 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
1346 To view the configured memory map in gdb, use the gdb command @option{info mem}
1347 All other unasigned addresses within gdb are treated as RAM.
1349 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1350 this can be changed to the old behaviour by using the following gdb command.
1352 set mem inaccessible-by-default off
1355 If @option{gdb_flash_program enable} is also used, gdb will be able to
1356 program any flash memory using the vFlash interface.
1358 gdb will look at the target memory map when a load command is given, if any
1359 areas to be programmed lie within the target flash area the vFlash packets
1362 If the target needs configuring before gdb programming, a script can be executed.
1364 target_script 0 gdb_program_config config.script
1367 To verify any flash programming the gdb command @option{compare-sections}
1370 @node TCL and OpenOCD
1371 @chapter TCL and OpenOCD
1372 @cindex TCL and OpenOCD
1373 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1376 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1378 The command and file interfaces are fairly straightforward, while the network
1379 port is geared toward intergration with external clients. A small example
1380 of an external TCL script that can connect to openocd is shown below.
1383 # Simple tcl client to connect to openocd
1384 puts "Use empty line to exit"
1385 set fo [socket 127.0.0.1 6666]
1386 puts -nonewline stdout "> "
1388 while {[gets stdin line] >= 0} {
1389 if {$line eq {}} break
1394 puts -nonewline stdout "> "
1400 This script can easily be modified to front various GUIs or be a sub
1401 component of a larger framework for control and interaction.
1404 @node TCL scripting API
1405 @chapter TCL scripting API
1406 @cindex TCL scripting API
1409 The commands are stateless. E.g. the telnet command line has a concept
1410 of currently active target, the Tcl API proc's take this sort of state
1411 information as an argument to each proc.
1413 There are three main types of return values: single value, name value
1414 pair list and lists.
1416 Name value pair. The proc 'foo' below returns a name/value pair
1422 > set foo(you) Oyvind
1423 > set foo(mouse) Micky
1424 > set foo(duck) Donald
1432 me Duane you Oyvind mouse Micky duck Donald
1434 Thus, to get the names of the associative array is easy:
1436 foreach { name value } [set foo] {
1437 puts "Name: $name, Value: $value"
1441 Lists returned must be relatively small. Otherwise a range
1442 should be passed in to the proc in question.
1444 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
1445 is the low level API upon which "flash banks" is implemented.
1447 OpenOCD commands can consist of two words, e.g. "flash banks". The
1448 startup.tcl "unknown" proc will translate this into a tcl proc
1449 called "flash_banks".
1453 @chapter Deprecated/Removed Commands
1454 @cindex Deprecated/Removed Commands
1455 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1458 @item @b{load_binary}
1460 @*use @option{load_image} command with same args
1463 @*@option{target} no longer take the reset_init, reset_run, run_and_halt, run_and_init. The @option{reset} command
1464 always does a @option{reset run} when passed no arguments.
1465 @item @b{dump_binary}
1467 @*use @option{dump_image} command with same args
1468 @item @b{flash erase}
1470 @*use @option{flash erase_sector} command with same args
1471 @item @b{flash write}
1473 @*use @option{flash write_bank} command with same args
1474 @item @b{flash write_binary}
1475 @cindex flash write_binary
1476 @*use @option{flash write_bank} command with same args
1477 @item @b{arm7_9 fast_writes}
1478 @cindex arm7_9 fast_writes
1479 @*use @option{arm7_9 fast_memory_access} command with same args
1480 @item @b{flash auto_erase}
1481 @cindex flash auto_erase
1482 @*use @option{flash write_image} command passing @option{erase} as the first parameter.
1483 @item @b{daemon_startup}
1484 @cindex daemon_startup
1485 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
1486 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
1487 and @option{target cortex_m3 little reset_halt 0}.
1488 @item @b{arm7_9 sw_bkpts}
1489 @cindex arm7_9 sw_bkpts
1490 @*On by default. See also @option{gdb_breakpoint_override}.
1491 @item @b{arm7_9 force_hw_bkpts}
1492 @cindex arm7_9 force_hw_bkpts
1493 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
1494 for flash if the gdb memory map has been set up(default when flash is declared in
1495 target configuration).
1496 @item @b{run_and_halt_time}
1497 @cindex run_and_halt_time
1498 @*This command has been removed for simpler reset behaviour, it can be simulated with the
1511 @item OpenOCD complains about a missing cygwin1.dll.
1513 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1514 claims to come with all the necessary dlls. When using Cygwin, try launching
1515 OpenOCD from the Cygwin shell.
1517 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1518 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1519 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1521 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1522 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1523 software breakpoints consume one of the two available hardware breakpoints.
1525 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1526 and works sometimes fine.
1528 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1529 clock at the time you're programming the flash. If you've specified the crystal's
1530 frequency, make sure the PLL is disabled, if you've specified the full core speed
1531 (e.g. 60MHz), make sure the PLL is enabled.
1533 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1534 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1535 out while waiting for end of scan, rtck was disabled".
1537 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1538 settings in your PC BIOS (ECP, EPP, and different versions of those).
1540 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1541 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1542 memory read caused data abort".
1544 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1545 beyond the last valid frame. It might be possible to prevent this by setting up
1546 a proper "initial" stack frame, if you happen to know what exactly has to
1547 be done, feel free to add this here.
1549 @item I get the following message in the OpenOCD console (or log file):
1550 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1552 This warning doesn't indicate any serious problem, as long as you don't want to
1553 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1554 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1555 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1556 independently. With this setup, it's not possible to halt the core right out of
1557 reset, everything else should work fine.
1559 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1560 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1561 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1562 quit with an error message. Is there a stability issue with OpenOCD?
1564 No, this is not a stability issue concerning OpenOCD. Most users have solved
1565 this issue by simply using a self-powered USB hub, which they connect their
1566 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1567 supply stable enough for the Amontec JTAGkey to be operated.
1569 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1570 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1571 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1572 What does that mean and what might be the reason for this?
1574 First of all, the reason might be the USB power supply. Try using a self-powered
1575 hub instead of a direct connection to your computer. Secondly, the error code 4
1576 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1577 chip ran into some sort of error - this points us to a USB problem.
1579 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1580 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1581 What does that mean and what might be the reason for this?
1583 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1584 has closed the connection to OpenOCD. This might be a GDB issue.
1586 @item In the configuration file in the section where flash device configurations
1587 are described, there is a parameter for specifying the clock frequency for
1588 LPC2000 internal flash devices (e.g.
1589 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1590 which must be specified in kilohertz. However, I do have a quartz crystal of a
1591 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1592 Is it possible to specify real numbers for the clock frequency?
1594 No. The clock frequency specified here must be given as an integral number.
1595 However, this clock frequency is used by the In-Application-Programming (IAP)
1596 routines of the LPC2000 family only, which seems to be very tolerant concerning
1597 the given clock frequency, so a slight difference between the specified clock
1598 frequency and the actual clock frequency will not cause any trouble.
1600 @item Do I have to keep a specific order for the commands in the configuration file?
1602 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1603 listed for the JTAG scan chain must be given in the right order (jtag_device),
1604 with the device closest to the TDO-Pin being listed first. In general,
1605 whenever objects of the same type exist which require an index number, then
1606 these objects must be given in the right order (jtag_devices, targets and flash
1607 banks - a target references a jtag_device and a flash bank references a target).
1609 @item Sometimes my debugging session terminates with an error. When I look into the
1610 log file, I can see these error messages: Error: arm7_9_common.c:561
1611 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP